CN114048161A - Communication integrated system for packaging circuit containing SPI communication protocol and I2C communication protocol - Google Patents
Communication integrated system for packaging circuit containing SPI communication protocol and I2C communication protocol Download PDFInfo
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- CN114048161A CN114048161A CN202111383255.7A CN202111383255A CN114048161A CN 114048161 A CN114048161 A CN 114048161A CN 202111383255 A CN202111383255 A CN 202111383255A CN 114048161 A CN114048161 A CN 114048161A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
Abstract
The invention discloses a communication integrated system for a packaging circuit containing an SPI communication protocol and an I2C communication protocol, which comprises a packaging integrated communication unit and a packaging integrated data communication unit, wherein the packaging integrated communication unit comprises a sequence code detection module, an enabling logic signal end, a data output end, an I2C data input end and an SPI data input end, the packaging integrated data communication unit comprises an input-output module and an input module, the input-output module comprises an enabling signal judgment end, a communication data output end and a first communication data input end, and the input module comprises a second communication data input end. The invention can realize the application of the integrated circuit containing the SPI and the I2C communication protocol, saves the chip area of the chip, reduces the packaging pins and controls the cost. The function of automatically judging the working communication protocol mode through the logic by checking the serial code of the sequence is realized. The protocol communication integration is realized through the original chip packaging pin, and the requirements of compatibility and flexible conversion of each working mode are met.
Description
Technical Field
The invention relates to a communication integrated system for a packaging circuit containing an SPI communication protocol and an I2C communication protocol, in particular to an internal protocol communication configuration integration in a semiconductor integrated circuit and a microelectronic special circuit, and belongs to the technical field of semiconductor packaging circuits.
Background
Semiconductor integrated circuit chips need to be packaged, play a role in placing, fixing, sealing, protecting the chips and enhancing the electric heating performance, and are also a bridge for communicating the internal world of the chips with external circuits. Therefore, the package plays an important role for both the CPU and other LSI integrated circuits.
With the development of low cost and high integration technology of integrated circuits, the design of saving package pins on a chip is required, so as to realize the requirements of saving the area and cost of the integrated circuit chip.
At present, SPI communication protocol and I2C communication protocol exist in chip communication, wherein the SPI communication protocol includes three-wire SPI communication protocol and four-wire SPI communication protocol, three-wire SPI communication protocol includes clock input port SCL, chip selection enable signal input port SCSB, two-way input and output end SDI, four-wire SPI communication protocol includes clock input port SCL, chip selection enable signal input port SCSB, input SDI, output SDO, I2C communication protocol includes two-way input and output end SDA, clock input port SCL.
Generally, in order to save the area and cost of an integrated circuit chip, a communication protocol is single, and cost control is realized by losing compatibility of the communication protocol, while in some chip designs requiring compatibility of an SPI communication protocol and an I2C communication protocol, independent communication protocol communication designs exist, so that the number of package pins is very large, and the area of a circuit chip is large.
Disclosure of Invention
The invention aims to solve the defects of the prior art, and provides a communication integrated system for a packaging circuit containing an SPI communication protocol and an I2C communication protocol, aiming at the problem that the single or multiple communication protocols of the traditional integrated circuit chip communication protocol independently cause the large area of multiple circuit current chips with the number of packaging pins.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
for a communication integrated system including an SPI communication protocol and I2C communication protocol encapsulation circuit,
comprises a package integrated communication unit and a package integrated data communication unit,
the packaging integrated communication unit comprises a serial code detection module for judging the working protocol mode, an enabling logic signal end for enabling the logic signal output, a data output end for outputting SPI communication protocol or I2C communication protocol data, an I2C data input end for inputting the I2C communication protocol data, and an SPI data input end for inputting the SPI communication protocol data,
the encapsulated integrated data communication unit comprises an input-output module and an input module,
the input/output module comprises an enabling signal judging end for receiving the enabling logic signal of the enabling logic signal end to carry out input or output judgment, a communication data output end connected with the data output end, and a first communication data input end connected with the I2C data input end,
the input module comprises a second communication data input end connected with the SPI data input end.
Preferably, the SPI communication protocol comprises a three-wire SPI communication protocol and a four-wire SPI communication protocol,
the packaged integrated communication unit comprises a second enabling logic signal terminal for enabling logic signal output by a three-wire SPI communication protocol, the data output terminal is shared by the three-wire SPI communication protocol, the four-wire SPI communication protocol and the I2C communication protocol, and the input and output module is shared by the three-wire SPI communication protocol and the I2C communication protocol.
Preferably, the sequence code detection module comprises a clock input end for inputting a clock command, an input code sequence input end for inputting a code sequence according to the clock input end scl, an analog signal end for generating an rstb signal, an initial end for judging a communication protocol, and a first communication protocol judging end for judging an SPI communication protocol and an I2C communication protocol in cooperation with the initial end.
Preferably, the sequence code detection module includes a second communication protocol determination end configured to perform three-wire SPI communication protocol and four-wire SPI communication protocol determination in cooperation with the initiation end prob.
The invention has the following beneficial effects:
1. the application of an integrated circuit containing SPI and I2C communication protocols can be realized, the tape-out area of a chip is saved, the packaging pins are reduced, and the cost is controlled.
2. The function of automatically judging the working communication protocol mode through the logic by checking the serial code of the sequence is realized.
3. The protocol communication integration is realized through the original chip packaging pin, and the requirements of compatibility and flexible conversion of each working mode are met.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 is a schematic diagram of a framework structure of a communication integration system including an SPI communication protocol and an I2C communication protocol encapsulation circuit according to the present invention.
FIG. 2 is a schematic structural diagram of a first embodiment of the communication integration system for a package circuit including an SPI communication protocol and an I2C communication protocol according to the present invention.
FIG. 3 is a schematic diagram of a second embodiment of the communication integration system according to the present invention, which is used for a package circuit containing an SPI communication protocol and an I2C communication protocol.
Fig. 4 is a schematic structural diagram of a serial code detection module in a communication integrated system including an SPI communication protocol and I2C communication protocol encapsulation circuit according to the present invention.
FIG. 5 is a timing diagram of a general communication protocol used in a communication integrated system including an SPI communication protocol and an I2C communication protocol encapsulation circuit according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the related invention are shown in the drawings. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
The invention provides a communication integrated system for a packaging circuit containing an SPI communication protocol and an I2C communication protocol, which is applied to an integrated circuit or a special circuit containing the SPI and the I2C communication protocol, and carries out communication between the corresponding circuit and other chips through an SPI or I2C interface, thereby meeting the characteristics of small area, high integration level, stream chip cost saving and the like.
The internal design of the integrated circuit uses the original working communication protocol, namely SPI and the clock signal working by I2C, the input or output port of the enable signal as the packaging pin on the chip, and uses the input sequence code of the corresponding pin to detect the working protocol mode, and uses the signal line for transmitting data as the packaging pin of the input and/or output port.
The special purpose circuit or integrated circuit design which is used for realizing the communication protocol with an external chip under a certain communication protocol mode and is used for specific contained SPI and I2C communication protocols and conforms to the correct data input and output protocol. The circuit design area is saved and the packaging pins are reduced. The working protocol mode is judged through the logic serial input sequence of the port signal, the serial code sequence input can be realized through the original input/output pin of the protocol, the judgment of the working protocol mode is realized through an internal digital circuit logic module, in addition, different serial sequence codes are input through the packaging port pin communicated by the SPI and the I2C protocol to work on the mutual switching of the three-wire SPI, the four-wire SPI and the I2C communication protocols, the packaging cost is saved, the area and the cost of a chip stream are reduced, and the purpose of saving the cost is achieved.
Example one
As shown in fig. 2, the communication device includes a package integrated communication unit and a package integrated data communication unit, wherein the package integrated communication unit includes a serial code detection module seq _ det for determining a working protocol mode, an enable logic signal end SPI _ miso _ en for enabling a logic signal to be output, a data output SPI _ miso _ o for outputting SPI communication protocol or I2C communication protocol data, an I2C data input SPI _ miso _ I for inputting I2C communication protocol data, and an SPI data input for inputting the SPI communication protocol data.
The packaging integrated data communication unit comprises an input/output module and an input module, wherein the input/output module comprises an enabling signal judgment end ien for receiving enabling logic signals of an enabling logic signal end SPI _ miso _ en to carry out input or output judgment, a communication data output end dout connected with a data output end SPI _ miso, and a first communication data input end din connected with an I2C data input end SPI _ miso _ I, and the input module comprises a second communication data input end din connected with an SPI data input end.
The specific implementation process and principle description are as follows:
first, the sequence code detection module seq _ det is explained, as shown in fig. 5, a communication protocol common to the SPI communication protocol and the I2C communication protocol is designed in the module, that is, the shared scl (sck) port is an input port of the clock working in the I2C or the SPI, and the shared chip select scsb (cs) port is an input port of the chip select enable signal working in the I2C or the SPI. The operating protocol mode is detected by the input sequence code.
The input/output module SDO is a bidirectional input/output port, and is enabled to be a high-level logic when ien is enabled to be used as a din input characteristic, and is enabled to be a low-level logic when ien is enabled to be used as a dout output characteristic.
The first embodiment is a connection scheme compatible with a four-wire SPI communication protocol and an I2C communication protocol.
Firstly, the protocol judgment of the four-wire type SPI communication protocol and the I2C communication protocol is carried out through the sequence code detection module seq _ det, so that the matched protocol communication connection is realized.
The spi _ miso _ en logic signal is a data input output enable signal which is controlled by the I2c _ sda _ en signal inside the I2c communication protocol in the I2C mode, i.e., the internal I2C protocol is related to controlling I2c communication; and under the four-wire SPI communication protocol mode, the SPI _ miso _ en logic signal is generated by enabling signal control of the working control data input and output of the SPI communication protocol.
The SPI _ miso _ o logic signal selects the communication protocol of the I2C to transmit data output when operating in the I2C communication protocol mode, and selects the communication protocol of the SPI to transmit data output when operating in the four-wire SPI communication protocol mode.
The SPI _ miso _ I logic signal is a data input signal in the working I2C communication protocol mode, and the SPI _ mosi _ I logic signal is a data input signal in the four-wire SPI communication protocol mode.
The ien signal controlling the input enable of the SDI port is internally tied high, i.e., SDI is the input pin. And the input and output enable signal of the control SDO is connected with the internal logic spi _ miso _ en, and the input and output characteristics of the pin I/O are controlled by the spi _ miso _ en.
When operating as communication under the I2C protocol, the spi _ miso _ en logic is a data enable signal for controlling the I2C input and output, the spi _ miso _ o is the data output logic of the I2C communication protocol to the SDO, and the spi _ miso _ I is the data input logic of the I2C communication protocol input from the SDO port. When the device works under the four-wire SPI communication protocol, namely the SPI _ miso _ en is an enabling signal for controlling the internal data of the SPI protocol to be output to the port SDO through the SPI _ miso _ o logic, and the SPI _ mosi is input through the port SDI for the data input of the SPI communication protocol.
Example two
As shown in fig. 3, the connection scheme is compatible with three-wire SPI communication protocol, four-wire SPI communication protocol and I2C communication protocol.
The packaged integrated communication unit comprises a second enabling logic signal end SPI _ out _ en for enabling logic signal output of the three-wire type SPI communication protocol, the data output end SPI _ miso _ o is shared by the three-wire type SPI communication protocol, the four-wire type SPI communication protocol and the I2C communication protocol, and the input and output module is shared by the three-wire type SPI communication protocol and the I2C communication protocol.
Specifically, the serial code detection module seq _ det performs protocol judgment of the three-wire SPI communication protocol, the four-wire SPI communication protocol, and the I2C communication protocol, thereby realizing matching protocol communication.
The working principle of the four-wire SPI communication protocol and the I2C communication protocol is the same as in the first embodiment.
When the three-wire SPI communication operation is carried out, the SPI _ out _ en signal is additionally designed in the original four-wire SPI communication protocol through the internal digital logic, the SPI _ out _ en controls the data input and output enable signal of the three-wire SPI communication protocol, the reading or writing SPI operation is judged according to the high address of the internal logic of the original four-wire SPI communication protocol, the SPI _ out _ en signal is high-level logic after the addr, namely the first byte, is completed in the reading operation through the internal digital logic, and the SPI _ out _ en signal is low-level logic at other moments. And controlling an SDO (three-wire SPI logic is combined into an SDIO) bidirectional port by the SPI _ out _ en, namely realizing the input of the original SDI port logic signal when the SDIO port carries out a write command, firstly taking the read command as the input of the original SDI port logic signal, reading an address, and then outputting the read command to the SDIO port as the SDO original logic signal when returning data.
In one embodiment, as shown in fig. 4, the serial code detection module seq _ det includes a clock input scl for inputting a clock command, an input code sequence input scsb for inputting a code sequence according to the clock input scl, an analog signal terminal rstb for generating an rstb signal, an initial terminal perb for communication protocol determination, a first communication protocol determination terminal I2c _ select for performing SPI communication protocol and I2C communication protocol determination in cooperation with the initial terminal prob, and a second communication protocol determination terminal SPI _ select for performing three-wire SPI communication protocol and four-wire SPI communication protocol determination in cooperation with the initial terminal prob.
The module is used for directly transmitting the input signals scl and scsb through the pins, so that the input of the input code sequence of the protocol work can be distinguished, and the probability of mistakenly identifying the input data in the working protocol mode can be reduced.
The serial code sequence input by a pin direct-through input signal scsb detects the scl input serial sequence code by using the scl as clock input, and can generate internally required rstb; the function of switching four-wire spi and three-wire spi through the input command detection sequence is realized; the signal i2c _ select is generated which selects either spi internally or the operating protocol i2c internally. And saving an extra rstb pin and a pin for judging whether spi is the protocol mode of i2c, wherein a seq _ det module input signal porb is directly input by an internal analog circuit POR signal to generate an initial value. scsb is used as an input sequence of clock sampling scl after the command is input by scl, and seq _ det detects the input sequence and generates a corresponding signal after judging that the original code and the complement code are correct.
Specifically, the scl input command generates the rstb signal: using a perb to generate an initial value, wherein the perb is 0, the rstb is 1, and when scl inputs serial commands bit 7-bit 0, the values are 01011011; the internal logic determines that the original code is 01011011 and the complement is 10100101, resulting in a logic with rstb of 0; when the input commands bit 7-bit 0: 10100110; the internal logic determines the original code to be 10100110 and the complement to be 01011010, resulting in a logic with an rstb of 1.
The scl input command generates a four-wire spi and three-wire spi interconverted signal: using PORB to generate initial value, PORB is 0, spi _ sel initialization value is 0, when the input commands bit7~ bit 0: 00111010, respectively; when the internal logic judges that the original code is 00111010 and the complement code is 11000110, the SPI _ sel is 0, and the four-wire SPI is obtained; when the input commands bit 7-bit 0: 11000111; the internal logic determines that the original code 11000111 and the complementary code are 00111001, SPI _ sel is 1, and the three-wire SPI is obtained.
The scl input command generates a signal for pattern recognition and translation of spi with i2 c: generating an initial value using PORB, PORB is 0, i2c _ select initialization value is 0, input commands bit 7-bit 0: 01101010, respectively; when the internal logic judges the original code is 01101010 and the judgment complement code is 10010110, i2c _ select is 0, and the mode is the spi mode; inputting commands bit 7-bit 0: 10010111; the internal logic determines the original code to be 10010111 and the complement to be 01101001, i2c _ select is 1, which is the i2c mode. All signals generated after command detection are once generated and remain unchanged until the corresponding input serial sequence code changing its value is detected again to change.
Through the above description, it can be found that the invention is used for the communication integrated system containing the SPI communication protocol and the I2C communication protocol packaging circuit, can realize the integrated circuit application containing the SPI and the I2C communication protocol, saves the chip area of the chip, reduces the packaging pins, and controls the cost. The function of automatically judging the working communication protocol mode through the logic by checking the serial code of the sequence is realized. The protocol communication integration is realized through the original chip packaging pin, and the requirements of compatibility and flexible conversion of each working mode are met.
The terms "comprises," "comprising," or any other similar term are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
So far, the technical solutions of the present invention have been described in connection with the preferred embodiments shown in the drawings, but it is easily understood by those skilled in the art that the scope of the present invention is obviously not limited to these specific embodiments. Equivalent changes or substitutions of related technical features can be made by those skilled in the art without departing from the principle of the invention, and the technical scheme after the changes or substitutions can fall into the protection scope of the invention.
Claims (4)
1. A communication integrated system for a circuit containing an SPI communication protocol and an I2C communication protocol package, characterized in that:
comprises a package integrated communication unit and a package integrated data communication unit,
the packaging integrated communication unit comprises a serial code detection module for judging the working protocol mode, an enabling logic signal end for enabling the logic signal output, a data output end for outputting SPI communication protocol or I2C communication protocol data, an I2C data input end for inputting the I2C communication protocol data, and an SPI data input end for inputting the SPI communication protocol data,
the encapsulated integrated data communication unit comprises an input-output module and an input module,
the input/output module comprises an enabling signal judging end for receiving the enabling logic signal of the enabling logic signal end to carry out input or output judgment, a communication data output end connected with the data output end, and a first communication data input end connected with the I2C data input end,
the input module comprises a second communication data input end connected with the SPI data input end.
2. The communication integration system for packaging circuitry including an SPI communication protocol and an I2C communication protocol according to claim 1, wherein:
the SPI communication protocol includes a three-wire SPI communication protocol and a four-wire SPI communication protocol,
the packaged integrated communication unit comprises a second enabling logic signal terminal for enabling logic signal output by a three-wire SPI communication protocol, the data output terminal is shared by the three-wire SPI communication protocol, the four-wire SPI communication protocol and the I2C communication protocol, and the input and output module is shared by the three-wire SPI communication protocol and the I2C communication protocol.
3. The communication integration system for packaging circuit containing SPI communication protocol and I2C communication protocol according to claim 1 or 2, characterized by:
the sequence code detection module comprises a clock input end used for inputting a clock instruction, an input code sequence input end used for inputting a code sequence according to the clock input end, an analog signal end used for generating an rstb signal, an initial end used for judging a communication protocol, and a first communication protocol judging end used for matching with the initial end to judge an SPI communication protocol and an I2C communication protocol.
4. The communication integration system for packaging circuitry including an SPI communication protocol and an I2C communication protocol according to claim 3, wherein:
the sequence code detection module comprises a second communication protocol judgment end which is used for being matched with the initial end to judge the three-wire SPI communication protocol and the four-wire SPI communication protocol.
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| CN101588171A (en) * | 2009-06-23 | 2009-11-25 | 广州润芯信息技术有限公司 | Can be simultaneously compatible three-way and the digital control interface device of four line SPI working forms |
| CN105208034A (en) * | 2015-10-09 | 2015-12-30 | 中国兵器工业集团第二一四研究所苏州研发中心 | SPI bus and CAN bus protocol converting circuit and method |
| CN112804128A (en) * | 2021-03-25 | 2021-05-14 | 广州智慧城市发展研究院 | Bus control system and method supporting multiple protocols |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101588171A (en) * | 2009-06-23 | 2009-11-25 | 广州润芯信息技术有限公司 | Can be simultaneously compatible three-way and the digital control interface device of four line SPI working forms |
| CN105208034A (en) * | 2015-10-09 | 2015-12-30 | 中国兵器工业集团第二一四研究所苏州研发中心 | SPI bus and CAN bus protocol converting circuit and method |
| CN112804128A (en) * | 2021-03-25 | 2021-05-14 | 广州智慧城市发展研究院 | Bus control system and method supporting multiple protocols |
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