CN101588171A - Can be simultaneously compatible three-way and the digital control interface device of four line SPI working forms - Google Patents
Can be simultaneously compatible three-way and the digital control interface device of four line SPI working forms Download PDFInfo
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- CN101588171A CN101588171A CNA2009100404413A CN200910040441A CN101588171A CN 101588171 A CN101588171 A CN 101588171A CN A2009100404413 A CNA2009100404413 A CN A2009100404413A CN 200910040441 A CN200910040441 A CN 200910040441A CN 101588171 A CN101588171 A CN 101588171A
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Abstract
The invention discloses a kind of can be simultaneously compatible three-way and the digital control interface device of four line SPI working forms.Comprise SPI control module and data buffer, control operation is read and write to the SPI module to RF chip internal register, comprise the control input end of clock, control enables input, the control data input, the control data output, five I/O ports of control data Enable Pin, data buffer is provided with output buffer (201), input buffer (202) and control data enable line, the control data output output of SPI module is through the output of output buffer (201) buffering, the control data input of SPI module is buffered into through input buffer (202), and the control data enable line controls output buffer (201) by the signal of input and input buffer (202) is opened and turn-offed.The present invention only needs simple configuration in the integrated circuit (IC) chip outside, just can control rfic chip inside with three-way or four linear formulas.
Description
Technical field
The invention belongs to the technical field of the digital control interface that communication base band integrated circuit (IC) chip controls rfic chip, specifically be meant a kind of can be compatible three-way simultaneously and the digital control interface device of four line SPI working forms.。
Background technology
At present, the base-band digital chip need be controlled and observe radio frequency chip internal register in communication system, needs a kind of common interface standard and carries out the communication of chip chamber.In order to lower the quantity of control line in the communication, simplify the configuration difficulty, realize the short distance high-speed communication between the chip, therefore adopted SPI (Serial Peripheral Interface--serial peripheral interface) control interface.The transmission rate of present SPI interface bus can reach more than tens Mbps, and SPI control interface form mainly contains three-way and four line structures.In four line structures, the control circuit that comprises has the control clock line of sclk (Serial Clock) for the clock output of primary module, the beginning of address part signal transmission in register manipulation and the read register operation and the control enable line of end are write in sen (Serial Enable) control, mosi (Master Output, Slave Input) primary module is write from the module controls data wire, miso (Master Input, Slave Output) primary module is read from the module controls data wire.In the four-wire interface form, what control interface adopted is semiduplex mode of operation, the read operation and the write operation that use control data line separately radio frequency IC internal register to be carried out serial.In order further to lower control line quantity, the digital interface of some chip adopts is that the synchronous three-way serial control interface form of a kind of full duplex (emission data and a control line that receives data are controlled, merged into a control data line) is used for the register of radio frequency IC interior is carried out the read operation and the write operation of serial.The SPI interface is because standard and interface sequence are various, the interface shape difference, the chip interface form for different need provide the corresponding interface structural arrangements, but so its expanded configuration performance lower, the scope of application of interface is restricted.
Summary of the invention
The object of the present invention is to provide that a kind of to realize possessing three-way radio-frequency (RF) digital control interface function, configuration with two kinds of forms of four lines on same chip simple, easy to use can be compatible three-way simultaneously and the digital control interface device of four line SPI working forms.
For solving the problems of the technologies described above, the technical solution used in the present invention is: can be simultaneously compatible three-way and the digital control interface device of four line SPI working forms, comprise SPI control module and data buffer, control operation is read and write to described SPI module to RF chip internal register, comprise the control input end of clock, control enables input, the control data input, the control data output, five I/O ports of control data Enable Pin, described data buffer is provided with output buffer, input buffer and control data enable line, the control data output output of described spi module is through the output of output buffer buffering, the control data input of spi module is buffered into through input buffer, and described control data enable line controls output buffer by the signal of input and input buffer is opened and turn-offed.
The present invention also comprises the hour hands buffer, and the control input end of clock of described spi module is through the input of hour hands buffer buffers.
The present invention also comprises enable buffer, and the control data Enable Pin of described spi module is through the input of enable buffer buffering.
Owing to adopted above-mentioned structure, the present invention has realized the compatibility function of the digital control interface of SPI of three-way and four linear formulas, strengthened the accommodation of radio frequency chip, only need simple configuration in the integrated circuit (IC) chip outside, just can control rfic chip inside with three-way or four linear formulas.
Description of drawings
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in further detail.
Fig. 1 is a SPI control module logic diagram;
Fig. 2 is a data buffer modular structure block diagram;
Fig. 3 is three-way and four lines configuration block diagram;
Fig. 4 is three-way and the four-wire compatible configuration structure;
Fig. 5 is three-way and four-wire compatible extends block diagram.
Embodiment
As shown in Figure 1, described SPI module meets the working forms of four line SPI control, and major function is that control operation is read and write to RF chip internal register, and it has five I/Oinput/output ports, comprising:
Input: sclkSPI Clock controls input end of clock, is used for synchronous sdata_i and sdata_o data-signal, controls its sample frequency;
Input: senSPI Enable control enables input;
Input: sdata_iSPI Data Input control data input, be used for transmitting the data content of control signal of the needs of concrete radio frequency integrated circuit inside, comprise the read-write flag bit, address bit and data bit;
Output: sdata_oSPI Data Output control data output is used for transmitting the data content of concrete radio frequency integrated circuit internal register;
Output: sdata_en (SPI Data Enable) control data Enable Pin is used to control the operating state on sdata_i and the sdata_o data wire.
As shown in Figure 2, described data buffer is provided with output buffer 201, input buffer 202 and control data enable line, the Data_buf module is as the buffer area of chip internal and external pin input signal, and paired domination number carries out ternary buffering control according to input on the line and output function.The data buffer port is still keeping two input FPDP, two dateout ports:
Sdata_o control data output line is exported through output buffer BufO201 buffering from the output of spi module controls data output end;
Sdata_i control data incoming line cushions the control data input that inputs to the spi module by the external pin input through input buffer BufI202.
These two buffer have ternary function, and when the control Enable Pin signal of buffer was high level, buffer opened, the output channel state; When the control Enable Pin signal of buffer was low level, buffer turn-offed, and output is in high-impedance state, and ternary control line wherein is control data enable line sdata_en.The concrete logic of Data_buf module is: when reading the internal register operation by the sdata_i Data In-Line, the process internal logic is the sdata_en home position signal, at this moment sdata_en control data enable line is a high level, buffer BufO201 opens, data are exported by the sdata_o DOL Data Output Line, and buffer BufI202 turn-offs, and the sdata_i data wire is in high-impedance state; When reading the internal register end of operation by the sdata_i Data In-Line, internal logic resets the sdata_en signal, at this moment sdata_en control data enable line is a low level, buffer BufO201 turn-offs, sdata_o data wire output high resistant, and buffer BufI202 opens, and the sdata_i data wire just can be operated by the read-write register that BufI202 carries out next time like this.Therefore come Sdata_en control data enable line just is configured and can controls the state of inputoutput data line effectively by the mode of operation of SPI module.
As shown in Figure 4, the outer three-way and four line collocation methods realization of SPI interface chip, the digital control interface of SPI is integrated in radio frequency chip inside, Chip Packaging becomes four linear formulas, by of the control of the inner paired domination number of SPI, disposed the mutual translation function that just can realize three-way 302 and four line 301 interface shapes in chip exterior according to state on the line.In addition, also set up hour hands buffer and enable buffer, the control input end of clock of described spi module is through the input of hour hands buffer buffers, and the control data Enable Pin of described spi module is through the input of enable buffer buffering.
Under the default configuration, the digital control interface of SPI is encapsulated as four port pinouts, interface is in four lines, 301 mode of operations, control data can be by outside sdata_i pin input control data and sdata_o pin output control data, and this moment, data buffer Data_Buffer401 can both allow sdata_i and sdata_o be in path or off state effectively.
Four lines change three-way configuration, simply, be connected with four lines 302 shown in the configuration block diagram as Fig. 3 three-way 302, particularly in Fig. 4, only need be connected two pins of sdata_i and sdata_o in chip exterior, so just, merge into single line sdata, because internal data buffer Data_Buffer402 can control the operating state on the sdata line effectively, so utilize single sdata data wire just can have input/output function simultaneously, thereby two lines are transferred to a line, and whole SPI interface transfers three-way 403 controls to by 402 controls of four lines.
Identical, three-way 403 change 402 configurations of four lines, also only need disconnect the line between sdata_i that has connected and sdata_o in chip exterior, and the data wire that utilizes sdata_i and sdata_o to be used as SPI write operation and read operation respectively gets final product again.Whole three-way structured flowchart with four-wire compatible SPI is three-way with shown in the four-wire compatible configuration structure as accompanying drawing 4.
More than such conversion configurations simple and practical, compatible performance is good, has solved chip chamber effectively because of the inconsistent problem that can't dock control of interface shape.
As shown in Figure 5, the compatible invention of described SPI three or four linear formulas is further extended, add buffer switch BufSwBuffer Switch501 at chip internal, the unlatching and the shutoff of specifying BufSw501 by the digital control interface configuration radio frequency chip of outside SPI internal register, thereby being connected and disconnection of control sdata_o and sdata_i.
Concrete enforcement is configured to: select suitable type of attachment according to the control chip interface shape in the connection of chip exterior.When docking with three-wire interface, carry out with three-way form in the connection, need initialization chip internal SPI to be set to three-way state of a control, specifically can control inner BufSw501 by input data line sdata_i input control data opens, thereby sdata_i is connected with sdata_o at chip internal, the data wire sdata_i of this moment has just possessed the reception data function of sdata_o simultaneously, and three-way like this function has just been opened; When chip docks with four-wire interface, carry out with four linear formulas in the connection, need initialization chip internal SPI to be set to four line traffic control states, specifically can control inner BufSw501 by data wire sdata_i input control data turn-offs, at this moment Wai Bu four lines maintain the connection, and so just can use as four-wire interface.What more than the configuration implementation process only needed is to carry out three-way and four line function selecting by the digital control interface of SPI to the radio frequency chip internal, just can realize three-way and switchings four line functions.
In a word; though the present invention has exemplified above-mentioned preferred implementation, should illustrate, though those skilled in the art can carry out various variations and remodeling; unless such variation and remodeling have departed from scope of the present invention, otherwise all should be included in protection scope of the present invention.
Claims (3)
- One kind can be simultaneously compatible three-way and the digital control interface device of four line SPI working forms, comprise SPI control module and data buffer, control operation is read and write to described SPI module to RF chip internal register, comprise the control input end of clock, control enables input, the control data input, the control data output, five I/O ports of control data Enable Pin, it is characterized in that: described data buffer is provided with output buffer (201), input buffer (202) and control data enable line, the control data output output of described spi module is through the output of output buffer (201) buffering, the control data input of spi module is buffered into through input buffer (202), and described control data enable line controls output buffer (201) by the signal of input and input buffer (202) is opened and turn-offed.
- According to claim 1 is described can be simultaneously compatible three-way and the digital control interface device of four line SPI working forms, it is characterized in that: also comprise the hour hands buffer, the control input end of clock of described spi module is through the input of hour hands buffer buffers.
- According to claim 1 or 2 described can be simultaneously compatible three-way and the digital control interface device of four line SPI working forms, it is characterized in that: also comprise enable buffer, the control data Enable Pin of described spi module is through the input of enable buffer buffering.
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| CNA2009100404413A CN101588171A (en) | 2009-06-23 | 2009-06-23 | Can be simultaneously compatible three-way and the digital control interface device of four line SPI working forms |
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| CNA2009100404413A CN101588171A (en) | 2009-06-23 | 2009-06-23 | Can be simultaneously compatible three-way and the digital control interface device of four line SPI working forms |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101958936A (en) * | 2010-09-21 | 2011-01-26 | 四川长虹电器股份有限公司 | Digital interface-based data transmission system and method |
| CN102929820A (en) * | 2011-12-30 | 2013-02-13 | 广东佳和通信技术有限公司 | SPI communication device compatible with single/dual wires and communication method thereof |
| CN104978294A (en) * | 2015-06-18 | 2015-10-14 | 珠海市杰理科技有限公司 | Compatible device of serial peripheral interface, serial peripheral interface and host device |
| CN106649159A (en) * | 2016-12-23 | 2017-05-10 | 中国电子科技集团公司第五十四研究所 | Radio-frequency assembly and special SPI data transmission method thereof |
| CN103746942B (en) * | 2013-11-26 | 2017-06-27 | 苏州智汇谱电子科技有限公司 | A kind of gate controlled switch device |
| CN114036096A (en) * | 2021-11-04 | 2022-02-11 | 珠海一微半导体股份有限公司 | Read controller based on bus interface |
| CN114048161A (en) * | 2021-11-22 | 2022-02-15 | 苏州聚元微电子股份有限公司 | Communication integrated system for packaging circuit containing SPI communication protocol and I2C communication protocol |
-
2009
- 2009-06-23 CN CNA2009100404413A patent/CN101588171A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101958936A (en) * | 2010-09-21 | 2011-01-26 | 四川长虹电器股份有限公司 | Digital interface-based data transmission system and method |
| CN101958936B (en) * | 2010-09-21 | 2013-05-08 | 四川长虹电器股份有限公司 | Digital interface-based data transmission system and method |
| CN102929820A (en) * | 2011-12-30 | 2013-02-13 | 广东佳和通信技术有限公司 | SPI communication device compatible with single/dual wires and communication method thereof |
| CN103746942B (en) * | 2013-11-26 | 2017-06-27 | 苏州智汇谱电子科技有限公司 | A kind of gate controlled switch device |
| CN104978294A (en) * | 2015-06-18 | 2015-10-14 | 珠海市杰理科技有限公司 | Compatible device of serial peripheral interface, serial peripheral interface and host device |
| CN104978294B (en) * | 2015-06-18 | 2018-11-16 | 珠海市杰理科技股份有限公司 | Compatible equipment, Serial Peripheral Interface (SPI) and the host equipment of Serial Peripheral Interface (SPI) |
| CN106649159A (en) * | 2016-12-23 | 2017-05-10 | 中国电子科技集团公司第五十四研究所 | Radio-frequency assembly and special SPI data transmission method thereof |
| CN106649159B (en) * | 2016-12-23 | 2019-03-15 | 中国电子科技集团公司第五十四研究所 | A kind of radio frequency component and its dedicated SPI data transmission method |
| CN114036096A (en) * | 2021-11-04 | 2022-02-11 | 珠海一微半导体股份有限公司 | Read controller based on bus interface |
| CN114036096B (en) * | 2021-11-04 | 2024-05-03 | 珠海一微半导体股份有限公司 | Read controller based on bus interface |
| CN114048161A (en) * | 2021-11-22 | 2022-02-15 | 苏州聚元微电子股份有限公司 | Communication integrated system for packaging circuit containing SPI communication protocol and I2C communication protocol |
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