CN114039601A - Signal sampling circuit and target positioning method - Google Patents
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Abstract
The application discloses a signal sampling circuit and a target positioning method, relates to the technical field of circuits, does not need an analog-to-digital converter, and can reduce the power consumption of the signal sampling circuit. A signal sampling circuit, comprising: a sensor unit; each group of n-level comparators is used for receiving sampling signals of the same sensor unit, wherein n is a natural number larger than 1, reference signal values accessed by comparators at different stages are different, and reference signal values accessed by comparators at the same stage between the n-level comparators in different groups are the same; a first switching device disposed between the comparators of adjacent two stages.
Description
Technical Field
The present application relates to the field of circuit technologies, and in particular, to a signal sampling circuit and a target positioning method.
Background
At present, information processing by using a digital signal processing system has become a common application, but various real objects or signals in a real environment are usually analog signals, and an analog-to-digital conversion circuit is needed in a signal sampling circuit to complete conversion from the analog signals to the digital signals.
However, in the conventional signal sampling circuit, in order to increase the sampling rate, each sampling channel is connected to an ADC (analog-to-digital converter) to convert an analog signal into a digital signal, which causes signal data of all sampling channels to be analog-to-digital converted at the same time, resulting in large power consumption of the signal sampling circuit.
Disclosure of Invention
The embodiment of the application provides a signal sampling circuit and a target positioning method, an analog-to-digital converter is not needed, and the power consumption of the signal sampling circuit can be reduced.
In a first aspect of embodiments of the present application, a signal sampling circuit is provided, including:
a sensor unit;
each group of n-level comparators is used for receiving sampling signals of the same sensor unit, wherein n is a natural number larger than 1, reference signal values accessed by comparators of different levels are different, and the reference signal values accessed by the comparators of the same level between the n-level comparators of different groups are the same;
a first switching device disposed between the comparators of adjacent two stages.
In some embodiments, the signal sampling circuit further comprises:
and the output control unit is electrically connected with the output end of each comparator.
In some embodiments, a second switching device is disposed between the output control unit and the output terminal of each of the comparators.
In some embodiments, the signal sampling circuit further comprises:
a memory cell electrically connected to the output terminal of each of the comparators through the second switching device.
In some embodiments, the signal sampling circuit further comprises:
and the reference signal control unit is electrically connected with the reference signal input end of each stage of the comparator.
In some embodiments, a third switching device is disposed between the reference signal control unit and the reference signal input terminal of the comparator of each stage.
In some embodiments, the reference signal value is a reference voltage value, and a voltage dividing unit is disposed between reference voltage input terminals of two adjacent stages of the comparators, and the voltage dividing unit includes a resistor.
In some embodiments, the sensor unit includes a sensor and a current-to-voltage converter electrically connected between the sensor and each of the n-stage comparators.
In some embodiments, the current-to-voltage converter includes a resistor, one end of the resistor is used for grounding, and the other end of the resistor is connected between the sensor and each group of the n-stage comparators.
In some embodiments, the signal sampling circuit further comprises:
and the data processing unit is electrically connected with the output end of each comparator respectively.
In some embodiments, the signal sampling circuit further comprises:
and the fourth switching device is arranged between the sensor unit and the sampling signal input end of each comparator, and the data processing unit is used for controlling the fourth switching device to be switched on and switched off.
In some embodiments, the first switching device comprises a MOS transistor.
In a second aspect of the embodiments of the present application, there is provided a target positioning method using the signal sampling circuit according to the first aspect, the method including:
controlling a sensor unit to sample a target object to obtain a sampling signal;
the 1 st-stage comparator performs comparison operation according to the sampling signal and the reference signal value and outputs a comparison result;
the comparison result output by the n-1 th-stage comparator controls the on and off of a first switching device between the n-1 th-stage comparator and the nth-stage comparator;
and determining the sampling positions of the sensor units corresponding to all comparison results output by the kth-level comparator as target positions, wherein k is more than or equal to 1 and less than or equal to n.
In some embodiments, before determining that the sampling positions of the sensor unit corresponding to all comparison results output by the kth stage comparator are target positions, the method further includes:
traversing a result array based on a set array size to select a target array, wherein the result array comprises the comparison results output by each of the comparators of the same rank, the target array being determined based on a number and a location of target results in the target array;
controlling a next-stage comparator corresponding to the target array to perform comparison operation;
the determining that the sampling positions of the sensor units corresponding to all comparison results output by the kth-stage comparator are target positions includes:
determining the sampling position of a target sensor as the target position, wherein the target sensor is determined by the target result in the target array corresponding to the k-th stage comparator.
In some embodiments, the set array size for selecting the target array for each stage of the comparator is different.
The signal sampling circuit and the target positioning method provided by the embodiment of the application receive sampling signals of the same sensor unit by setting each group of n-stage comparators, reference signal values accessed by different stages of comparators are different, a first switch device is arranged between two adjacent stages of comparators, a comparison result output by a previous stage of comparator can control the on and off of a corresponding first switch device, only a next stage of comparator corresponding to the closed first switch device continues to perform comparison operation, the next stage of comparator corresponding to the disconnected first switch device does not perform comparison operation, only part of the next stage of comparator performs comparison operation, and the rest of the next stage of comparator does not perform comparison operation, so that the power consumption of the sampling circuit can be saved, and unnecessary power consumption waste is avoided. In addition, reference signal values accessed by comparators in different stages are different, so that sampling signals of each sensor unit are compared step by step, target sampling signal ranges can be screened out in the step-by-step comparison process of all the sampling signals, the sampling positions of the target sampling signals corresponding to the sensor units can be further locked, the position of a target object is further obtained, the positioning and tracking function can be realized, an analog-to-digital converter is not needed, only the comparators of partial sampling channels run, and the electric energy consumption of simultaneously performing analog-to-digital conversion on all the sampling channels in the existing sampling circuit can be avoided. The occupied area of the n-stage comparator is smaller than that of an analog-to-digital converter of the multi-channel sampling circuit in the prior art, and the occupied area of the sampling circuit can be reduced.
Drawings
Fig. 1 is a schematic structural block diagram of a signal sampling circuit provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of another signal sampling circuit provided in an embodiment of the present application;
fig. 3 is a schematic flowchart of a target positioning method provided in an embodiment of the present application;
fig. 4 is a schematic diagram illustrating a comparison result of outputs of an n-stage comparator according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a target array provided by an embodiment of the present application;
fig. 6 is a schematic diagram illustrating a comparison result of outputs of another n-stage comparator according to an embodiment of the present application.
Detailed Description
In order to better understand the technical solutions provided by the embodiments of the present specification, the technical solutions of the embodiments of the present specification are described in detail below with reference to the drawings and specific embodiments, and it should be understood that the specific features in the embodiments and examples of the present specification are detailed descriptions of the technical solutions of the embodiments of the present specification, and are not limitations on the technical solutions of the embodiments of the present specification, and the technical features in the embodiments and examples of the present specification may be combined with each other without conflict.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element. The term "two or more" includes the case of two or more.
At present, information processing by using a digital signal processing system has become a common application, but various real objects or signals in a real environment are usually analog signals, and an analog-to-digital conversion circuit is needed in a signal sampling circuit to complete conversion from the analog signals to the digital signals. However, in the conventional signal sampling circuit, in order to increase the sampling rate, each sampling channel is connected to an ADC to convert an analog signal into a digital signal, which causes the signal data of all the sampling channels to be analog-to-digital converted at the same time, resulting in large power consumption of the signal sampling circuit.
In view of this, embodiments of the present disclosure provide a signal sampling circuit and a target positioning method, which can reduce power consumption of the signal sampling circuit without using an analog-to-digital converter.
In a first aspect of an embodiment of the present application, a signal sampling circuit is provided, and fig. 1 is a schematic structural block diagram of the signal sampling circuit provided in the embodiment of the present application. As shown in fig. 1, a signal sampling circuit provided in an embodiment of the present application includes: the sensor unit 100, the sensor unit 100 may be a photosensitive sensor, a pressure-sensitive sensor, a temperature sensor, etc., and the embodiment of the present application is not particularly limited. An n-stage comparator 200, where n is a natural number greater than 1, and in the n-stage comparator shown in fig. 1, for example, n is 3, that is, a 3-stage comparator; each group of n-level comparators 200 is configured to receive sampling signals of the same sensor unit 100, where the reference signal values accessed by the comparators of different levels are different, and the reference signal values accessed by the comparators of the same level between the n-level comparators 200 of different groups are the same; and a first switching device 300, the first switching device 300 being disposed between adjacent two stages of comparators.
For example, as shown in fig. 1, the signal sampling circuit may include a plurality of sets of n-stage comparators 200, and fig. 1 shows a 3-stage comparator, so that n-3 is taken as an example for description. Each set of n-stage comparators 200 includes a 1 st stage comparator 210, a 2 nd stage comparator 220, and a 3 rd stage comparator 230; the reference signal values inputted to the reference signal input terminals c of all the same-stage comparators of all the groups of n-stage comparators 200 are the same, that is, all the 1 st-stage comparators 210 are inputted to the first reference signal Ref1, all the reference signal input terminals c of the 2 nd-stage comparators 220 are inputted to the second reference signal Ref2, and all the reference signal input terminals c of the 3 rd-stage comparators 230 are inputted to the third reference signal Ref 3; the reference signal values accessed by the comparators of different stages are different, i.e., the values of the first reference signal Ref1, the second reference signal Ref2, and the third reference signal Ref3 may be different. The sampling signal input end e of each comparator in the n-level comparators 200 in the same group is connected to the same sensor unit 100, a first switching device 300 is disposed between two adjacent comparators, and the specific first switching device 300 may be disposed between the output end of the comparator in the previous level and the sampling signal input end of the comparator in the next level, it should be noted that the comparator in the previous level is a comparator relatively close to the sensor unit 100 in the two adjacent comparators, the comparator in the next level is a comparator relatively far away from the sensor unit 100, for example, between the comparator 210 in the 1 st level and the comparator 220 in the 2 nd level, the comparator 210 in the 1 st level is a comparator in the previous level, and the comparator 220 in the 2 nd level is a comparator in the next level. Specifically, one first switching device 300 is disposed between each 1 st-stage comparator 210 and each 2 nd-stage comparator 220, the 1 st-stage comparator 210, the 2 nd-stage comparator 220 and the first switching device 300 are in a one-to-one relationship, one first switching device 300 is disposed between each 2 nd-stage comparator 220 and each 3 rd-stage comparator 230, and the 2 nd-stage comparator 220, the 3 rd-stage comparator 230 and the first switching device 300 are in a one-to-one relationship. The number of comparators, the number of first switching devices 300, the number of sensor units 100, and the value of n shown in fig. 1 are all schematic and are not intended to be specific limitations of the embodiments of the present application.
The working principle of the signal sampling circuit shown in fig. 1 is exemplarily illustrated:
all the sensor units 100 perform synchronous sampling, each sensor unit 100 obtains a corresponding sampling signal, the sampling signal is input into the 1 st-stage comparator 210 through a sampling signal input end e of the correspondingly connected 1 st-stage comparator 210, all the 1 st-stage comparators 210 perform comparison operation according to a first reference signal Ref1 and the correspondingly input sampling signal to obtain a 1 st-stage comparison result, the 1 st-stage comparison result can be output through an output end b of the 1 st-stage comparator 210, and the 1 st-stage comparison result output by the 1 st-stage comparator 210 can control the on and off of the first switching device 300 correspondingly connected to the output end b. If the 1 st-stage comparison result output by the 1 st-stage comparator 210 controls the corresponding first switching device 300 to be turned on, the corresponding sensor unit 100 and the sampling signal input end e of the corresponding 2 nd-stage sensor 220 are turned on through the turned-on first switching device 300, and the corresponding 2 nd-stage comparator 220 may perform a comparison operation according to the second reference signal Ref2 and the corresponding input sampling signal to obtain a 2 nd-stage comparison result; if the 1 st-stage comparison result output by the 1 st-stage comparator 210 controls the corresponding first switching device 300 to be turned off, the sampling signal input end e of the corresponding 2 nd-stage comparator 220 does not receive the sampling signal, and the corresponding 2 nd-stage comparator 220 does not perform the comparison operation. Likewise, the stage 2 comparison result may control the closing and opening of the first switching device between the stage 2 comparator 220 and the stage 3 comparator 230. If the 2 nd-level comparison result output by the 2 nd-level comparator 220 controls the corresponding first switching device 300 to be closed, the corresponding sensor unit 100 and the sampling signal input end e of the corresponding 3 rd-level sensor 230 are turned on through the closed first switching device 300, and the corresponding 3 rd-level comparator 230 may perform a comparison operation according to the third reference signal Ref3 and the corresponding input sampling signal, so as to obtain a 3 rd-level comparison result; if the 2 nd-stage comparison result output by the 2 nd-stage comparator 220 controls the corresponding first switching device 300 to be turned off, the sampling signal input end e of the corresponding 3 rd-stage comparator 230 does not receive the sampling signal, and the corresponding 3 rd-stage comparator 230 does not perform the comparison operation, at this time, the 3 rd-stage comparison result output by all the 3 rd-stage comparators 230 is the final sampling result.
It should be noted that, the comparison results output by the comparators of the same stage may partially control the first switching device 300 to be turned on, and partially control the first switching device 300 to be turned off, for example, 3 of the 1 st comparison results output by all the comparators of the 1 st comparator 210 may control the corresponding first switching device 300 to be turned on, and the remaining 1 st comparison results all control the corresponding first switching device 300 to be turned off, so that the 2 nd comparator 220 corresponding to the first switching device 300 that is turned on may perform the comparison operation, and the 2 nd comparator 220 corresponding to the first switching device 300 that is turned off may not perform the comparison operation, and the comparator that may not perform the comparison operation may be considered as not operating, and may not occupy the power consumption of the circuit. The values of the first reference signal Ref1, the second reference signal Ref2 and the third reference signal Ref3 are different from each other, and the first reference signal Ref1 is greater than the second reference signal Ref2 and the second reference signal Ref2 is greater than the third reference signal Ref3 according to the sampling requirement, so that the sampling signals can be compared and output step by step in an n-stage comparator to obtain a final comparison result, and by adopting the sampling signal processing mode, the target object can be position-tracked, that is, the number of the sensor units 100 corresponding to each stage of comparison result is reduced step by step, the sampling position of the sensor unit 100 corresponding to the final comparison result can be used as the position-tracking position of the target object, the sampling signals which are not within the range of the target sampling signal are eliminated, the corresponding comparator does not need to operate, and the comparator corresponding to the step-by-step selected sampling signal is retained for comparison operation, the operation of unnecessary comparators can be reduced, the power consumption of a sampling circuit is saved, and the position range of a target object corresponding to the target sampling signal range can be obtained without using an analog-to-digital converter. It is easy to understand that the target sampling range can be a signal range set according to the sampling purpose, and the target object is the sampling object found according to the need of localization tracking. For example, a possible application scenario is to positionally track the eyeball with a photosensitive sensor in a VR device.
Illustratively, the comparison result output by each comparator may be 0 or 1, for example, when the sampling signal is greater than the reference signal value, the comparison result output is 1, otherwise the comparison result output is 0, or when the sampling signal is less than the reference signal value, the comparison result output is 1, otherwise the comparison result output is 0, the analog sampling signal may be converted into a digital signal, and the n-stage comparator 200 may replace the analog-to-digital converter. The sampling signal may be a current signal or a voltage signal, and the corresponding reference signal may be a current signal or a voltage signal, which is not particularly limited in the embodiments of the present application. Each sensor unit 100 and the corresponding connected group of n-stage comparators 200 can form one sampling channel, and a plurality of sensor units 100 correspondingly form a plurality of sampling channels. The occupied area of the comparator is smaller than that of the analog-to-digital converter, so that in a circuit meeting the requirement of multi-channel sampling, the occupied area of the n-stage comparator in the embodiment of the application is smaller than that of the analog-to-digital converter.
The signal sampling circuit provided by the embodiment of the application receives the sampling signal of the same sensor unit 100 by setting each group of n-level comparators 200, the reference signal values accessed by the comparators of different levels are different, the first switch device 300 is arranged between the adjacent two-level comparators, the comparison result output by the previous-level comparator can control the on-off of the corresponding first switch device 300, only the next-level comparator corresponding to the closed first switch device 300 continues to perform the comparison operation, the next-level comparator corresponding to the disconnected first switch device 300 does not perform the comparison operation, only part of the next-level comparator performs the comparison operation, and the rest of the next-level comparator does not perform the comparison operation, so that the power consumption of the sampling circuit can be saved, and unnecessary power consumption waste is avoided. In addition, reference signal values accessed by comparators in different stages are different, so that sampling signals of each sensor unit 100 are compared step by step, target sampling signal ranges can be screened in the step-by-step comparison process of all the sampling signals, the sampling positions of the target sampling signals corresponding to the sensor units can be further locked, the position of a target object is further obtained, the positioning and tracking function can be realized, analog-to-digital converters are not needed, only the comparators of partial sampling channels run, and the electric energy consumption of simultaneously performing analog-to-digital conversion on all the sampling channels in the existing sampling circuit can be avoided. The occupied area of the n-stage comparator 200 is smaller than that of the analog-to-digital converter of the multi-channel sampling circuit in the prior art, so that the occupied area of the sampling circuit can be reduced.
In some embodiments, fig. 2 is a schematic block diagram of another signal sampling circuit provided in an embodiment of the present application. As shown in fig. 2, for example, the sensor unit 100 employs a photodiode D, the first switching device 300 employs a first MOS transistor M1, and specifically, the first MOS transistor M1 illustrated in fig. 2 is a PMOS, and the characteristics of the PMOS are that a low level is turned on, a high level is turned off, the first MOS transistor M1 is turned on, that is, the first switching device is turned on, and the first MOS transistor M1 is turned off, that is, the first switching device is turned off. For example, the output end of the previous-stage comparator is connected to the gate of the first MOS transistor M1, the source of the first MOS transistor M1 is connected to the photodiode D, the drain of the first MOS transistor M1 is connected to the sampling signal input end e of the next-stage comparator, when the comparison result output by the previous-stage comparator is 0, the corresponding first MOS transistor M1 can be controlled to be turned on, the source and the drain of the first MOS transistor M1 are turned on, and the sampling signal input end e of the next-stage comparator can receive the sampling signal to perform the comparison operation; when the comparison result output by the previous-stage comparator is 1, the corresponding first MOS transistor M1 can be controlled to be turned off, the source and the drain of the first MOS transistor M1 are in an off state, and the sampling signal input end e of the next-stage comparator cannot receive the sampling signal, so that the comparison operation is not performed. The application scenario of the signal sampling circuit illustrated in fig. 2 may be an eyeball tracking application in a VR device, and the photodiode D may sense light reflected by an eyeball, and may generate current change according to the intensity of the reflected light, so as to implement an application of identifying the position of the eyeball. Specifically, an infrared light source can be arranged, the eyeball reflects infrared light, and the intensity of reflected light at the eyeball position is different from the intensity of reflected light at other positions, so that the current change of the photodiode D is different, and a related sampling signal of the eyeball position can be obtained. The structure of the signal sampling circuit shown in fig. 2 is merely illustrative and is not intended to be a specific limitation of the embodiments of the present application.
In some embodiments, with continuing reference to fig. 2, the signal sampling circuit provided in this embodiment of the present application may further include: and an output control unit 400, wherein the output control unit 400 is electrically connected with the output end b of each comparator. The output control unit 400 may be configured to control whether the comparison result output by each comparator can be output to the storage unit for storage, where the storage may be temporary storage or normal storage, and the embodiment of the present application is not limited in particular. For example, the output control of the output control unit 400 for the comparison result may be implemented by a controller and a switching device, and a second switching device is disposed between the output control unit 400 and the output terminal b of each comparator.
In some embodiments, the signal sampling circuit provided in the embodiments of the present application further includes: and the storage unit is electrically connected with the output end of each comparator through a second switching device. The output control unit 400 may select the comparison result output by any one of the comparators as the final sampling result for output. For example, all comparison results output by the 1 st-stage comparator may be used as output results of the signal sampling circuit, and the output control unit 400 may control, by using the controller, the turn-on of the second switching device connected to the output terminal b of the 1 st-stage comparator 210, and then all comparison results output by the 1 st-stage comparator 210 are output to the storage unit through the turned-on second switching device for storage. If all the comparison results output by the 3 rd-stage comparator 230 are taken as the output results of the signal sampling circuit, the second switching device connected to the output end b of the 3 rd-stage comparator 230 may be controlled to be turned on, and the turning on or off of the second switching device corresponding to the 1 st-stage comparator 210 and the second switching device corresponding to the 2 nd-stage comparator 220 may be specifically set according to sampling requirements, which is not specifically limited in the embodiment of the present application.
The signal sampling circuit that this application embodiment provided through setting up output control unit 400, can select the comparison result of arbitrary grade comparator output as final sampling result and export, and the collection of sampling signal is more nimble, can set for the comparator progression of output according to concrete needs, and signal sampling circuit's compatibility is stronger.
In some embodiments, the signal sampling circuit provided in the embodiments of the present application further includes: and the reference signal control unit is electrically connected with the reference signal input end of each stage of comparator. The reference signal control unit may implement input control of the reference signal by a switching device, for example, a third switching device is provided between the reference signal control unit and the reference signal input terminal of each stage of the comparator. The reference signal control unit can control the on and off of the third switching device through the controller to control whether the reference signal is input to the reference signal input end of each stage of comparator, so as to control whether each stage of comparator operates. For example, the reference signal input ends of all comparators of each stage of comparator may be correspondingly connected to the same third switching device, and whether the corresponding comparators of the same stage perform the comparison operation is controlled by controlling the on or off of the corresponding third switching device, if no reference signal is input, the comparators cannot perform the comparison operation, and if a reference signal is input, the comparators have the condition for performing the comparison operation. Therefore, the reference signal control unit and the third switching device may control whether the corresponding comparator is turned on or not.
The signal sampling circuit provided by the embodiment of the application can control whether the comparator which is correspondingly connected can carry out comparison operation or not by controlling the input of the reference signal through setting the reference signal control unit and the third switching device, thereby realizing the operation control of the comparator, being capable of enabling the comparator which does not need to carry out comparison operation to be in a non-operation state such as a dormant state, avoiding the invalid operation of the comparator and saving the power consumption of the circuit.
In some embodiments, the reference signal value is a reference voltage value, and a voltage dividing unit is disposed between the reference voltage input terminals of two adjacent stages of comparators, and includes a resistor. The reference signal compared by the comparator in the signal sampling circuit provided by the embodiment of the present application may be a voltage signal, or may also be a current signal or other signal, and the embodiment of the present application is exemplarily illustrated by a voltage signal. When the reference signal is a voltage signal, the reference voltage value input to each stage of comparator may be different, and if the first switching device is a PMOS, the corresponding reference voltage value decreases or increases step by step with the increase of the stage number of the comparator, which mainly depends on the comparison logic of the comparator. When the reference voltage value is reduced along with the increase of the number of the comparator stages, a voltage division unit needs to be arranged between the reference voltage values input by the comparators of two adjacent stages, a simpler voltage division device can be a resistor, and the resistor voltage division is more conventional. The resistor in the voltage dividing unit can divide a part of the reference voltage input by the comparator of the previous stage, and the reference voltage input by the comparator of the next stage is smaller than the reference voltage input by the comparator of the previous stage.
The signal sampling circuit that this application embodiment provided sets up the partial pressure unit through between the reference voltage input of adjacent two-stage comparator, and the partial pressure unit includes resistance, realizes that the reference voltage value of different grades of comparator input is different, and circuit structure realizes simple circuit structure easily.
In some embodiments, the sensor unit includes a sensor and a current-to-voltage converter electrically connected between the sensor and each of the n-stage comparators. If the reference signal is a voltage signal, the sampling signal input in the comparator also needs to be a voltage signal, and usually, the sampling signal collected by the sensor unit is a current signal, and a current-voltage converter is needed to convert the current signal into a voltage signal. The current-to-voltage converter may include a resistor having one end connected to ground and the other end connected between the sensor and each of the n-stage comparators. The current value sampled by the sensor can be converted into a voltage signal through the resistor with one end grounded, namely the potential at the connecting point of the sensor and the other end of the resistor is the sampled voltage signal.
The signal sampling circuit that this application embodiment provided sets up current-voltage converter and converts the current signal that the sensor was gathered into voltage signal, and current-voltage converter can be realized through one end ground connection, other end connection sensor's resistance, simple structure, and is with low costs and realize easily.
In some embodiments, the signal sampling circuit provided in the embodiments of the present application further includes: and the data processing unit is electrically connected with the output end of each comparator respectively. A fourth switching device may be disposed between the sensor unit and the sampling signal input terminal of each comparator, and the data processing unit is configured to control the fourth switching device to be turned on and off. The data processing unit may be configured to analyze and process the comparison result stored in the storage unit, and the data processing unit may be electrically connected to the storage unit, or the storage unit and the data processing unit are arranged in the same circuit module to perform memory sharing, and then the data processing unit is directly connected to the output end of each comparator to obtain the comparison result. The data processing unit can control the on or off of the fourth switching devices of the sampling signal input ends of the rest comparators according to the analysis result of the current comparison result, and can control the corresponding fourth switching devices to be off if the rest comparators are controlled according to the current analysis result without comparison operation, so that the corresponding comparators cannot receive the sampling signals and cannot perform the comparison operation.
For example, with continued reference to fig. 2, the second switching device may also employ a MOS transistor, i.e., a second MOS transistor M2, and the output control unit 400 is connected to the gate of each second MOS transistor M2 for controlling the second MOS transistor M2 to be turned on and off. The source of the second MOS transistor M2 is connected to the output terminal b of the corresponding comparator, and the drain d of the second MOS transistor M2 can be connected to the storage unit or to a module shared by the storage unit and the data processing unit, because the space is limited, the number of lines is too many, and fig. 2 does not show the connection relationship of the drain of the second MOS transistor M2, nor the storage unit and the data processing unit. The current-voltage converter may include a first resistor R1, one end of the first resistor R1 is grounded, and the other end of the first resistor R1 is connected to the photodiode D, so that the current change of the photodiode D may be converted into the potential change of the connection point of the first resistor R1 and the photodiode D, that is, the voltage change of the common potential point Q, the current signal of the sampling signal may be converted into the voltage signal, and the voltage value of the common potential point Q is input from the sampling signal input terminal e of the comparator. A second resistor R2 is disposed between the reference signal input terminal c of the 1 st-stage comparator 210 and the reference signal input terminal c of the 2 nd-stage comparator 220, a third resistor R3 is disposed between the reference signal input terminal c of the 2 nd-stage comparator 220 and the reference signal input terminal c of the 3 rd-stage comparator 230, and the second resistor R2 and the third resistor R3 are corresponding voltage dividing units for implementing different values of the reference voltage signals input to each stage of comparator. The total reference voltage is REF, a first reference signal REF1 is input to the 1 st-stage comparator 210 through voltage division of the fifth resistor R5, a second reference signal REF2 is obtained through voltage division of the second resistor R2 again and is input to the 2 nd-stage comparator 220, a third reference signal REF3 is obtained through voltage division of the third resistor R3 again and is input to the 3 rd-stage comparator 230, the reference signal input end c of each stage of comparator is connected to the third switching device SR, the third switching device SR may be a MOS transistor, and the embodiment of the present invention is not particularly limited. The fourth resistor R4 can also be regarded as a voltage divider, and cooperates with the third resistor R3 to provide the third reference signal Ref3 to be inputted to the 3 rd stage comparator 230. Fig. 2 does not show the fourth switching device and the data processing unit, the fourth switching device may be a MOS transistor, and the embodiment of the present application is not particularly limited. The dashed line shown in fig. 2 may represent a sampling target, to which the photodiode D is directed for signal sampling. The MOS tube is used as a switch device, so that the control is easy, the control precision is high, the device performance is mature, and the circuit integration is easy to realize.
The signal sampling circuit provided by the embodiment of the application can realize the comparison operation of the comparator or the dynamic adjustment of result output by setting at least one of the first switch device, the output control unit, the second switch device, the reference signal control unit, the third switch device, the data processing unit and the fourth switch device, can realize the quick positioning of the target object, and can save the energy consumption of the circuit.
In a second aspect of the embodiments of the present application, a target positioning method is provided, where the signal sampling circuit according to the first aspect is applied, and fig. 3 is a schematic flowchart of the target positioning method provided in the embodiments of the present application. As shown in fig. 3, a target positioning method provided in the embodiment of the present application includes:
s100: and controlling the sensor unit to sample the target object to obtain a sampling signal. The sampling signal may be a voltage signal, a current signal, or other signal, and the embodiments of the present application are not limited in particular. The sensor unit is controlled to sample a target object, if the sensor unit comprises a photosensitive diode, the step can be a process of electrifying the signal sampling circuit, the photosensitive diode can automatically sense ambient light, the comparator is electrified, a reference signal is input into the comparator, and the comparator can perform comparison operation of the sampling signal and the reference signal. Or a switch is arranged on the sensor unit to control whether the sensor unit operates or not, and the embodiment of the present application is not particularly limited.
S200: and the 1 st-stage comparator performs comparison operation according to the sampling signal and the reference signal value and outputs a comparison result. The comparison operation of the 1 st-stage comparator may be performed automatically, and the comparison operation may be performed as long as the first reference signal Ref1 and the sampling signal are input into the 1 st-stage comparator, resulting in a comparison result. The operation of the comparator may also be controlled by controlling the input of the reference signal, and the embodiment of the present application is not particularly limited.
S300: the comparison result output by the n-1 st comparator controls the closing and opening of the first switching device between the n-1 st comparator and the nth comparator. The n-1 th comparator may be a comparator of a previous stage in two adjacent stages, and the nth comparator may be a comparator of a next stage. The comparison result output by the comparator in the previous stage can control the on and off of the first switching device between the two adjacent stages of comparators.
S400: and determining sampling positions of the sensor units corresponding to all comparison results output by the kth-stage comparator as target positions, wherein k is more than or equal to 1 and less than or equal to n. In the signal sampling circuit for target positioning, the comparison result output by any one stage of comparator can be determined as the final target positioning sampling result according to the setting or according to the analysis of the comparison result of the existing output. K is less than or equal to 1 and less than or equal to n, the k-th stage comparator can be any stage comparator, and the number of comparators for comparison operation of the k-th stage comparator can be less than or equal to the number of 1-th stage comparators due to the setting of the first switching device.
Illustratively, referring to fig. 2, the first switching device is a PMOS, and the result output by each comparator is either 0 or 1. 0 may be used as the target comparison result for target positioning. For example, fig. 4 is a schematic diagram illustrating a comparison result of outputs of an n-stage comparator according to an embodiment of the present application. With reference to fig. 2 and 4, all the sensor units 100 form a 7 × 7 array, and each corresponding comparator of the stages may also form a 7 × 7 array, so that the 1 st comparison result output by the 1 st comparator 210 may form a 1 st result array (7 × 7 array), according to the indication of the 1 st result array, only the four comparators in the 1 st result array output the comparison result of 0, the corresponding 2 nd comparator 220 will continue the comparison operation of the sampling signal of the sampling channel, only the four comparators in the 2 nd comparator output the comparison result, and the comparison result output by the 2 nd comparator may have 2 bits, that is, the first bit is the comparison result output by the 1 st comparator, and the second bit is the comparison result output by the 2 nd comparator itself. As shown in fig. 4, if only one of the 2 nd-stage result arrays output by the 2 nd-stage comparator is 0, the 2 nd-stage comparator may be used as an output comparator for final target positioning, and the 2 nd-stage comparator is finally determined as a sampling result for final target positioning, where k is 2, the sensor unit corresponding to the comparator whose comparison result is 00 output in the fourth row and the fourth column in the 7 × 7 array may be regarded as a target sensor, and the positioning information of the sampling signal corresponding to the target sensor may be the position information of the target object, thereby completing target positioning. Under the action of the first switching device, the 2 nd-stage comparator corresponding to the 1 st-stage comparator with the output result of 1 does not need to perform comparison operation, so that the power consumption of the signal sampling circuit can be saved, and meanwhile, the signal processing efficiency can be improved.
The target positioning method provided by the embodiment of the application utilizes the signal sampling circuit of the first aspect, each group of n-stage comparators 200 is arranged to receive sampling signals of the same sensor unit 100, the reference signal values accessed by the comparators of different stages are different, the first switch device 300 is arranged between the two adjacent stages of comparators, the comparison result output by the previous stage of comparator can control the on and off of the corresponding first switch device 300, only the next stage of comparator corresponding to the closed first switch device 300 continues to perform the comparison operation, the next stage of comparator corresponding to the disconnected first switch device 300 does not perform the comparison operation, only part of the next stage of comparator performs the comparison operation, and the rest of the next stage of comparator does not perform the comparison operation, so that the power consumption of the sampling circuit can be saved, and unnecessary power consumption waste is avoided. In addition, reference signal values accessed by comparators in different stages are different, so that sampling signals of each sensor unit 100 are compared step by step, target sampling signal ranges can be screened in the step-by-step comparison process of all the sampling signals, the sampling positions of the target sampling signals corresponding to the sensor units can be further locked, the position of a target object is further obtained, the positioning and tracking function can be realized, analog-to-digital converters are not needed, only the comparators of partial sampling channels run, and the electric energy consumption of simultaneously performing analog-to-digital conversion on all the sampling channels in the existing sampling circuit can be avoided. The occupied area of the n-stage comparator 200 is smaller than that of the analog-to-digital converter of the multi-channel sampling circuit in the prior art, so that the occupied area of the sampling circuit can be reduced.
In some embodiments, before step S400, the method may further include:
traversing the result array based on the set array size to select a target array, wherein the result array comprises comparison results output by each of the same level comparators, and the target array is determined based on the number and position of the target results in the target array.
For example, fig. 5 is a schematic diagram of a target array provided in an embodiment of the present application. As shown in fig. 5, for example, the comparison result output by the comparator of the 1 st stage forms a result array of the 1 st stage, and if the set array size may be 4 × 4, the size of the target array is 4 × 4, and the target result is 0. The target array may be determined to be the target array by traversing the level 1 result array at an array size of 4 x 4, finding the middle position of the target result in the set size array, and the largest number of target results in the array.
And controlling the next-stage comparator corresponding to the target array to perform comparison operation. The next-stage comparator corresponding to the target array can be controlled to carry out comparison operation through the data processing unit, other comparators do not carry out comparison operation, time for target positioning can be saved, the next-stage comparator corresponding to the sampling signal with small correlation is closed, and circuit energy consumption is saved. The target array may be selected in the 1 st-stage comparator in a traversal manner, or may be selected in a comparison result output by any one stage of comparator, and the embodiment of the present application is not particularly limited.
Step S400, including:
and determining the sampling position of the target sensor as the target position, wherein the target sensor is determined by the target result in the target array corresponding to the k-th-stage comparator. The target result in the target array corresponding to the comparator as the final target positioning is the final target result, the sensor corresponding to the target result is the target sensor, the sampling position corresponding to the target sensor is the position of the target object, and the target positioning can be completed.
According to the target positioning method provided by the embodiment of the application, the target array is selected in a mode of traversing the result array, the position range of the target object can be limited, unnecessary comparators can be closed, the circuit energy consumption is not occupied, and the signal sampling circuit has low energy consumption.
In some embodiments, the set array size for the selected target array is different for each stage of comparators. The size of the target array can be reduced step by step as the number of comparator steps is increased. For example, fig. 6 is a schematic diagram of a comparison result of an output of another n-stage comparator provided in an embodiment of the present application. Taking eye tracking of the VR device as an example, as shown in fig. 5 and 6, the size of the target array corresponding to the 1 st stage result array is 4 × 4, the size of the target array corresponding to the 2 nd stage result array is 4 × 2, the result output by the comparator is 0, which can be characterized as a sampling signal corresponding to an eye, the target result is 0, the signal sampling circuit needs to screen the comparison result 0 step by step, and finally, if the comparison result output by 2 comparators in the 3 rd stage result array is 0, there are 2 target results in the 3 rd stage result array, if the 3 rd stage comparator is used as a comparator for final target positioning, the sensors corresponding to the two target results can be taken as target sensors, that is, the sensor corresponding to the 3 rd stage comparator output the comparison result of 000 is taken as a target sensor, and there are two 000 in the 3 rd stage result array, the sampling positions of the two target sensors take the central value as position information of the target object, namely, the central value of the corresponding sampling position of the sensor in the 4 th row and the 4 th column and the sensor in the 5 th row and the 4 th column in the sensor array is the positioning information of the target object, and the positioning of the target object is completed. The selection process and the data analysis process of the target array can be completed by using the data processing unit, the next-stage comparator corresponding to the target array is not subjected to comparison operation, and the fourth switching device can be controlled by the data processing unit to complete the closing control of the comparator. The data processing unit may be provided with a microcontroller therein, and the embodiment of the present application is not particularly limited.
According to the target positioning method provided by the embodiment of the application, the set array sizes which are corresponding to each stage of comparator and used for selecting the target array are different, the sizes of different target arrays can be selected in the result arrays output by different stages of comparators according to the characteristics of the target object, the range of the sampling signal of the target object is gradually limited, the target object can be positioned more accurately, all comparators do not need to be started to operate, other comparators except the next stage of comparator corresponding to the target array are closed, and circuit energy consumption is saved.
While preferred embodiments of the present specification have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all changes and modifications that fall within the scope of the specification.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present specification without departing from the spirit and scope of the specification. Thus, if such modifications and variations of the present specification fall within the scope of the claims of the present specification and their equivalents, the specification is intended to include such modifications and variations.
Claims (15)
1. A signal sampling circuit, comprising:
a sensor unit;
each group of n-level comparators is used for receiving sampling signals of the same sensor unit, wherein n is a natural number larger than 1, reference signal values accessed by comparators of different levels are different, and the reference signal values accessed by the comparators of the same level between the n-level comparators of different groups are the same;
a first switching device disposed between the comparators of adjacent two stages.
2. The signal sampling circuit of claim 1, further comprising:
and the output control unit is electrically connected with the output end of each comparator.
3. The signal sampling circuit of claim 2, wherein a second switching device is disposed between the output control unit and the output of each of the comparators.
4. The signal sampling circuit of claim 3, further comprising:
a memory cell electrically connected to the output terminal of each of the comparators through the second switching device.
5. The signal sampling circuit of claim 1, further comprising:
and the reference signal control unit is electrically connected with the reference signal input end of each stage of the comparator.
6. The signal sampling circuit according to claim 5, wherein a third switching device is provided between the reference signal control unit and the reference signal input terminal of the comparator of each stage.
7. The signal sampling circuit according to claim 1, wherein the reference signal value is a reference voltage value, and a voltage dividing unit is disposed between reference voltage input terminals of two adjacent stages of the comparators, and the voltage dividing unit includes a resistor.
8. The signal sampling circuit of claim 1, wherein the sensor unit comprises a sensor and a current-to-voltage converter electrically connected between the sensor and each set of the n-stage comparators.
9. The signal sampling circuit of claim 8, wherein the current-to-voltage converter comprises a resistor, one end of the resistor is connected to ground, and the other end of the resistor is connected between the sensor and each group of the n-stage comparators.
10. The signal sampling circuit of claim 1, further comprising:
and the data processing unit is electrically connected with the output end of each comparator respectively.
11. The signal sampling circuit of claim 10, further comprising:
and the fourth switching device is arranged between the sensor unit and the sampling signal input end of each comparator, and the data processing unit is used for controlling the fourth switching device to be switched on and switched off.
12. The signal sampling circuit of claim 1, wherein the first switching device comprises a MOS transistor.
13. A method for object localization, using a signal sampling circuit according to any one of claims 1 to 12, the method comprising:
controlling a sensor unit to sample a target object to obtain a sampling signal;
the 1 st-stage comparator performs comparison operation according to the sampling signal and the reference signal value and outputs a comparison result;
the comparison result output by the n-1 th-stage comparator controls the on and off of a first switching device between the n-1 th-stage comparator and the nth-stage comparator;
and determining the sampling positions of the sensor units corresponding to all comparison results output by the kth-level comparator as target positions, wherein k is more than or equal to 1 and less than or equal to n.
14. The method of claim 13, wherein before determining that the sampling positions of the sensor units corresponding to all comparison results output by the k-th comparator are target positions, the method further comprises:
traversing a result array based on a set array size to select a target array, wherein the result array comprises the comparison results output by each of the comparators of the same rank, the target array being determined based on a number and a location of target results in the target array;
controlling a next-stage comparator corresponding to the target array to perform comparison operation;
the determining that the sampling positions of the sensor units corresponding to all comparison results output by the kth-stage comparator are target positions includes:
determining the sampling position of a target sensor as the target position, wherein the target sensor is determined by the target result in the target array corresponding to the k-th stage comparator.
15. The method of claim 14, wherein the set array size for selecting the target array is different for each stage of the comparator.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2092666A1 (en) * | 1993-04-27 | 1994-10-28 | William Martin Snelgrove | Self-calibration technique for high-speed two-stage and pipelined multi-stage analog-to-digital converters |
| US20160336949A1 (en) * | 2015-05-12 | 2016-11-17 | Teledyne Scientific & Imaging, Llc | Comparator circuits with constant input capacitance for a column-parallel single-slope adc |
| CN112349316A (en) * | 2019-08-06 | 2021-02-09 | 北京知存科技有限公司 | Read-out unit for memory cell array and integrated memory chip including the same |
-
2021
- 2021-11-03 CN CN202111310151.3A patent/CN114039601A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2092666A1 (en) * | 1993-04-27 | 1994-10-28 | William Martin Snelgrove | Self-calibration technique for high-speed two-stage and pipelined multi-stage analog-to-digital converters |
| US20160336949A1 (en) * | 2015-05-12 | 2016-11-17 | Teledyne Scientific & Imaging, Llc | Comparator circuits with constant input capacitance for a column-parallel single-slope adc |
| CN112349316A (en) * | 2019-08-06 | 2021-02-09 | 北京知存科技有限公司 | Read-out unit for memory cell array and integrated memory chip including the same |
Non-Patent Citations (2)
| Title |
|---|
| YAN HUA MA等: "Optimal design of 10-bit single-slope ADC for CMOS image sensor based on swarm intelligent optimization algorithm", IET CIRCUITS，DEVICES，SYSTEMS, 5 April 2021 (2021-04-05), pages 787 - 802 * |
| 俞侃等: "高性能单片机C8051F020在车辆监控方面的应用", 计算机与数字工程, 20 March 2005 (2005-03-20), pages 65 - 68 * |
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