CA2092666A1 - Self-calibration technique for high-speed two-stage and pipelined multi-stage analog-to-digital converters - Google Patents
Self-calibration technique for high-speed two-stage and pipelined multi-stage analog-to-digital convertersInfo
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- CA2092666A1 CA2092666A1 CA 2092666 CA2092666A CA2092666A1 CA 2092666 A1 CA2092666 A1 CA 2092666A1 CA 2092666 CA2092666 CA 2092666 CA 2092666 A CA2092666 A CA 2092666A CA 2092666 A1 CA2092666 A1 CA 2092666A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
- H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
- H03M1/0607—Offset or drift compensation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
- H03M1/069—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy by range overlap between successive stages or steps
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
- H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
- H03M1/167—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
- H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
- H03M1/362—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider
- H03M1/365—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider the voltage divider being a single resistor string
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
The self-calibration technique presented in this disclosure is designed for high-speed two-stage and pipelined multi-stage A/D converters (ADCs), and n is absolutely unique in world-wide literature or markets at the time of this application. The technique is found to be very helpful in improving the conventional design of the ADCs toward higher speed, lower power dissipation and smaller device size by reducing stringent component-mismatching requirement in designing very large scale integration (VLSI) ADC chips. The technique provides a non-switched-capacitor (non-SC) robust alternative for VLSI implementation of critical parts in two-stage and pipelined multi-stage ADCs.
The technique comprises an adaptive offset shaping technique for flash A/D subconverters (ADSCs) of all stages and residue-based error correction technique for digital-to-analog subconverters (DASCs) of all stages in two-stage or pipelined multi-stage ADCs. The critical part of the adaptive offset shaping technique for ADSCs is an adaptive self-trimming process. The self-trimming process is delta-modulation based, and is carried out at each time instant by adjusting voltage thresholds of two successive comparators in an ADSC when digital output from the lower one is set to HIGH. Gain error in interstage sample-and-held amplifier (SHA) of a two-stage or pipelined multi-stage ADC can be automatically counteracted during the threshold self-trimming. The residue-based error correction technique uses overflow/underflow code information obtained from quantizing a residue signal from each previous subconversion stage of a two-stage or pipelined multi-stage ADC, and the threshold errors of ADSC and DASC in the previous stage are corrected solely based upon overflow and underflow of the residue signal.
The self-calibration technique presented in this disclosure is designed for high-speed two-stage and pipelined multi-stage A/D converters (ADCs), and n is absolutely unique in world-wide literature or markets at the time of this application. The technique is found to be very helpful in improving the conventional design of the ADCs toward higher speed, lower power dissipation and smaller device size by reducing stringent component-mismatching requirement in designing very large scale integration (VLSI) ADC chips. The technique provides a non-switched-capacitor (non-SC) robust alternative for VLSI implementation of critical parts in two-stage and pipelined multi-stage ADCs.
The technique comprises an adaptive offset shaping technique for flash A/D subconverters (ADSCs) of all stages and residue-based error correction technique for digital-to-analog subconverters (DASCs) of all stages in two-stage or pipelined multi-stage ADCs. The critical part of the adaptive offset shaping technique for ADSCs is an adaptive self-trimming process. The self-trimming process is delta-modulation based, and is carried out at each time instant by adjusting voltage thresholds of two successive comparators in an ADSC when digital output from the lower one is set to HIGH. Gain error in interstage sample-and-held amplifier (SHA) of a two-stage or pipelined multi-stage ADC can be automatically counteracted during the threshold self-trimming. The residue-based error correction technique uses overflow/underflow code information obtained from quantizing a residue signal from each previous subconversion stage of a two-stage or pipelined multi-stage ADC, and the threshold errors of ADSC and DASC in the previous stage are corrected solely based upon overflow and underflow of the residue signal.
Description
2~266~ `
A NOVEL SELF-CALIBRATION TECHNIQUE
FOR HIGH-SPEED TWO-STAGE AND PIPELINED MULTI~STAGE ADCS
The present invention is primarily designed for correcting static or slowly-evolving random errors in high-speed two-stage and pipelined multi-step analogue-to-dbnal converters (ADCs), although it can be used for other purposes. The invention comprises two parts, anrJ these two parts are applied to critical parls of a high-speed two-stage or pipelined multi-stage ADC: AID
subconverters (ADSCs), D/A subconverters (DASCs) and interstage sample-and-held amplifiers (SHAs).
Several types of self-calibration techniques for a stand-alone ADSC are currently available in market or in literature, but they are enher operated on-line by use of switched-capacnor (SC) techniques or off-line by use of some memory-based compensation techniques. Examples of these techniques can be found in References 11]¦2] (on-line techniques) and Reference 131 (ff-line techniques).
~=;
111. H.Ohaa, H.X.Ngo, M.J.Armstrong, C.F.Rahim, and P.R.Gray, ~A CMOS programmable self-calibrabng 13-bit ebht-channel data acqulsl~on perlpherar, IEEE Joumal of Solid-Stale Circuits, Vol.SC-22, No.6, Dec.19~7.
121. Y.M.Um, B.Klm and P.R.Gray, ~A 13-b 2.~MHz self calibrated r*elined A/D xn\terter in ~fU m CMOS~. IEEE Jounal of SoUd Stab Circuits, Vol.26, No.4, April 1991.
131. A.C.Dent and C.F.N.Cowan, ~Unearizabon of analog t~di9iEIl converters~, IEEE Transaction on Circuits and Sysbms, Vol.37, No.6, pp72~737, Oc~ 1990.
These available 1echniques have many disadvantages. The SC-based on-line self-calibratbn techniques forADSCs are restricted to each individual analog comparator block of an ADSC and use a set of clock signals to control its self-calibration processes. While the SC
cbcking processes of the techniques are complicated, the SC circuitry to which these clocking processes correspond reduces the input impedance of an ADSC and also takes a considerable 30 amount of die areas. As the common characteristics that these techniques share is that the SC
error-correction operates in a signal-forward-path and the error correction for each entire comparator offset error is made within one single clock duty cycle, the sampling speed of an ADSC which uses the SC techniques is limited by these techniques to around 50 MHz and the best resolution that it can achieve is around 1 mV. These SC techniques thus do not allow us to take full advantages of the current trend of scaling-down VLSI technologies in order to have smaller transistor skes, to reduce power dissipation and to allow for higher operational speed.
7he memory-based off-line compensation techniques for ADSCs requires a precise measurement of the nonlinearity of each ADSC anr~ the subsequent storage of the ADSC
40 nonlinearity data to a memory. The nonlinearity data is then used to compensate the ADSC
- 2~926g~ ~
nonlinearity during its normal conversion process. ADC chips with these off-line techniques can not adapt to parameter drifts due to temperature change and component aging during their operation.
There are a very limaed number of self-calibration techniques which are currently available for random errors in DASCs and interstage SHAs of a two-stage or pipelined multi-stage ADC.
In most cases, therefore, the conversion accuracy of DASCs and interstage SHAs depends upon a careful layout and thus is usually limited to below 10-bit resolution. -Therefore, it is very desirable to have a self-calibration technique for ADSCs which can be operated on-line, and of which the calibration process does not constrain the operational speerl of ADSCs. Of course, it would be superior if the self-calibration technique can also be applied on-line to correct random errors in DASCs and interstage SHAs. The present invention is ~ -intended to achieve all of these goals.
The present invention mainly consists of two closely-related calibration techniques:
adaptive offset shaping technique for ADSCs and residue-based e~ror correction technique for -:
DASCs. The former technique automatically counteracts gain errors of interstage SHAs in two-stage and pipelined multi-stage ADCs during as adaptive operation.
The adaptive offset shaping technique for ADSCs mainly involves a seH-trimming process and interaction between the process and a conventional digital error correction technique for an ADSC. An ordinary standard ADSC usualb consists of an array of latched differential-pair comparators. The difference between threshold voltages of two successive comparators is called quantkation interval. The basic concept of correcting random offset errors in a single differential-pair latched comparator, which is adopted in the present invention, is to balance :
biasing current in two sides of ~he differen1ial-pair comparator and in so doing compensate for offset errors. For the error conection, an extra adjustable current source may be added to one side ot the comparator circuitry so that adjusting current in the extra current source is equivalent 30 to adjusting the threshold voltage of the comparator (several types of such current-trimming circuas are currently available in literature or in market). The self-trimming process for an ADSC
is therefore realked by connecting a simple feedback loop to each of these threshold-adjustable comparators to form a cbse~bop block, and then interconnecting these closerl-bop blocks together in a way described below.
. , . ,, -. . . . ,, . . .. ~ ... .
~ 20926~6 The simple feedback loop alone for a comparator may comprise some digital logic circuitry, an analogue adder and an analogue integrator. (Or it may comprise an UP/DOWN
digital counter and D/A converter.) The input of the digital logic circuitry is connected to the output of the comparator, and its output connected to two analogue adcfers, one for this comparator and the other for that is above this comparator in the comparator array. The output from the adWer for this comparator is connected to an analogue integrator, and the output from the integrator connected to a current-trimming circuit mentioned above.
The first part of the invention, as exemplified by a preferred embocfiment, is described with reference to Figures 1A&1 B in Summary of Drawings:
Figure lA shows the structure of an adaptive offset-shaped flash ADSC in contrast to a standard ADSC shown in Figure 1B, wherein: vh(t) is the unknown analogue input at time t to the ADSC, which is to be converled by the ADSC; x,(t) is the threshold voltage of i - th comparator in the ADSC; x,(O) is the initial threshoW
voltage of i - th comparator, which contains unwanted random offset error at time t = O; the error signal e, (t) iS the difference signal between the analogue input vln(t) and the threshold x,(t); q,(t) is the two-level output (or called thermometer code outpu~ from the i - th comparator; g,(t) is the analogue output from the integrator of the i - th comparator; B,(t) is the binary output from the dbital logic circuitry.
Refening to the drawing, the embodiment of the first part of the invention shown, an adaptive offset shaping ADSC 10 comprises an anay of two-level analogue comparators 12, an array of feedback integrators 14, an array of current-trimming circuits 16, some digital logic circuitry 18 represented in Figure 1A by an array of "exclusive-or" gates (in practice, NAND-gates are usually used), an array of analogue aWers 20. Each comparator block 22 can also be considered as a pseudo delta-modulator.
The operation of the seH-trimming process for an ADSC, which is implemented by the 30 structure described above and shown in Figure 1A, can be mathematically expressed as:
For ea~h individual quantkation interval, e.g., i - th interval where i~[LN] (N is the number of quantizatbn intervals of the ADSC), if x, l ( t ) S Vh (t ) ~ x, (t ), x,,(t+T)=x, l(t)+~"; xl(t+T)=x,(t)-~". (1) 2092~
with the two end conditions: x0 (t) = -OO and XN (t) = + for all time t . In the above equation, ~"
is a small adaptation step (measured in volts) for the self-trimming.
The second part of the present invention, the residue-based error correction technique for DASCs, is realized by making use of residue overflow/underflow information from conventional digital error correction circuitry.
The conventional digital error correclion is applied a~ an ADSC in a two-stage or pipelined multi-stage ADC to digitally correct nonlinearity error resulting from the previous subconversion stage, and its circuitry comprises a group of digital logic gates of various types. The information that 1he digital error correction process needs for its operation is overllow/underflow code, which reflects whether the overranging of a residue signal from 1he previous s1age occurs.
Overfbw/underflow code is contained in digital output codes, which result from quantking 1he residue signal. The digital error correction process takes the overflow/underflow code to decide whether one code should be added or subtracted from the digital output codes.
As 1he second part of 1he present invention, the residue-based error correction technique for DASCs 1akes 1he overflow/underflow code 10 conect nonlinearity enor in 1he DASC of 1he previous subconversion stage. The error correction 1echnique, as exemplified by a preferred embodiment, is described with reference 10 Figure 2A&2B in Summary of Drawings:
Fgure 2A shows 1he effect of DASC nonlinearity of a 4bit two-s1age ADC (which isg;ven in Fgure 2B) on 1he histogram of 1he residue signal from 1he firs1 conversion stage when 1he firs1-s1age ADSC is assumed 10 be ideal. and how an overall histogram corresponding 10 the error-contaminated residue panern (see Figure 2A(c)) is generated from four individual histogram pieces conesponding to four individual resWue sections separated by 1hree 1hresholds xl,,, x, 2 and xl 3 (see Fgure 2A(b)), wherein: Held Input in Figure 2A is unknown analogue inpu110 be converted, whkh is 1he output from 1he sample-and-heW circuit ahead of 1he first-stage ADSC;
xl 1, xl 2~ xl 3 are 1hree successive 1hreshoW voRages of 1he first-s1age ADSC, and x2" x22, x23 are 1hree successive 1hreshoW vol1ages of 1he second-s1age ADSC;
Yl,l. Yl,2. y1,3 are output levels of 1he first-stage DASC; V~ is 1he reference voltage of each ADSC and DASC; Arn,olified Residue in Figure 2A is defined as: v,~""~" 2N~
in which v"",~" is 1he residue signal from 1he firs1-s1age (see Figure 2B) and Nl is lhe resolution of 1he firs1-stage ADSC; 1he 1erm Histogram, which is used in Fgure 2A.
- 2 0 9 2 ~
represents the number of occurrences of existing digital codes which output from the second-stage ADSC; as two extra quantizatbn intervals are reserved for the second-stage ADSC, i.e., [o x21) and [X23,Vr~f)~ the actual conversion range of the second-stage ADSC is denoted as Expandetl Conve~sion Range of Next Stage in hgure2A. ~;
The residue-based error correction operation for the DASC in a two-stage ADC is mathematically expressed with reference to Figure 2A as:
When x~(t)Sv~ )cx~.~+l(t), unde~low: if v"",l",(t) < X2,1 (t), YIJ ~t + T) = YIJ (t) ~ ~d ove~low:if v""~",(t)>x23(t),ylJ(t+T)=y~(t)+~ (2) where Ql is the adaptation step ske for the DASC, and could be set differently from ~" given in Equathn (1) for ADSCs. Nonlinearny error in any DASC in a pipelined multi-stage ADC can be handled in the same way.
The first part of 1he present invennion, the adaptive offset shaping technique, exhib-ns an adaptive "filtering" effect on thresholds of an ADSC (see Figure 1A in Summary of Drawings for 20 a bask architecture of lhe adaptive offset-shaped ADSC). The control mechanism of the adaptive technbue is histogram-based, because 1he histogram of digital binary codes which olnp ln from an uniformly-sampling ADSC offers information on all bit transilion levels and so allows us to monRor the linearny of the ADSC.
A typical histogram of digRal binary codes which output from an ADSC can be outlined and shown in hgure 3 in Summary of Drawi.ngs, in which each pair of adjacent thresholds in the ADSC oLnlines a quantkation interval, and the height of the interval represents occurrences of binary codes falling into this interval. Because the histogram of binary codes is a functhn of the ADSC thresholds, we expect that by adapting these successive ADSC thresholds we can 30 eventually transform a bad histogram, whkh is associated wah some error-contaminated thresholds, into one that we want. Like conventhnal adaptive filters (either analogue or digital), the adaptive offset shaping technique of the present invention needs a reference, too, either for these ADSÇ thresholds or for the histogram of binary codes which output from the ADSC.
Fgure 3 shows a histogram of input signal vh and digital ounput codes, wherein:
xO~...,x, l,x"...,x2N are thresholds in an ADSC of N-ba resolution; p(i) represents the 2 ~ 9 ~
histogram of i - th quantization interval [x, "x,), i e the occurrences that theamplitude of anabgue input vln falls into i - th interval; p(xl) in the equation in Figure 3 is the (2N +l)-th order probability density function (PDF) of a continuous random variable (RV) x at point x,.
' , A nearly-uniform histogram is used as a reference in the adaptive offset shaping technique of the presenn invention. The point of choosing a nearly-uniforrn histogram is that we want to avoid both computing the histogram of digital binary codes which output from an ADSC and the need of generating externally a reference histogram for the computed histogram because these 10 two operatbns can cost a substantial amount of anabgue/digRal circuRry. This can be realized by applying lhe adaptive technique to second-stage ADSC in a two-stage ADC or each ADSC
(except the tirst) in a pipelined multi-stage ADC, because the residue signal from the first subconversion stage in a two-stage ADC or from the previous subconversion stage of each ADSC (except the first) in a pipelined multi-stage ADC has a nearly-uniform distribution and thus the digital binary codes which output from quantizing the residue signal also have a nearly-uniform histogram if the second-stage ADSC in a two-stage ADC or the ADSC (except the first) in a pipelined muiti-stage ADC which performs the quantkation is ideal.
When the analogue residue signal resulting from the first subconversion stage in a two-20 stage ADC (or the prevbus stage of an ADSC in a pipelined multi-stage ADC) is used as inpLn to the seconci-stage ADSC in the two-stage ADC (or the ADSC in the pipelined multi-stage ADC) and when in is assumed to have a nearfy-uniform distribution, the nonuniformity in the histogram of binary codes which o npln from the second-stage ADSC in the two-stage ADC (or the ADSC in the pipelined multi-stage ADC) can be either attributed to the nonuniformny in the distribution of the residue signal or to the noneven spacings of the ADSC's threshoWs (i.e., the quantization intervals of an ADSC are not even). When the contribution from the nonuniformity in the distrib nbn of the residue signal is relatively small compared to that from the noneven spacings of the ADSC's thresholds, adapting ADSC threshoids against a nearly-uniform histogram of the digital binary codes using Equatbn (1) can force the thresholds to be nearb even-spaced and 30 thus in the meanwhile successfulb avoid both computing a code histogram and the need of generating externally a reference histogram for the computed histogram.
The operation for such a threshold adaptation was described by Equation (1) and the architecture of ns practical implementation was described above with reference to Figure 1A in Summary of Drawings.
- ., ~, ` 209~g~ :
The threshold adaptation for an ADSC using Equation (1) actually has a problem in handling two end threshoWs, i.e., ~2, and x23 in the second-stage ADSC in a 4-bit two-stage ADC. The problem can be solved by two diflerent approaches given below, each having its own inherent advantages and disadvantages. The first is to force these overflow and underflow codes obtained from quantizing a residue signal to happen with a certain probability by ratioing the adaptatbn step skes used to increment and decrement the two end ADSC thresholds, x2 1 and x2,3. For example, by using:
~f v,~ (t) ~ X2,1 (t), X2.1(t + T) = X2,1 (t)- 15~4 ~ ( ) we can keep underfbw codes happening about 4 115 of the time and so hold the threshold x2 1 at the edge of the histogram (see Figure 4 in Summary of Drawings for illustration of the ratioing technique).
Fgure 4 illustrates the ratioing of adaptation step skes which keep underflow happening about 4 115 of the time.
In fact, underfbw codes are also needed to adjust the threshold just above x2 ~, i.e., X2 2 in this 2-bit ADSC example, in order to avoid propagating systematic differenbal nonlinea~ty (DNL) 20 (which is mathematicalb defined as DNL, =x,-x, l -lLSBat i-th threshold in the ADSC, where lLSB = 2N~2 and N2 is the resolution of the second-stage ADSC), and therefore, the update rule for X2 2 needs to be modified from Equation (1 ) to:
if v,~d~,,(t)<x2,l(t)orX2,l(t)<v~ (t)<x2~2(t). X2.2(J+T)=X2.2(t)-~ (4) The case of overflow is handled in a similar way. The advantage of 1his approach is that it does not cost extra circuitry. while the problem associated with this approach is that it finalb results in a small DC offset aWitive to these two end threshokds, and this DC offset somewhat affects the accuracy of the conventional digital error correction which heavily relies upon the linearity of the 30 seroncf-stage ADSC in this two-stage ADC example.
This DC offset problem is avoided in the second approach in which we vary lhreshoWs in the firs1-stage ADSC in a two-stage ADC to exercise overflow and underfbw correction in a '' . -' . . . -- ---- --~` 2 0 9 2 ~
controlled fashion, rather than from errors alone (and the same approach can be applied to case of a pipelined multi-stage ADC; for sake of simplicity, the following discussion for the second approach is restricted to case of a two-stage ADC). This can be done by using a simple sw-nching-type control circuin embedded in the original first-stage ADSC. hgure 5 in Summary of Drawings shows a schematic diagram of such a circuin in the first-stage ADSC with a 2-bn resolunion as an example. From the figure, we can see that one extra switch is aWed to the original swnches for first and third comparator b~cks while two extra ones added to the original swnch for second comparator block (the section including the original sw-nches and the extra ones is marked as "ADSC swnched" in the figure). All ~ADSC swnches~ are successively 10 controlled by the digital outputs s, and s2 of a serial shift register (at the lower part of Figure 5).
Figure 5 shows simple control circuitry embedded in the first-stage ADSC in a 4-bit two-stage ADC to avoid the boundary effect of self-trimming, wherein: v", is unknown analogue input to the first-stage ADSC; ~l and ~2 are the synchronkathn clock signals for the first-stage ADSC and DASC, respectively; xl, X2, X3 are the voltage threshoWs of the first-stage ADSC; yl. Y2 . Y3. y4 are the digital code output from the first-stage ADSC; sl and s2 are the cbck signals from the serial shift register, which control the swinching operation; SAI, SB2, SC2 are the normal sw-nches, and SA2, SBI, ~ .
5~3, SCIare so-called "extra" switches added for the switching control purpose.
-~
The control mechanism of the embecWed circuitry is best illustrated winh reference to Figure 6 in Summary of Drawings for a 4-bin two-stage ADC. When the cbck signals sl and S2 are bolh off, the three original switched SAI, SB2 and SC2 are tumed on and so the norrnal threshold voltages are used (see Fgure 6(a)). In this case, no binary codes from the second-stage ADSC are used for as own self-trimming. When sl is on and S2 off (see Fgure 6(b)), three ~ -swaches SA2, SBI and SC2 (the first two are "extra") are tumed on while others are off. In this case, x,,l is len-shiRed by 1/2-LSB while xl 2 right-shifled by 1/2-LSB whilex,,3 remains the same.
The resulting residue in the enlarged section [x,.l,x,.2) (where, x~.~=x,,~-lLSBand X~.2 = X~"2 ~ 2 LSB; xl I and x, 2 are the normal thresholds) thus consists of the original residue 30 portion and two halves from as nebhboring sections, and as amplaude swing now spreads over the entire expanded conversion range of the second-stage ADSC. Digaal binary codes resulting from quantèing this residue can then be used for self-trimming of the second-stage ADSC.
When sl is off and s~ on (see Figure 6(c)), three swaches SAI, SB3, SCI are tumed on (the latter two are "extra") while others are all off. In this case, xl 2 is lefl-shifled by 1/2-LSB and xl 3 right-209266~ i shifted by 1/2-LSB while x, I remains the same. This gives another residue signal in the enlarged section [x, 2,X~3) (where X~.2 = Xl2 - I LSB and X~3 = X~3 + 1 LSB; Xl2 and X~3 are the normal thresholds), which spreads over the entire expanded conversion range of the second-stage ADSC. Digital binary codes from this residue signal can also be used for self-trimming of the second-stage ADSC. The overall histogram of the residue signal (as input to the second-stage ADSC) thus results from the averaging of these two histogram sections. With this control circuRry, there is no boundary problem associated wah the two end ADSC thresholds x2, and X2 3 and Ihus the self-trimming of the second-stage ADSC can be done just with the operation of Equation (1). 0 hgure 6 shows the basic mechanism of a swaching-type control approach which is intended to avoid the DC offset problem resulting from handling two end ADSC
thresholds by ratioing adaptation step skes used to increment and decrement the two end thresholds. The definitions of all symbols used in the figure are the same as those used in Figure 5.
A problem wah this switching-type control approach is that overflow and underfbw errors occurring in the enlarged sections (see Figure 6(b) and (c)) will not be detected so that the accuracy of the first-stage ADSC may be in doubt in these cases. One solunion to reduce the 20 effect of this problem on the overall accuracy of the two-stage ADC is to use a large time interval between two successive swaching operations (i.e., from the operation shown in hgure 6 (b) to that shown in hgure 6 (c)) so that the chances of overflow and underfhw codes' not being correc~ed can be made minimal.
., As thresholds in the ser ond-stage ADSC in a two-stage ADC or an ADSC (except the first) in a pipelined multi-stage ADC adapt against a nearly-uniform code histogram, the quantization interval outlined by every adjacent two of these successive ADSC thresholds expands or shrinks accordingly wah the number of occurrences of binary codes' falling into that quantization interval during the adaptatbn process, and eventually all of these quantization intervals converge to 30 some vahes, whkh are cbse to the ideal LSB, based upon the nearly-equal numbers of occurrences of binary codes' falling into the quantkation intervals. Because the effect of the interstage gain error (i.e., gain error in an interstage SHA) on a residue from the previous stage Of an ADSC whbh takes the resWue as input only causes the amplified residue to be eaher larger or smaller than the normal conversion range of the ADSC depending upon whether the interstage .
., , :
2~925~
gain is larger or smaller than the ideal one, this self-trimming operation thus automatically counteracts the gain error in an interstage SHA ahead of the ADSC.
,-The adaptive offset shaping technique alone works well for self-trimming of the second-stage ADSC in a two-stage ADC when the residue signal to the two-stage ADC swings randomly with a full amplhude, and when the first-stage ADSC and DASC in the two-stage ADC are error-free. This also applies to case of an ADSC except the first in a pipelined muHi-stage ADC. When the first-stage ADSC has some nonlinearity but the DASC is still error-free, it needs interaction wah the conventional digital error correction technique. The interaction between the adaptive 10 offset shaping technique and the digital error correction technique is discussed as follows, while the nonlinear-ity problem in an DASC is handled by the second part of the present invention.
For simplicay, we still use a 4-bit two-stage ADC as our illustrative example with reference to hgure 7 in Summary of Drawings. Figure 7 shows the residue sbnal v""~", versus the analogue input v", to the two-stage ADC when the first-stage ADSC has some nonlinearity but the DASC is still ideal. (Note that in Figure 7 we have assumed a uniformly-distributed residue panem, i.e., an ideal case, for simplicity). In this example, two of the ADSC thresholds, x,land X, 3, are left-shifled and rbht-shifted by some offsets, respectively (see Figure 7(a)). The overall conversion error arising from these threshold offsets is trivial as long as the offsets are within a 20 range of i2-LSB, because they can be readily handled by the conventional digital error correction. But these offsets can be troublesome to our self-trimming of the second-stage ADSC, as these thresholds offsets move the original histogram piece in each individual residue section (which is outlined, respectively, by two of three successive thresholds x,,, x, 2 and x, 3 of the first-stage ADSC either upward or downward along the residue axis (i.e., the vertical axis in Figure 7(b)). The boundary errors, as shown in Figure 7(b), first affect the two end thresholds x2, and x23, and then their effects propagate through the self-trimming process toward the central threshold X2 2 from both the sides.
Figure 7 shows how nonlinearity errors in the first-stage ADSC of a two-stage ADC
affect the residue panern (see Figure 7(a)) while the first-stage DASC is error-free, and how an overall histogram corresponding to the error-contaminated residue pattern is generated (see Figure 7(c)) from four individual histogram pieces separated by three thresholds xll,x~2 and X~3, wherein: x", x,2, xl3 are the voltage 209266~
thresholds of the tirs~-stage ADSC in a 4-bit two-stage ADC; x2" x22, x23 are the voltage thresholds of the second-stage ADSC.
The conventional digital error correction logic encodes the overranging of each residue section (shown in Flgure 7(b)) due to the ADSC 1hreshold offsets, i.e., the two residue pieces in [x,.l~x,~2) and [x,2.x,3) in this example, as overflow and underflow codes to correct wrong codes trom the first-stage ADSC in a two-stage ADC (and the same approach applies to case of a pipelined multi-stage ADC). The adaptive offset shaping technique of the present invention takes these overflow and underflow codes in the meanwhile to trim comparator thresholds in the first-10 stage ADSC of a two-stage ADC and all ADSCs (except the first) in a pipelined multi-stage ADC.
For sake of simplicity, we still use a 4-bit two-stage ADC below as our illustrative example to show how it works. As usual, the two end thresholds, x2, and x2,3, of the second-stage ADSC of a 4-bil two-stage ADC are used to detect the overflow and underfbw for the correction logic.
Overflow and underfbw codes from the correction bgic are then used to trim the thresholds of the first-stage ADSC. The trim operation for the first-stage ADSC can be mathematically expressed as:
when X~J(t)<V",(t)<X4,~(t), ~
overfbw: if v",~,,(t) > X2,3(r). x4,1(t+T) = X4tl (t)-~
underflow: ~fv""~",(t)<x2,(t),x4(t+T)=x4(t)+~, (5) where ~, is 1he adaptation step ske (measured in volts) for the first-stage ADSC. This equation can be interpreted as folbws: when the input v",(t) falls into (j+V-1h quantiza1ion interval [X,J,x4.,.l ) of the first-s1age ADSC at 1ime t, e.g., [x",x,.2 ) when j = 1 (see Figure 7(a)) for 1his exarnple),anunderfbwcodeoccurs(i.e., v, ,~""(t)<x2~(t))whenx~l(t) isleft-shiltedbyasmall offset. In 1his case, we can correct the offse1 1hreshoW x"(t) by trimming it up with a small voltage sfep ~,. A similar 1rip opera1hn applies to 1he overflow case. With 1he simple trimming performed in a large number of itera1ions, 1he 1hreshold offsets in the first-s1age ADSC in a two-s1age ADC can be eventually corrected, and thus the boundary effect of 1he residue's histogram 30 can be diminished.
The second part of the present inventhn, the residue-based error correction technique for DASCs, is cbsely related to the first part of the invention in terms of using the same existing overflow/underfbow information and the comparator current-trimming methorJ for error correction.
To illus1rane how the residue-based error correction 1echnique work, we will still use a 4-bit two-~ ~ . : . . .
20926~
stage ADC while referring to Figure 2A & Figure 2B in Summary of Drawing, which has beendescribed above, just for simplicity.
Figure 2A jR Summary of Drawings shows the effect of the DASC nonlinearity in a 4bn two-stage ADC, when the first-stage ADSC is ideal. From Figure 2A(a), we can see that when two output levels of the 2-bn DASC, y,.l and Yl2. are enher too large or too small, underflow or overflow occurs. The underflow or the overflow shifts the histogram piece of each related individual section in [x,.l,xl2) or [X12,X13) enher downward or upward tsee Figure 2A(b)). ~
Summing up the four histogram pieces results in an overall histogram, but this histogram has ~ `
10 some boundary effect (see Figure 2A(c)). As in case of the first-stage ADSC nonlinearity discussed above (also see Figure 7), we can also make a small correction to the distorted output levels by using: ~ ~
when xl~(t) _Vh tt)cx~+l(t), : ..
overflow: if v""d",(t)>x23(t),ylJ(t+T)=y4(t)+~
underfbw:ifv""d~,(t)<x2,(t).Y,~(t+T)=Y4(t)-~d (6) where, ~d is the adaptation step size for the DASC, and could be set differennly from ~" given above. In practice, ~d should be set relatively small compared to ~, used for the ADSCs 20 because the accuracy requirement on the DASC linearity is much hbher than that on the ADSC
nonlinearity.
The two parts of the presenn invennion~ the first for two ADSCs and the seoond for DASC in a two-stage ADC, or the first for all ADSCs and the second for all DASCs in a pipelined muHi-stage ADC provide three more degrees of freedbm for desbning a two-stage ADC, or many degrees of freedom for designing a pipelined multi-stage ADC. The combination of these two - ~ ~ ;
parts or these three degrees of freedom therefore gives a complete non-SC on-line seH-calibration scheme. Figures 8(a)&(b) in Summary of Drawings shows a bbck diagram of such a seH-calibrated N-bit two-stage ADC, and a seH-calibrated pipelined multi-stage ADC.
Figures 8(a)&(b) shows a diagram of a seH-calibrated two-stage ADC and a self-calibrated pipelined multi-stage ADC, wherein: v,~ is the unknown analogue input to ~-the ADC; V""d", is the residue signal from the first stage in a two-stage case; the first part of the present invention is outlined by the block "Trim Control", which is attached to the second-stage ADSC; the overflow and underflow information from the , . ~,....
: . :.. ', ' . :. .: -.,, ::. ,: : .- - ~ '. . . ' 2~926fi6 conventional digital error correction logic circuitry is denoted as "trim bits" in the figure.
The present invention is not limited to the features of the embodiments described and illustrated above, but includes all variations and modifications within the scope of the claims.
`',':"'
A NOVEL SELF-CALIBRATION TECHNIQUE
FOR HIGH-SPEED TWO-STAGE AND PIPELINED MULTI~STAGE ADCS
The present invention is primarily designed for correcting static or slowly-evolving random errors in high-speed two-stage and pipelined multi-step analogue-to-dbnal converters (ADCs), although it can be used for other purposes. The invention comprises two parts, anrJ these two parts are applied to critical parls of a high-speed two-stage or pipelined multi-stage ADC: AID
subconverters (ADSCs), D/A subconverters (DASCs) and interstage sample-and-held amplifiers (SHAs).
Several types of self-calibration techniques for a stand-alone ADSC are currently available in market or in literature, but they are enher operated on-line by use of switched-capacnor (SC) techniques or off-line by use of some memory-based compensation techniques. Examples of these techniques can be found in References 11]¦2] (on-line techniques) and Reference 131 (ff-line techniques).
~=;
111. H.Ohaa, H.X.Ngo, M.J.Armstrong, C.F.Rahim, and P.R.Gray, ~A CMOS programmable self-calibrabng 13-bit ebht-channel data acqulsl~on perlpherar, IEEE Joumal of Solid-Stale Circuits, Vol.SC-22, No.6, Dec.19~7.
121. Y.M.Um, B.Klm and P.R.Gray, ~A 13-b 2.~MHz self calibrated r*elined A/D xn\terter in ~fU m CMOS~. IEEE Jounal of SoUd Stab Circuits, Vol.26, No.4, April 1991.
131. A.C.Dent and C.F.N.Cowan, ~Unearizabon of analog t~di9iEIl converters~, IEEE Transaction on Circuits and Sysbms, Vol.37, No.6, pp72~737, Oc~ 1990.
These available 1echniques have many disadvantages. The SC-based on-line self-calibratbn techniques forADSCs are restricted to each individual analog comparator block of an ADSC and use a set of clock signals to control its self-calibration processes. While the SC
cbcking processes of the techniques are complicated, the SC circuitry to which these clocking processes correspond reduces the input impedance of an ADSC and also takes a considerable 30 amount of die areas. As the common characteristics that these techniques share is that the SC
error-correction operates in a signal-forward-path and the error correction for each entire comparator offset error is made within one single clock duty cycle, the sampling speed of an ADSC which uses the SC techniques is limited by these techniques to around 50 MHz and the best resolution that it can achieve is around 1 mV. These SC techniques thus do not allow us to take full advantages of the current trend of scaling-down VLSI technologies in order to have smaller transistor skes, to reduce power dissipation and to allow for higher operational speed.
7he memory-based off-line compensation techniques for ADSCs requires a precise measurement of the nonlinearity of each ADSC anr~ the subsequent storage of the ADSC
40 nonlinearity data to a memory. The nonlinearity data is then used to compensate the ADSC
- 2~926g~ ~
nonlinearity during its normal conversion process. ADC chips with these off-line techniques can not adapt to parameter drifts due to temperature change and component aging during their operation.
There are a very limaed number of self-calibration techniques which are currently available for random errors in DASCs and interstage SHAs of a two-stage or pipelined multi-stage ADC.
In most cases, therefore, the conversion accuracy of DASCs and interstage SHAs depends upon a careful layout and thus is usually limited to below 10-bit resolution. -Therefore, it is very desirable to have a self-calibration technique for ADSCs which can be operated on-line, and of which the calibration process does not constrain the operational speerl of ADSCs. Of course, it would be superior if the self-calibration technique can also be applied on-line to correct random errors in DASCs and interstage SHAs. The present invention is ~ -intended to achieve all of these goals.
The present invention mainly consists of two closely-related calibration techniques:
adaptive offset shaping technique for ADSCs and residue-based e~ror correction technique for -:
DASCs. The former technique automatically counteracts gain errors of interstage SHAs in two-stage and pipelined multi-stage ADCs during as adaptive operation.
The adaptive offset shaping technique for ADSCs mainly involves a seH-trimming process and interaction between the process and a conventional digital error correction technique for an ADSC. An ordinary standard ADSC usualb consists of an array of latched differential-pair comparators. The difference between threshold voltages of two successive comparators is called quantkation interval. The basic concept of correcting random offset errors in a single differential-pair latched comparator, which is adopted in the present invention, is to balance :
biasing current in two sides of ~he differen1ial-pair comparator and in so doing compensate for offset errors. For the error conection, an extra adjustable current source may be added to one side ot the comparator circuitry so that adjusting current in the extra current source is equivalent 30 to adjusting the threshold voltage of the comparator (several types of such current-trimming circuas are currently available in literature or in market). The self-trimming process for an ADSC
is therefore realked by connecting a simple feedback loop to each of these threshold-adjustable comparators to form a cbse~bop block, and then interconnecting these closerl-bop blocks together in a way described below.
. , . ,, -. . . . ,, . . .. ~ ... .
~ 20926~6 The simple feedback loop alone for a comparator may comprise some digital logic circuitry, an analogue adder and an analogue integrator. (Or it may comprise an UP/DOWN
digital counter and D/A converter.) The input of the digital logic circuitry is connected to the output of the comparator, and its output connected to two analogue adcfers, one for this comparator and the other for that is above this comparator in the comparator array. The output from the adWer for this comparator is connected to an analogue integrator, and the output from the integrator connected to a current-trimming circuit mentioned above.
The first part of the invention, as exemplified by a preferred embocfiment, is described with reference to Figures 1A&1 B in Summary of Drawings:
Figure lA shows the structure of an adaptive offset-shaped flash ADSC in contrast to a standard ADSC shown in Figure 1B, wherein: vh(t) is the unknown analogue input at time t to the ADSC, which is to be converled by the ADSC; x,(t) is the threshold voltage of i - th comparator in the ADSC; x,(O) is the initial threshoW
voltage of i - th comparator, which contains unwanted random offset error at time t = O; the error signal e, (t) iS the difference signal between the analogue input vln(t) and the threshold x,(t); q,(t) is the two-level output (or called thermometer code outpu~ from the i - th comparator; g,(t) is the analogue output from the integrator of the i - th comparator; B,(t) is the binary output from the dbital logic circuitry.
Refening to the drawing, the embodiment of the first part of the invention shown, an adaptive offset shaping ADSC 10 comprises an anay of two-level analogue comparators 12, an array of feedback integrators 14, an array of current-trimming circuits 16, some digital logic circuitry 18 represented in Figure 1A by an array of "exclusive-or" gates (in practice, NAND-gates are usually used), an array of analogue aWers 20. Each comparator block 22 can also be considered as a pseudo delta-modulator.
The operation of the seH-trimming process for an ADSC, which is implemented by the 30 structure described above and shown in Figure 1A, can be mathematically expressed as:
For ea~h individual quantkation interval, e.g., i - th interval where i~[LN] (N is the number of quantizatbn intervals of the ADSC), if x, l ( t ) S Vh (t ) ~ x, (t ), x,,(t+T)=x, l(t)+~"; xl(t+T)=x,(t)-~". (1) 2092~
with the two end conditions: x0 (t) = -OO and XN (t) = + for all time t . In the above equation, ~"
is a small adaptation step (measured in volts) for the self-trimming.
The second part of the present invention, the residue-based error correction technique for DASCs, is realized by making use of residue overflow/underflow information from conventional digital error correction circuitry.
The conventional digital error correclion is applied a~ an ADSC in a two-stage or pipelined multi-stage ADC to digitally correct nonlinearity error resulting from the previous subconversion stage, and its circuitry comprises a group of digital logic gates of various types. The information that 1he digital error correction process needs for its operation is overllow/underflow code, which reflects whether the overranging of a residue signal from 1he previous s1age occurs.
Overfbw/underflow code is contained in digital output codes, which result from quantking 1he residue signal. The digital error correction process takes the overflow/underflow code to decide whether one code should be added or subtracted from the digital output codes.
As 1he second part of 1he present invention, the residue-based error correction technique for DASCs 1akes 1he overflow/underflow code 10 conect nonlinearity enor in 1he DASC of 1he previous subconversion stage. The error correction 1echnique, as exemplified by a preferred embodiment, is described with reference 10 Figure 2A&2B in Summary of Drawings:
Fgure 2A shows 1he effect of DASC nonlinearity of a 4bit two-s1age ADC (which isg;ven in Fgure 2B) on 1he histogram of 1he residue signal from 1he firs1 conversion stage when 1he firs1-s1age ADSC is assumed 10 be ideal. and how an overall histogram corresponding 10 the error-contaminated residue panern (see Figure 2A(c)) is generated from four individual histogram pieces conesponding to four individual resWue sections separated by 1hree 1hresholds xl,,, x, 2 and xl 3 (see Fgure 2A(b)), wherein: Held Input in Figure 2A is unknown analogue inpu110 be converted, whkh is 1he output from 1he sample-and-heW circuit ahead of 1he first-stage ADSC;
xl 1, xl 2~ xl 3 are 1hree successive 1hreshoW voRages of 1he first-s1age ADSC, and x2" x22, x23 are 1hree successive 1hreshoW vol1ages of 1he second-s1age ADSC;
Yl,l. Yl,2. y1,3 are output levels of 1he first-stage DASC; V~ is 1he reference voltage of each ADSC and DASC; Arn,olified Residue in Figure 2A is defined as: v,~""~" 2N~
in which v"",~" is 1he residue signal from 1he firs1-s1age (see Figure 2B) and Nl is lhe resolution of 1he firs1-stage ADSC; 1he 1erm Histogram, which is used in Fgure 2A.
- 2 0 9 2 ~
represents the number of occurrences of existing digital codes which output from the second-stage ADSC; as two extra quantizatbn intervals are reserved for the second-stage ADSC, i.e., [o x21) and [X23,Vr~f)~ the actual conversion range of the second-stage ADSC is denoted as Expandetl Conve~sion Range of Next Stage in hgure2A. ~;
The residue-based error correction operation for the DASC in a two-stage ADC is mathematically expressed with reference to Figure 2A as:
When x~(t)Sv~ )cx~.~+l(t), unde~low: if v"",l",(t) < X2,1 (t), YIJ ~t + T) = YIJ (t) ~ ~d ove~low:if v""~",(t)>x23(t),ylJ(t+T)=y~(t)+~ (2) where Ql is the adaptation step ske for the DASC, and could be set differently from ~" given in Equathn (1) for ADSCs. Nonlinearny error in any DASC in a pipelined multi-stage ADC can be handled in the same way.
The first part of 1he present invennion, the adaptive offset shaping technique, exhib-ns an adaptive "filtering" effect on thresholds of an ADSC (see Figure 1A in Summary of Drawings for 20 a bask architecture of lhe adaptive offset-shaped ADSC). The control mechanism of the adaptive technbue is histogram-based, because 1he histogram of digital binary codes which olnp ln from an uniformly-sampling ADSC offers information on all bit transilion levels and so allows us to monRor the linearny of the ADSC.
A typical histogram of digRal binary codes which output from an ADSC can be outlined and shown in hgure 3 in Summary of Drawi.ngs, in which each pair of adjacent thresholds in the ADSC oLnlines a quantkation interval, and the height of the interval represents occurrences of binary codes falling into this interval. Because the histogram of binary codes is a functhn of the ADSC thresholds, we expect that by adapting these successive ADSC thresholds we can 30 eventually transform a bad histogram, whkh is associated wah some error-contaminated thresholds, into one that we want. Like conventhnal adaptive filters (either analogue or digital), the adaptive offset shaping technique of the present invention needs a reference, too, either for these ADSÇ thresholds or for the histogram of binary codes which output from the ADSC.
Fgure 3 shows a histogram of input signal vh and digital ounput codes, wherein:
xO~...,x, l,x"...,x2N are thresholds in an ADSC of N-ba resolution; p(i) represents the 2 ~ 9 ~
histogram of i - th quantization interval [x, "x,), i e the occurrences that theamplitude of anabgue input vln falls into i - th interval; p(xl) in the equation in Figure 3 is the (2N +l)-th order probability density function (PDF) of a continuous random variable (RV) x at point x,.
' , A nearly-uniform histogram is used as a reference in the adaptive offset shaping technique of the presenn invention. The point of choosing a nearly-uniforrn histogram is that we want to avoid both computing the histogram of digital binary codes which output from an ADSC and the need of generating externally a reference histogram for the computed histogram because these 10 two operatbns can cost a substantial amount of anabgue/digRal circuRry. This can be realized by applying lhe adaptive technique to second-stage ADSC in a two-stage ADC or each ADSC
(except the tirst) in a pipelined multi-stage ADC, because the residue signal from the first subconversion stage in a two-stage ADC or from the previous subconversion stage of each ADSC (except the first) in a pipelined multi-stage ADC has a nearly-uniform distribution and thus the digital binary codes which output from quantizing the residue signal also have a nearly-uniform histogram if the second-stage ADSC in a two-stage ADC or the ADSC (except the first) in a pipelined muiti-stage ADC which performs the quantkation is ideal.
When the analogue residue signal resulting from the first subconversion stage in a two-20 stage ADC (or the prevbus stage of an ADSC in a pipelined multi-stage ADC) is used as inpLn to the seconci-stage ADSC in the two-stage ADC (or the ADSC in the pipelined multi-stage ADC) and when in is assumed to have a nearfy-uniform distribution, the nonuniformity in the histogram of binary codes which o npln from the second-stage ADSC in the two-stage ADC (or the ADSC in the pipelined multi-stage ADC) can be either attributed to the nonuniformny in the distribution of the residue signal or to the noneven spacings of the ADSC's threshoWs (i.e., the quantization intervals of an ADSC are not even). When the contribution from the nonuniformity in the distrib nbn of the residue signal is relatively small compared to that from the noneven spacings of the ADSC's thresholds, adapting ADSC threshoids against a nearly-uniform histogram of the digital binary codes using Equatbn (1) can force the thresholds to be nearb even-spaced and 30 thus in the meanwhile successfulb avoid both computing a code histogram and the need of generating externally a reference histogram for the computed histogram.
The operation for such a threshold adaptation was described by Equation (1) and the architecture of ns practical implementation was described above with reference to Figure 1A in Summary of Drawings.
- ., ~, ` 209~g~ :
The threshold adaptation for an ADSC using Equation (1) actually has a problem in handling two end threshoWs, i.e., ~2, and x23 in the second-stage ADSC in a 4-bit two-stage ADC. The problem can be solved by two diflerent approaches given below, each having its own inherent advantages and disadvantages. The first is to force these overflow and underflow codes obtained from quantizing a residue signal to happen with a certain probability by ratioing the adaptatbn step skes used to increment and decrement the two end ADSC thresholds, x2 1 and x2,3. For example, by using:
~f v,~ (t) ~ X2,1 (t), X2.1(t + T) = X2,1 (t)- 15~4 ~ ( ) we can keep underfbw codes happening about 4 115 of the time and so hold the threshold x2 1 at the edge of the histogram (see Figure 4 in Summary of Drawings for illustration of the ratioing technique).
Fgure 4 illustrates the ratioing of adaptation step skes which keep underflow happening about 4 115 of the time.
In fact, underfbw codes are also needed to adjust the threshold just above x2 ~, i.e., X2 2 in this 2-bit ADSC example, in order to avoid propagating systematic differenbal nonlinea~ty (DNL) 20 (which is mathematicalb defined as DNL, =x,-x, l -lLSBat i-th threshold in the ADSC, where lLSB = 2N~2 and N2 is the resolution of the second-stage ADSC), and therefore, the update rule for X2 2 needs to be modified from Equation (1 ) to:
if v,~d~,,(t)<x2,l(t)orX2,l(t)<v~ (t)<x2~2(t). X2.2(J+T)=X2.2(t)-~ (4) The case of overflow is handled in a similar way. The advantage of 1his approach is that it does not cost extra circuitry. while the problem associated with this approach is that it finalb results in a small DC offset aWitive to these two end threshokds, and this DC offset somewhat affects the accuracy of the conventional digital error correction which heavily relies upon the linearity of the 30 seroncf-stage ADSC in this two-stage ADC example.
This DC offset problem is avoided in the second approach in which we vary lhreshoWs in the firs1-stage ADSC in a two-stage ADC to exercise overflow and underfbw correction in a '' . -' . . . -- ---- --~` 2 0 9 2 ~
controlled fashion, rather than from errors alone (and the same approach can be applied to case of a pipelined multi-stage ADC; for sake of simplicity, the following discussion for the second approach is restricted to case of a two-stage ADC). This can be done by using a simple sw-nching-type control circuin embedded in the original first-stage ADSC. hgure 5 in Summary of Drawings shows a schematic diagram of such a circuin in the first-stage ADSC with a 2-bn resolunion as an example. From the figure, we can see that one extra switch is aWed to the original swnches for first and third comparator b~cks while two extra ones added to the original swnch for second comparator block (the section including the original sw-nches and the extra ones is marked as "ADSC swnched" in the figure). All ~ADSC swnches~ are successively 10 controlled by the digital outputs s, and s2 of a serial shift register (at the lower part of Figure 5).
Figure 5 shows simple control circuitry embedded in the first-stage ADSC in a 4-bit two-stage ADC to avoid the boundary effect of self-trimming, wherein: v", is unknown analogue input to the first-stage ADSC; ~l and ~2 are the synchronkathn clock signals for the first-stage ADSC and DASC, respectively; xl, X2, X3 are the voltage threshoWs of the first-stage ADSC; yl. Y2 . Y3. y4 are the digital code output from the first-stage ADSC; sl and s2 are the cbck signals from the serial shift register, which control the swinching operation; SAI, SB2, SC2 are the normal sw-nches, and SA2, SBI, ~ .
5~3, SCIare so-called "extra" switches added for the switching control purpose.
-~
The control mechanism of the embecWed circuitry is best illustrated winh reference to Figure 6 in Summary of Drawings for a 4-bin two-stage ADC. When the cbck signals sl and S2 are bolh off, the three original switched SAI, SB2 and SC2 are tumed on and so the norrnal threshold voltages are used (see Fgure 6(a)). In this case, no binary codes from the second-stage ADSC are used for as own self-trimming. When sl is on and S2 off (see Fgure 6(b)), three ~ -swaches SA2, SBI and SC2 (the first two are "extra") are tumed on while others are off. In this case, x,,l is len-shiRed by 1/2-LSB while xl 2 right-shifled by 1/2-LSB whilex,,3 remains the same.
The resulting residue in the enlarged section [x,.l,x,.2) (where, x~.~=x,,~-lLSBand X~.2 = X~"2 ~ 2 LSB; xl I and x, 2 are the normal thresholds) thus consists of the original residue 30 portion and two halves from as nebhboring sections, and as amplaude swing now spreads over the entire expanded conversion range of the second-stage ADSC. Digaal binary codes resulting from quantèing this residue can then be used for self-trimming of the second-stage ADSC.
When sl is off and s~ on (see Figure 6(c)), three swaches SAI, SB3, SCI are tumed on (the latter two are "extra") while others are all off. In this case, xl 2 is lefl-shifled by 1/2-LSB and xl 3 right-209266~ i shifted by 1/2-LSB while x, I remains the same. This gives another residue signal in the enlarged section [x, 2,X~3) (where X~.2 = Xl2 - I LSB and X~3 = X~3 + 1 LSB; Xl2 and X~3 are the normal thresholds), which spreads over the entire expanded conversion range of the second-stage ADSC. Digital binary codes from this residue signal can also be used for self-trimming of the second-stage ADSC. The overall histogram of the residue signal (as input to the second-stage ADSC) thus results from the averaging of these two histogram sections. With this control circuRry, there is no boundary problem associated wah the two end ADSC thresholds x2, and X2 3 and Ihus the self-trimming of the second-stage ADSC can be done just with the operation of Equation (1). 0 hgure 6 shows the basic mechanism of a swaching-type control approach which is intended to avoid the DC offset problem resulting from handling two end ADSC
thresholds by ratioing adaptation step skes used to increment and decrement the two end thresholds. The definitions of all symbols used in the figure are the same as those used in Figure 5.
A problem wah this switching-type control approach is that overflow and underfbw errors occurring in the enlarged sections (see Figure 6(b) and (c)) will not be detected so that the accuracy of the first-stage ADSC may be in doubt in these cases. One solunion to reduce the 20 effect of this problem on the overall accuracy of the two-stage ADC is to use a large time interval between two successive swaching operations (i.e., from the operation shown in hgure 6 (b) to that shown in hgure 6 (c)) so that the chances of overflow and underfhw codes' not being correc~ed can be made minimal.
., As thresholds in the ser ond-stage ADSC in a two-stage ADC or an ADSC (except the first) in a pipelined multi-stage ADC adapt against a nearly-uniform code histogram, the quantization interval outlined by every adjacent two of these successive ADSC thresholds expands or shrinks accordingly wah the number of occurrences of binary codes' falling into that quantization interval during the adaptatbn process, and eventually all of these quantization intervals converge to 30 some vahes, whkh are cbse to the ideal LSB, based upon the nearly-equal numbers of occurrences of binary codes' falling into the quantkation intervals. Because the effect of the interstage gain error (i.e., gain error in an interstage SHA) on a residue from the previous stage Of an ADSC whbh takes the resWue as input only causes the amplified residue to be eaher larger or smaller than the normal conversion range of the ADSC depending upon whether the interstage .
., , :
2~925~
gain is larger or smaller than the ideal one, this self-trimming operation thus automatically counteracts the gain error in an interstage SHA ahead of the ADSC.
,-The adaptive offset shaping technique alone works well for self-trimming of the second-stage ADSC in a two-stage ADC when the residue signal to the two-stage ADC swings randomly with a full amplhude, and when the first-stage ADSC and DASC in the two-stage ADC are error-free. This also applies to case of an ADSC except the first in a pipelined muHi-stage ADC. When the first-stage ADSC has some nonlinearity but the DASC is still error-free, it needs interaction wah the conventional digital error correction technique. The interaction between the adaptive 10 offset shaping technique and the digital error correction technique is discussed as follows, while the nonlinear-ity problem in an DASC is handled by the second part of the present invention.
For simplicay, we still use a 4-bit two-stage ADC as our illustrative example with reference to hgure 7 in Summary of Drawings. Figure 7 shows the residue sbnal v""~", versus the analogue input v", to the two-stage ADC when the first-stage ADSC has some nonlinearity but the DASC is still ideal. (Note that in Figure 7 we have assumed a uniformly-distributed residue panem, i.e., an ideal case, for simplicity). In this example, two of the ADSC thresholds, x,land X, 3, are left-shifled and rbht-shifted by some offsets, respectively (see Figure 7(a)). The overall conversion error arising from these threshold offsets is trivial as long as the offsets are within a 20 range of i2-LSB, because they can be readily handled by the conventional digital error correction. But these offsets can be troublesome to our self-trimming of the second-stage ADSC, as these thresholds offsets move the original histogram piece in each individual residue section (which is outlined, respectively, by two of three successive thresholds x,,, x, 2 and x, 3 of the first-stage ADSC either upward or downward along the residue axis (i.e., the vertical axis in Figure 7(b)). The boundary errors, as shown in Figure 7(b), first affect the two end thresholds x2, and x23, and then their effects propagate through the self-trimming process toward the central threshold X2 2 from both the sides.
Figure 7 shows how nonlinearity errors in the first-stage ADSC of a two-stage ADC
affect the residue panern (see Figure 7(a)) while the first-stage DASC is error-free, and how an overall histogram corresponding to the error-contaminated residue pattern is generated (see Figure 7(c)) from four individual histogram pieces separated by three thresholds xll,x~2 and X~3, wherein: x", x,2, xl3 are the voltage 209266~
thresholds of the tirs~-stage ADSC in a 4-bit two-stage ADC; x2" x22, x23 are the voltage thresholds of the second-stage ADSC.
The conventional digital error correction logic encodes the overranging of each residue section (shown in Flgure 7(b)) due to the ADSC 1hreshold offsets, i.e., the two residue pieces in [x,.l~x,~2) and [x,2.x,3) in this example, as overflow and underflow codes to correct wrong codes trom the first-stage ADSC in a two-stage ADC (and the same approach applies to case of a pipelined multi-stage ADC). The adaptive offset shaping technique of the present invention takes these overflow and underflow codes in the meanwhile to trim comparator thresholds in the first-10 stage ADSC of a two-stage ADC and all ADSCs (except the first) in a pipelined multi-stage ADC.
For sake of simplicity, we still use a 4-bit two-stage ADC below as our illustrative example to show how it works. As usual, the two end thresholds, x2, and x2,3, of the second-stage ADSC of a 4-bil two-stage ADC are used to detect the overflow and underfbw for the correction logic.
Overflow and underfbw codes from the correction bgic are then used to trim the thresholds of the first-stage ADSC. The trim operation for the first-stage ADSC can be mathematically expressed as:
when X~J(t)<V",(t)<X4,~(t), ~
overfbw: if v",~,,(t) > X2,3(r). x4,1(t+T) = X4tl (t)-~
underflow: ~fv""~",(t)<x2,(t),x4(t+T)=x4(t)+~, (5) where ~, is 1he adaptation step ske (measured in volts) for the first-stage ADSC. This equation can be interpreted as folbws: when the input v",(t) falls into (j+V-1h quantiza1ion interval [X,J,x4.,.l ) of the first-s1age ADSC at 1ime t, e.g., [x",x,.2 ) when j = 1 (see Figure 7(a)) for 1his exarnple),anunderfbwcodeoccurs(i.e., v, ,~""(t)<x2~(t))whenx~l(t) isleft-shiltedbyasmall offset. In 1his case, we can correct the offse1 1hreshoW x"(t) by trimming it up with a small voltage sfep ~,. A similar 1rip opera1hn applies to 1he overflow case. With 1he simple trimming performed in a large number of itera1ions, 1he 1hreshold offsets in the first-s1age ADSC in a two-s1age ADC can be eventually corrected, and thus the boundary effect of 1he residue's histogram 30 can be diminished.
The second part of the present inventhn, the residue-based error correction technique for DASCs, is cbsely related to the first part of the invention in terms of using the same existing overflow/underfbow information and the comparator current-trimming methorJ for error correction.
To illus1rane how the residue-based error correction 1echnique work, we will still use a 4-bit two-~ ~ . : . . .
20926~
stage ADC while referring to Figure 2A & Figure 2B in Summary of Drawing, which has beendescribed above, just for simplicity.
Figure 2A jR Summary of Drawings shows the effect of the DASC nonlinearity in a 4bn two-stage ADC, when the first-stage ADSC is ideal. From Figure 2A(a), we can see that when two output levels of the 2-bn DASC, y,.l and Yl2. are enher too large or too small, underflow or overflow occurs. The underflow or the overflow shifts the histogram piece of each related individual section in [x,.l,xl2) or [X12,X13) enher downward or upward tsee Figure 2A(b)). ~
Summing up the four histogram pieces results in an overall histogram, but this histogram has ~ `
10 some boundary effect (see Figure 2A(c)). As in case of the first-stage ADSC nonlinearity discussed above (also see Figure 7), we can also make a small correction to the distorted output levels by using: ~ ~
when xl~(t) _Vh tt)cx~+l(t), : ..
overflow: if v""d",(t)>x23(t),ylJ(t+T)=y4(t)+~
underfbw:ifv""d~,(t)<x2,(t).Y,~(t+T)=Y4(t)-~d (6) where, ~d is the adaptation step size for the DASC, and could be set differennly from ~" given above. In practice, ~d should be set relatively small compared to ~, used for the ADSCs 20 because the accuracy requirement on the DASC linearity is much hbher than that on the ADSC
nonlinearity.
The two parts of the presenn invennion~ the first for two ADSCs and the seoond for DASC in a two-stage ADC, or the first for all ADSCs and the second for all DASCs in a pipelined muHi-stage ADC provide three more degrees of freedbm for desbning a two-stage ADC, or many degrees of freedom for designing a pipelined multi-stage ADC. The combination of these two - ~ ~ ;
parts or these three degrees of freedom therefore gives a complete non-SC on-line seH-calibration scheme. Figures 8(a)&(b) in Summary of Drawings shows a bbck diagram of such a seH-calibrated N-bit two-stage ADC, and a seH-calibrated pipelined multi-stage ADC.
Figures 8(a)&(b) shows a diagram of a seH-calibrated two-stage ADC and a self-calibrated pipelined multi-stage ADC, wherein: v,~ is the unknown analogue input to ~-the ADC; V""d", is the residue signal from the first stage in a two-stage case; the first part of the present invention is outlined by the block "Trim Control", which is attached to the second-stage ADSC; the overflow and underflow information from the , . ~,....
: . :.. ', ' . :. .: -.,, ::. ,: : .- - ~ '. . . ' 2~926fi6 conventional digital error correction logic circuitry is denoted as "trim bits" in the figure.
The present invention is not limited to the features of the embodiments described and illustrated above, but includes all variations and modifications within the scope of the claims.
`',':"'
Claims (9)
1. An array of inter-connected delta-modulation-based comparator blocks (as shown in Figure 1A in Summary of Drawings), which comprises:
an array of two-level differential-pair analogue comparators to form a standard flash A/D
converter or a flash A/D subconverter, each comparator being current-trimmable for adjustment of its voltage threshold; and an array of feedback integrators (in form of either analogue or digital); and an array of digital logic gates which can be "EXCLUSIVE-OR"- or NAND-gates and which convert thermometer code output resulting from the array of two-level analogue comparators to binary, each taking thermometer output codes from two adjacent two-level analogue comparators as its input; and an array of analogue summers, each taking binary code output from two adjacent digital logic gates mentioned above.
The array of the inter-connected comparator blocks given above is also called adaptive offset shaped flash A/D converter in Petitioner Zhiqiang Gu's Master of Applied Science thesis.
an array of two-level differential-pair analogue comparators to form a standard flash A/D
converter or a flash A/D subconverter, each comparator being current-trimmable for adjustment of its voltage threshold; and an array of feedback integrators (in form of either analogue or digital); and an array of digital logic gates which can be "EXCLUSIVE-OR"- or NAND-gates and which convert thermometer code output resulting from the array of two-level analogue comparators to binary, each taking thermometer output codes from two adjacent two-level analogue comparators as its input; and an array of analogue summers, each taking binary code output from two adjacent digital logic gates mentioned above.
The array of the inter-connected comparator blocks given above is also called adaptive offset shaped flash A/D converter in Petitioner Zhiqiang Gu's Master of Applied Science thesis.
2. An adaptive threshold updating (or called self-trimming) algorithm for an array of inter-connected delta-modulation-based comparator blocks as claimed in claim 1, which is mathematically expressed by the following equation:
if xi-1(t)?v?,(t)<x1(t), xi-1(t+T)=xi-1(t)+.DELTA..alpha.; x1(t+T)=x1(t)-.DELTA..alpha..
where, the symbol v?,(t) represents analogue input to the array of the inter-connected comparator blocks; the symbol x1(t) or xi-1(t) are voltage threshold (measured in volts) of i-th or (i-1)-th two-level analogue comparator; the symbol .DELTA..alpha. is a small adaptation step (measured in volts) for the adaptive threshold updating; the symbol T is a small time interval (measured in second).
The algorithm can be implemented by either purely-analogue circuits or mixed analogue/digital approach such as by using digital UP/DOWN counter and digital-to-analogue (D/A) converter together.
if xi-1(t)?v?,(t)<x1(t), xi-1(t+T)=xi-1(t)+.DELTA..alpha.; x1(t+T)=x1(t)-.DELTA..alpha..
where, the symbol v?,(t) represents analogue input to the array of the inter-connected comparator blocks; the symbol x1(t) or xi-1(t) are voltage threshold (measured in volts) of i-th or (i-1)-th two-level analogue comparator; the symbol .DELTA..alpha. is a small adaptation step (measured in volts) for the adaptive threshold updating; the symbol T is a small time interval (measured in second).
The algorithm can be implemented by either purely-analogue circuits or mixed analogue/digital approach such as by using digital UP/DOWN counter and digital-to-analogue (D/A) converter together.
3. A ratioing technique for handling two end thresholds (i.e., first and last thresholds) in an adapting threshold array of the inter-connected comparator blocks as claimed in claim 1 and claim 2, of which the algorithm is mathematically expressed by the following equations with reference to Figure 4 in Summary of Drawings:
for first threshold xi-1 in N-bit i-th stage A/D subconverter of a two-stage or a pipelined multi-stage AID converter where i?1, if v?(t)<xi,1(t), xi,1(t+T)=xi,1(t)-M?.alpha., where, the symbol v?(t) represents analogue input to the array of the inter-connected comparator blocks; the symbol xi,1 is first threshold in i-th stage A/D subconverter; the symbol M is an integer ratio; the symbol .DELTA..alpha. is a small adaptation step (measured in volts) for the adaptive threshold updating; the symbol T is a small time interval (measured in second).
By using the above equation, underflow codes obtained from quantizing the analogue input v?(t) can be forced to happen about of the time and so the first threshold xi,1 can be held at the edge of the histogram (refer back to Figure 4 in Summary of Drawings). Last threshold in N-bit i-th stage A/D subconverter of a two-stage or a pipelined multi-stage A/D converter (where i?1) can be handled in a similar way.
for first threshold xi-1 in N-bit i-th stage A/D subconverter of a two-stage or a pipelined multi-stage AID converter where i?1, if v?(t)<xi,1(t), xi,1(t+T)=xi,1(t)-M?.alpha., where, the symbol v?(t) represents analogue input to the array of the inter-connected comparator blocks; the symbol xi,1 is first threshold in i-th stage A/D subconverter; the symbol M is an integer ratio; the symbol .DELTA..alpha. is a small adaptation step (measured in volts) for the adaptive threshold updating; the symbol T is a small time interval (measured in second).
By using the above equation, underflow codes obtained from quantizing the analogue input v?(t) can be forced to happen about of the time and so the first threshold xi,1 can be held at the edge of the histogram (refer back to Figure 4 in Summary of Drawings). Last threshold in N-bit i-th stage A/D subconverter of a two-stage or a pipelined multi-stage A/D converter (where i?1) can be handled in a similar way.
4. A switching-type control circuit for handling two end thresholds (Le., first and last thresholds) in an adapting threshold array of the inter-connected comparator blocks as claimed in claim 1 and claim 2 but being capable of avoiding the DC offset problem which finally remains with the ratioing technique as claimed in claim 3, which comprises the following electronic elements in addition to a standard flash A/D subconverter (as shown in Figure 1(b) in Summary of Drawings) with reference to Figure 5 in Summary of Drawings:
a serial shin register or other digital logic circuitry which generates (2N -2)clock sequences for the switching-type control technique in this claim; and two extra transistor switches are added to each switch (except the first and last threshold) in a standard flash A/D subconverter (as shown in Figure 1B in Summary of Drawings) which connects a certain voltage reference to one input node of a two-level analogue comparator, each being controlled by a clock sequence from a serial shift register or other digital logic circuitry mentioned above; and one extra transistor switch is added to first and last switches in a standard flash A/D
subconverter (as shown in Figure 1B in Summary of Drawings) which connect certain voltage references to input nodes of first and last two-level analogue comparators.
a serial shin register or other digital logic circuitry which generates (2N -2)clock sequences for the switching-type control technique in this claim; and two extra transistor switches are added to each switch (except the first and last threshold) in a standard flash A/D subconverter (as shown in Figure 1B in Summary of Drawings) which connects a certain voltage reference to one input node of a two-level analogue comparator, each being controlled by a clock sequence from a serial shift register or other digital logic circuitry mentioned above; and one extra transistor switch is added to first and last switches in a standard flash A/D
subconverter (as shown in Figure 1B in Summary of Drawings) which connect certain voltage references to input nodes of first and last two-level analogue comparators.
5. A residue-based threshold trimming technique applied at second-stage A/D subconverter for correcting random threshold offsets in first-stage A/D subconverter of a two-stage A/D
converter, which takes digital overflow/underflow code regarding whether the residue from the first subconversion stage is overranged or not from conventional digital error correction circuitry as input and of which the algorithm is mathematically expressed by the following equation:
when xij(t)?vin(t)<xij+1(t), overflow: if vresidue(t)>x2,2n-1(t),xij+1(t+T)=xij+1(t)-.DELTA..alpha.
underflow: if vresidue(t)<x2,1(t),xij(t+T)=xij(t)+.DELTA..alpha.
where, the symbol vin(t) represents the analogue input to the first-stage A/D subconverter of a two-stage A/D converter; the symbol vresidue(t) represents residue signal from the first stage A/D subconverter; the symbol xij is j-th threshold in i-th stage A/D subconverter; the symbol n is the resolution of the second-stage A/D subconverter; the symbol .DELTA..alpha. is a small adaptation step (measured in volts) for the adaptive threshold updating; the symbol T is a small time interval (measured in second).
converter, which takes digital overflow/underflow code regarding whether the residue from the first subconversion stage is overranged or not from conventional digital error correction circuitry as input and of which the algorithm is mathematically expressed by the following equation:
when xij(t)?vin(t)<xij+1(t), overflow: if vresidue(t)>x2,2n-1(t),xij+1(t+T)=xij+1(t)-.DELTA..alpha.
underflow: if vresidue(t)<x2,1(t),xij(t+T)=xij(t)+.DELTA..alpha.
where, the symbol vin(t) represents the analogue input to the first-stage A/D subconverter of a two-stage A/D converter; the symbol vresidue(t) represents residue signal from the first stage A/D subconverter; the symbol xij is j-th threshold in i-th stage A/D subconverter; the symbol n is the resolution of the second-stage A/D subconverter; the symbol .DELTA..alpha. is a small adaptation step (measured in volts) for the adaptive threshold updating; the symbol T is a small time interval (measured in second).
6. A residue-based threshold trimming technique applied at each A/D subconverter (except the first) of a pipelined multi-stage A/D converter for correcting random threshold offsets in the previous-stage A/D subconverter, which lakes digital overflow/underflow code regarding whether the residue from the previous subconversion stage is overranged or not from conventional digital error correction circuitry as input and of which the algorithm is mathematically expressed by the following equation:
when xij(t)?vin(t)<ij+1(t), overflow: if vresidue,i(t)>xi+1,2n-1(t),xij+1(t+T)=xij+1(t)-.DELTA..alpha.
underflow: if vresidue,i(t)<xi+1,1(t),xij(t+T)=xij(t)+.DELTA..alpha.
where, the symbol vin(t) represents the analogue input to the previous-stage A/Dsubconverter of an A/D subconverter; the symbol Vresidue,i(t) represents residue signal from the i-th stage A/D subconverter; the symbol xij is j-th threshold in i-th stage A/D
subconverter; the symbol n is the resolution of (i+1)-th stage A/D subconverter; the symbol .DELTA..alpha. is a small adaptation step (measured in volts) for the adaptive threshold updating; the symbol T is a small time interval (measured in second).
when xij(t)?vin(t)<ij+1(t), overflow: if vresidue,i(t)>xi+1,2n-1(t),xij+1(t+T)=xij+1(t)-.DELTA..alpha.
underflow: if vresidue,i(t)<xi+1,1(t),xij(t+T)=xij(t)+.DELTA..alpha.
where, the symbol vin(t) represents the analogue input to the previous-stage A/Dsubconverter of an A/D subconverter; the symbol Vresidue,i(t) represents residue signal from the i-th stage A/D subconverter; the symbol xij is j-th threshold in i-th stage A/D
subconverter; the symbol n is the resolution of (i+1)-th stage A/D subconverter; the symbol .DELTA..alpha. is a small adaptation step (measured in volts) for the adaptive threshold updating; the symbol T is a small time interval (measured in second).
7. An adaptive error correction technique for gain error in an interstage amplifier of a two-stage or pipelined multi-stage A/D converter by adaptively expanding or shrinking the quantization interval outlined by each adjacent two of successive voltage thresholds in a flash A/D
subconverter, which follows the interstage amplifier, accordingly with the number of occurrences of codes' falling into that quantization interval.
The circuit which carries out the technique comprises the same electronic elements as the array of inter-connected comparator blocks which is claimed in claim 1.
subconverter, which follows the interstage amplifier, accordingly with the number of occurrences of codes' falling into that quantization interval.
The circuit which carries out the technique comprises the same electronic elements as the array of inter-connected comparator blocks which is claimed in claim 1.
8. A residue-based error correction technique applied at second-stage A/D subconverter for D/A
subconverter in a two-stage A/D convener, which takes digital overflow/underflow code regarding whether the residue from the first stage is overranged or not from conventional digital error correction circuitry as input and of which the algorithm is mathematically expressed as:
when xij(t)?vin(t)<xij+1(t), overflow: if vresidue(t)>X2,2n-1(t),yij(t+T)=yij(t)+.DELTA.d underflow: if vresidue(t)<x2,1(t),yij(t+T=yij(t)-.DELTA.d where, the symbol vin(t) represents the analogue input to the first-stage A/D subconverter of a two stage A/D subconverter; the symbol vresidue(t) represents residue signal from the first subconversion stage; the symbol xij(t) is j-th threshold in i-th stage A/D subconverter;
the symbol yij(t) is j-th output level of first-stage D/A subconverter; the symbol n is the resolution of second-stage A/D subconverter; the symbol .DELTA.d is a small adaptation step (measured in volts) for correction of the D/A subconverter output levels; the symbol T is a small time interval (measured in second).
subconverter in a two-stage A/D convener, which takes digital overflow/underflow code regarding whether the residue from the first stage is overranged or not from conventional digital error correction circuitry as input and of which the algorithm is mathematically expressed as:
when xij(t)?vin(t)<xij+1(t), overflow: if vresidue(t)>X2,2n-1(t),yij(t+T)=yij(t)+.DELTA.d underflow: if vresidue(t)<x2,1(t),yij(t+T=yij(t)-.DELTA.d where, the symbol vin(t) represents the analogue input to the first-stage A/D subconverter of a two stage A/D subconverter; the symbol vresidue(t) represents residue signal from the first subconversion stage; the symbol xij(t) is j-th threshold in i-th stage A/D subconverter;
the symbol yij(t) is j-th output level of first-stage D/A subconverter; the symbol n is the resolution of second-stage A/D subconverter; the symbol .DELTA.d is a small adaptation step (measured in volts) for correction of the D/A subconverter output levels; the symbol T is a small time interval (measured in second).
9. A residue-based error correction technique applied at each A/D subconverter (except the first) for D/A subconverter of the previous stage in a pipelined multi-stage A/D converter, which takes digital overflow/underflow code regarding whether the residue from the previous subconversion stage is overranged or not from conventional digital error correction circuitry as input and of which the algorithm is mathematically expressed as:
when xij(t)?vin(t)<xij+1(t), overflow: if vresidue,i(t)>xi+1,2n-1(t),yij(t+T)=yij(t)+.DELTA.d underflow: if vresidue,i(t)<xi+1,1(t),yij(t+T)=yij(t)-.DELTA.d where, the symbol vin(t) represents the analogue input to the i-th stage A/D subconverter of a pipelined multi-stage A/D subconverter; the symbol vresidue,i(t) represents residue signal from the i-th subconversion stage; the symbol xij(t) is j-th threshold in i-th stage A/D
subconverter; the symbol yij(t) is j-th output level of i-th stage D/A subconverter; the symbol n is the resolution of (i+1)-th stage A/D subconverter; the symbol .DELTA.d is a small adaptation step (measured in volts) for correction of the D/A subconverter output levels; the symbol T is a small time interval (measured in second).
when xij(t)?vin(t)<xij+1(t), overflow: if vresidue,i(t)>xi+1,2n-1(t),yij(t+T)=yij(t)+.DELTA.d underflow: if vresidue,i(t)<xi+1,1(t),yij(t+T)=yij(t)-.DELTA.d where, the symbol vin(t) represents the analogue input to the i-th stage A/D subconverter of a pipelined multi-stage A/D subconverter; the symbol vresidue,i(t) represents residue signal from the i-th subconversion stage; the symbol xij(t) is j-th threshold in i-th stage A/D
subconverter; the symbol yij(t) is j-th output level of i-th stage D/A subconverter; the symbol n is the resolution of (i+1)-th stage A/D subconverter; the symbol .DELTA.d is a small adaptation step (measured in volts) for correction of the D/A subconverter output levels; the symbol T is a small time interval (measured in second).
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| CA 2092666 CA2092666A1 (en) | 1993-04-27 | 1993-04-27 | Self-calibration technique for high-speed two-stage and pipelined multi-stage analog-to-digital converters |
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| Application Number | Priority Date | Filing Date | Title |
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| CA 2092666 CA2092666A1 (en) | 1993-04-27 | 1993-04-27 | Self-calibration technique for high-speed two-stage and pipelined multi-stage analog-to-digital converters |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002069501A1 (en) * | 2001-02-27 | 2002-09-06 | Telefonaktiebolaget Lm Ericsson | A/d converter calibration test sequence insertion |
| WO2003081782A1 (en) * | 2002-03-25 | 2003-10-02 | Infineon Technologies Ag | A/d converter calibration |
| WO2010130866A1 (en) * | 2009-05-14 | 2010-11-18 | Consejo Superior De Investigaciones Científicas (Csic) | ADAPTIVE METHOD FOR CONCURRENT DIGITAL CALIBRATION OF THE OFFSET IN COMPARATORS IN ANALOG-TO-DIGITAL CONVERTERS (ADCs) |
| CN114039601A (en) * | 2021-11-03 | 2022-02-11 | 京东方科技集团股份有限公司 | Signal sampling circuit and target positioning method |
-
1993
- 1993-04-27 CA CA 2092666 patent/CA2092666A1/en not_active Abandoned
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002069501A1 (en) * | 2001-02-27 | 2002-09-06 | Telefonaktiebolaget Lm Ericsson | A/d converter calibration test sequence insertion |
| US7405681B2 (en) | 2001-02-27 | 2008-07-29 | Telefonaktiebolaget Lm Ericsson (Publ) | A/D converter calibration test sequence insertion |
| WO2003081782A1 (en) * | 2002-03-25 | 2003-10-02 | Infineon Technologies Ag | A/d converter calibration |
| US6972701B2 (en) | 2002-03-25 | 2005-12-06 | Infineon Technologies Ag | A/D converter calibration |
| WO2010130866A1 (en) * | 2009-05-14 | 2010-11-18 | Consejo Superior De Investigaciones Científicas (Csic) | ADAPTIVE METHOD FOR CONCURRENT DIGITAL CALIBRATION OF THE OFFSET IN COMPARATORS IN ANALOG-TO-DIGITAL CONVERTERS (ADCs) |
| ES2373282A1 (en) * | 2009-05-14 | 2012-02-02 | Consejo Superior De Investigaciones Científicas (Csic) | ADAPTIVE METHOD FOR CONCURRENT DIGITAL CALIBRATION OF THE OFFSET IN COMPARATORS IN ANALOG-TO-DIGITAL CONVERTERS (ADCs) |
| CN114039601A (en) * | 2021-11-03 | 2022-02-11 | 京东方科技集团股份有限公司 | Signal sampling circuit and target positioning method |
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