CN114039583B - Switching circuit and electronic device - Google Patents
Switching circuit and electronic device Download PDFInfo
- Publication number
- CN114039583B CN114039583B CN202111235596.XA CN202111235596A CN114039583B CN 114039583 B CN114039583 B CN 114039583B CN 202111235596 A CN202111235596 A CN 202111235596A CN 114039583 B CN114039583 B CN 114039583B
- Authority
- CN
- China
- Prior art keywords
- node
- pin
- analog switch
- coupled
- common
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
Abstract
The application provides a switch circuit and electronic equipment, relates to electronic equipment technical field, can reduce electronic equipment's cost. The switching circuit includes: at least one analog switch, an input node, a power supply node, a ground node, an enable node, a common node; the analog switch comprises an input pin, a power supply pin, a grounding pin, an enabling pin and a public pin; the input pin is coupled with the input node, the power supply pin is coupled with the power supply node, the grounding pin is coupled with the grounding node, the enabling pin is coupled with the enabling node, and the common pin is coupled with the common node; the switching circuit further includes: at least one impedance device; wherein the impedance device is coupled between at least one of the power pin and a power node, the ground pin and a ground node, and the enable pin and an enable node.
Description
Technical Field
The application relates to the technical field of electronic equipment, in particular to a switching circuit and electronic equipment.
Background
The analog switch is a switch for controlling a signal path by using the characteristics of an analog device (MOS tube), and is mainly used for completing the switching function of connecting or disconnecting a signal link. The high-power-consumption electronic device has the characteristics of low power consumption, high speed, no mechanical contact, small volume, long service life and the like, so that the high-power-consumption electronic device is widely applied to electronic devices such as mobile phones, tablets, computers and the like.
The analog switch is generally divided into a low-speed analog switch and a high-speed analog switch according to the application scene of the analog switch. For example, in a mobile phone, when a USB signal needs to be transmitted through an analog switch, the analog switch is a high-speed analog switch; when the audio analog signal needs to be transmitted through the analog switch, the analog switch can be a low-speed analog switch.
High speed analog switches require higher switching speeds, and therefore are more demanding and costly to design. When the high-speed analog switch is applied to electronic equipment such as a mobile phone, a tablet, a computer and the like, the cost of the electronic equipment is increased.
Disclosure of Invention
In order to solve the above technical problem, the present application provides a switching circuit and an electronic device. The cost of the electronic device can be reduced.
In a first aspect, an embodiment of the present application provides a switching circuit, including: at least one analog switch, an input node, a power supply node, a ground node, an enable node, a common node; the analog switch comprises an input pin, a power supply pin, a grounding pin, an enabling pin and a public pin; the input pin is coupled with the input node, the power supply pin is coupled with the power supply node, the grounding pin is coupled with the grounding node, the enabling pin is coupled with the enabling node, and the public pin is coupled with the public node; the switching circuit further includes: at least one impedance device; wherein the impedance device is coupled between at least one of the power pin and a power node, the ground pin and a ground node, and the enable pin and an enable node.
The impedance device is added on the pin of the analog switch, so that the impedance of the path is increased, the signal leakage is reduced, even if the used analog switch is a low-speed analog switch, a high-speed signal can be transmitted through the low-speed analog switch, and the use scene of the low-speed analog switch is widened. In addition, since the low-speed analog switch is low in cost, when the switching circuit is applied to an electronic device, the cost of the electronic device can be reduced.
Illustratively, the number of the analog switches is one, the number of the input pins in the analog switches is two, the number of the power supply pin, the ground pin, the enable pin and the common pin is one, and the two input pins include a first input pin and a second input pin. Or, the number of the input pins is four, that is, the input pins include a first input pin, a second input pin, a third input pin and a fourth input pin, and the number of the common pins is two, that is, the common pins include a first common pin and a second common pin, and the number of the enable pins is two, that is, the number of the enable pins includes a first enable pin, a second enable pin, a power supply pin and a ground pin is one.
In some possible implementations, the input nodes include a first input node and a second input node; the common nodes comprise a first common node and a second common node; the enabling node comprises a first enabling node and a second enabling node; the first input node, the second input node, the first common node, the second common node, the first enabling node and the second enabling node are respectively coupled with different pins of the analog switch; a first input node for receiving a positive differential signal; the first enabling node is used for receiving a first enabling voltage and transmitting the first enabling voltage to an enabling pin coupled with the first enabling node so as to enable a common pin coupled with the first common node and an input pin coupled with the first input node to be conducted; a common pin coupled to the first common node for transmitting the positive differential signal to the first common node; the second input node is used for receiving a negative differential signal; the second enabling node is used for receiving a second enabling voltage and transmitting the second enabling voltage to an enabling pin coupled with the second enabling node so as to enable a common pin coupled with the second common node and an input pin coupled with the second input node to be conducted; the common pin coupled to the second common node is used to transmit the negative differential signal to the second common node so that the switching circuit can be applied in transmitting differential signals.
For example, the first input node, the second input node, the first common node, the second common node, the first enable node, and the second enable node may be coupled to different pins of an analog switch, respectively. The analog switches corresponding to the pins coupled to the first input node, the first common node and the first enable node may be different from the analog switches corresponding to the pins coupled to the second input node, the second common node and the second enable node.
In some possible implementations, the switching circuit includes: at least two analog switches, including a first analog switch and a second analog switch; the first input node is coupled with an input pin in the first analog switch, and the first common node is coupled with a common pin in the first analog switch; the second input node is coupled to an input pin of a second analog switch, and the second common node is coupled to a common pin in the second analog switch. In this way, the positive and negative differential signals are transmitted in the two analog switches, respectively, further reducing the mutual coupling within the analog switches.
In some possible implementations, the number of impedance devices corresponding to the first analog switch is the same as the number of impedance devices corresponding to the second analog switch. The impedance device corresponding to each analog switch has the same influence on the positive differential signal and the negative differential signal, and the reliability of the signals is improved.
In some possible implementations, the position of the impedance device corresponding to the first analog switch is the same as the position of the impedance device corresponding to the second analog switch. Further, the impedance devices corresponding to the analog switches have the same influence on the positive differential signals and the negative differential signals, and the reliability of the signals is improved.
Illustratively, the impedance device corresponding to the first analog switch is coupled to the same pins and nodes as the impedance device corresponding to the second analog switch.
In some possible implementations, the switching speed of the analog switch is less than or equal to 100 mhz, i.e., a high-speed signal can be transmitted through the low-speed analog switch, which reduces the cost of the electronic device when the switching circuit is applied to the electronic device.
In some possible implementations, the impedance value of the impedance device is greater than 600 ohms, further increasing the impedance of the path, further preventing signal leakage.
In some possible implementations, the impedance device includes an inductor, a magnetic bead, or a combination of an inductor and a capacitor, among others.
In some possible implementations, the method includes: at least three impedance devices; the three impedance devices are coupled between the ground node and the ground pin, between the enable node and the enable pin, and between the power node and the power pin, respectively. Therefore, the signal transmission is not influenced, and the signal leakage can be better reduced.
In a second aspect, an embodiment of the present application provides an electronic device, which includes the switching circuit of any one of the above. All the effects of the above-described switching circuit can be achieved.
Drawings
Fig. 1 is an application scenario diagram of an electronic device according to an embodiment of the present application;
fig. 2 is a schematic view of an application scenario of an electronic device according to an embodiment of the present application;
fig. 3 is one of application scenarios of an electronic device according to an embodiment of the present application;
fig. 4 is one of application scenarios of an electronic device according to an embodiment of the present application;
fig. 5 is one of application scenarios of an electronic device according to an embodiment of the present application;
fig. 6 is one of application scenarios of an electronic device according to an embodiment of the present application;
fig. 7 is one of application scenarios of an electronic device according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a switching circuit according to an embodiment of the present disclosure;
fig. 9 is an equivalent circuit diagram of an analog switch according to an embodiment of the present application;
fig. 10 is a schematic structural diagram of a part of an electronic device according to an embodiment of the present application;
fig. 11 is a schematic partial structural diagram of an electronic device according to an embodiment of the present application;
fig. 12 is a schematic partial structural diagram of an electronic device according to an embodiment of the present application;
fig. 13 is a schematic partial structural diagram of an electronic device according to an embodiment of the present application;
fig. 14 is a schematic structural diagram of another switching circuit provided in the embodiment of the present application;
fig. 15 is a schematic structural diagram of another switching circuit provided in the embodiment of the present application;
fig. 16 is a schematic structural diagram of another switching circuit provided in the embodiment of the present application;
fig. 17 is a schematic structural diagram of another switching circuit provided in the embodiment of the present application;
fig. 18 is a schematic structural diagram of another switching circuit provided in the embodiment of the present application;
fig. 19 is a schematic structural diagram of another switching circuit provided in the embodiment of the present application;
fig. 20 is a schematic structural diagram of another switching circuit provided in the embodiment of the present application;
fig. 21 is a schematic structural diagram of another switching circuit provided in the embodiment of the present application;
fig. 22 is a schematic structural diagram of another switching circuit provided in the embodiment of the present application;
fig. 23 is a schematic structural diagram of another switching circuit provided in the embodiment of the present application;
fig. 24 is a schematic structural diagram of another switching circuit according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone.
The terms "first" and "second," and the like in the description and in the claims of the embodiments of the present application, are used for distinguishing between different objects and not for describing a particular order of the objects. For example, the first target object and the second target object, etc. are specific sequences for distinguishing different target objects, rather than describing target objects.
In the embodiments of the present application, words such as "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.
In the description of the embodiments of the present application, the meaning of "a plurality" means two or more unless otherwise specified. For example, a plurality of processing units refers to two or more processing units; the plurality of systems refers to two or more systems.
The embodiment of the application provides electronic equipment, which can be electronic equipment with an analog switch, such as a mobile phone, a computer, a tablet computer, a personal digital assistant (PDA for short), a vehicle-mounted computer, a television, intelligent wearable equipment, intelligent household equipment and the like.
The following describes specific structures and applications of the electronic device provided in the embodiments of the present application.
As shown in fig. 1, fig. 1 shows an application scenario schematic diagram of an electronic device provided in an embodiment of the present application, where the electronic device 100 includes a control module 10, an audio module 20, an analog switch 30, an external interface 40, and the like. The external interface 40 is provided so that the electronic device 100 can be coupled with an external device. The external interface 40 is, for example, a USB interface. The external device may include, for example, a charger, a headset, a mobile phone, a computer, and other electronic devices.
Illustratively, the analog switch 30 may comprise, for example, a Single Pole Double Throw (SPDT) switch, and fig. 2 shows a functional block diagram of the analog switch, and in conjunction with fig. 2, the analog switch 30 includes a first input pin 1, a ground pin 2, a second input pin 3, an enable pin 4, a power pin 5, and a common pin 6. The first input pin 1 is coupled with the control module 10, the second input pin 3 is coupled with the audio module 20, the ground pin 2 is grounded, the power pin 5 is used for receiving a power signal, the enable pin 4 is used for receiving an enable voltage, and the common pin 6 is controlled to be conducted with the first input pin 1 or the common pin 6 is controlled to be conducted with the second input pin 3 according to the enable voltage.
It should be noted that fig. 2 illustrates the analog switch 30 as an SPDT switch, but the present application is not limited thereto, and a person skilled in the art can select the type of the analog switch 30 according to actual circumstances, and the embodiment of the present application is not particularly limited. Hereinafter, the analog switch 30 is exemplified as the SPDT switch hereinafter unless otherwise stated.
In this case, for example, referring to fig. 3, when the external device accessed by the external interface 40 is a computer 200, the control module 10 may be used to output a high-speed USB signal, for example. The enable pin 4 controls the common pin 6 to be conducted with the first input pin 1 according to the received enable voltage, and the high-speed USB signal is transmitted to the computer 200 through the analog switch 30 and the external interface 40, so that the transmission of the USB signal is realized. The control module 10 may include, for example, a Micro Controller Unit (MCU). The control module 10 may be a stand-alone device or integrated on a system on chip (SoC), and the embodiment of the present invention is not limited thereto. Referring to fig. 4, when the external device connected to the external interface 40 is an earphone 300, the audio module 20 is used to output an audio analog signal, for example. The enable pin 4 controls the common pin 6 to be conducted with the second input pin 3 according to the received enable voltage, and the audio analog signal output by the audio module 20 is transmitted to the headset 300 through the analog switch 30 and the external interface 40, so that the headset 300 can hear the sound emitted by the electronic device 100. The audio module 20 may be, for example, a chip for performing audio processing, and on this basis, the embodiment of the present application does not limit the type of the chip.
As shown in fig. 5, fig. 5 is a schematic view illustrating still another application scenario of the electronic device according to the embodiment of the present application, where the electronic device 100 includes a control module 10, an analog switch 30, an external interface 40, and the like. The external interface 40 is provided so that the electronic device 100 can be coupled with an external device. The external interface 40 is, for example, a USB interface. The external device may include, for example, an electronic device such as a charger, a headset, a mobile phone, a computer, and a testing device.
The analog switch 30 is also illustrated as including a Single Pole Double Throw (SPDT) switch. Referring to fig. 6, when the external device accessed by the external interface 40 is a computer 200, the control module 10 may be used to output a high-speed USB signal, for example. The enable pin 4 controls the common pin 6 to be conducted with the first input pin 1 according to the received enable voltage, and the high-speed USB signal is transmitted to the computer 200 through the analog switch 30 and the external interface 40, thereby realizing the transmission of the USB signal. Referring to fig. 7, when the electronic device 100 needs to be debugged, the external device connected to the external interface 40 is a test device 400, and the control module 10 outputs a low-speed debug signal. The enable pin 4 controls the common pin 6 to be conducted with the second input pin 3 according to the received enable voltage, and the low-speed debugging signal is transmitted to the test equipment 400 through the analog switch 30 and the external interface 40 to debug the electronic equipment 100.
It should be noted that, the above example only uses the analog switch 30 to couple with the control module 10 and the audio module 20, respectively, and transmits the high-speed USB signal output by the control module 10 and the audio analog signal output by the audio module 20 through the analog switch 30; and, the analog switch 30 is coupled with the control module 10, and the high speed USB signal and the low speed debug signal are transmitted through the analog switch 30 as an example for explanation. Of course, the analog switch 30 can be applied to other scenarios to realize the transmission of other signals. Furthermore, the analog switch 30 may transmit only one signal; different signals can also be transmitted, which is not limited in the embodiments of the present application. Hereinafter, unless otherwise stated, the transmission of the high-speed USB signal and the audio analog signal through the analog switch 30 is taken as an example.
Since the USB signal is a high-speed signal, the analog switch 30 needs to be a high-speed analog switch, so that link switching can be quickly achieved to complete transmission of the high-speed signal. However, the high-speed analog switch is expensive due to the high requirements of the design, which results in a high cost of the electronic device 100.
In order to solve the above technical problem, an embodiment of the present application provides a switching circuit, which includes at least one analog switch and further includes an impedance device on a pin of the analog switch. The impedance device is added on the pin of the analog switch, so that the impedance of the access is increased, the signal leakage is reduced, even if the used analog switch is a low-speed analog switch, a high-speed signal can be transmitted through the low-speed analog switch, and the use scene of the low-speed analog switch is widened. In addition, since the low-speed analog switch is low in cost, when the switching circuit is applied to an electronic device, the cost of the electronic device can be reduced.
The switching circuit is specifically described below with reference to electronic devices.
As shown IN fig. 8, the switch circuit 50 includes an analog switch 30, an enable node IN, a power supply node VCC, a common node COM, a ground node GND, and an input node N. The input nodes N may include, for example, a first input node NO and a second input node NC. The switching speed of the analog switch 30 may be low, for example, the switching speed of the analog switch 30 may be less than or equal to 100 megahertz, for example. A first input node NO is coupled to the first input pin 1, a second input node NC is coupled to the second input pin 3, a ground node GND is coupled to the ground pin 2, an enable node IN is coupled to the enable pin 4, a power supply node VCC is coupled to the power supply pin 5, and a common node COM is coupled to the common pin 6.
With continued reference to fig. 8, the switching circuit 50 further includes impedance devices 60, the number of impedance devices 60 being, for example, 3. One of the impedance devices 60 is coupled between the ground node GND and the ground pin 2, one of the impedance devices 60 is coupled between the enable node IN and the enable pin 4, and one of the impedance devices 60 is coupled between the power supply node VCC and the power supply pin 5.
Specifically, the switching function of the analog switch 30 is realized by a MOS transistor, for example. FIG. 9 is an equivalent circuit diagram of the analog switch 30, and referring to FIG. 9, the gate and the source of the MOS transistor form a parasitic capacitance C gs The grid electrode and the drain electrode of the MOS tube form a parasitic capacitance C gd The source and drain of the MOS transistor form a parasitic capacitor C sd The first input node NO and the ground node GND form a parasitic capacitor C no The second input node NC and the ground node GND form a parasitic capacitance C nc The common node COM and the ground node GND form a parasitic capacitor C com . That is, the analog switch 30 internally includes a plurality of parasitic capacitances. The magnitude of the parasitic capacitance affects the edge timing of the signal. The main limitation of the low-speed analog switch is that the internal parasitic capacitance value is large, and the large parasitic capacitance seriously attenuates the high-speed signal and affects the transmission of the high-speed signal. IN the embodiment of the application, the connection between the ground node GND and the ground pin 2 and between the enable node IN and the enable pin 4And an impedance device 60 is provided between the power supply node VCC and the power supply pin 5. The impedance device 60 increases the impedance of the high-frequency path, and thus, leakage of a high-speed signal through the path between the ground node GND and the ground pin 2, the path between the enable node IN and the enable pin 4, and the path between the power supply node VCC and the power supply pin 5 can be reduced, and thus, even if the analog switch 30 used is a low-speed analog switch, a high-speed signal can be transmitted through the low-speed analog switch.
On this basis, for example, referring to fig. 10 and 11, when the external device connected to the external interface 40 is a computer 200, the transmission of the high-speed USB signal can be completed through the switch circuit 50 including the low-speed analog switch 30. Referring to fig. 12, when the external device connected to the external interface 40 is an earphone 300, the transmission of the audio analog signal may also be performed by the switching circuit 50 including the low-speed analog switch 30. And, referring to fig. 13, when the external device connected to the external interface 40 is the test device 400, the transmission of the low-speed debug signal may also be completed through the switch circuit 50 including the low-speed analog switch 30.
In the present application, when the switch circuit 50 is disposed in the electronic device 100, since the analog switch 30 of the switch circuit 50 can be a low-speed analog switch, that is, the switch circuit 50 including the low-speed analog switch completes transmission of a high-speed signal between the electronic device 100 and an external device, the cost of the electronic device 100 can be reduced.
It should be noted that, the analog switch 30 is not limited to be a low-speed analog switch, the analog switch 30 may also be a high-speed analog switch, and when the analog switch 30 in the switch circuit 50 is a high-speed analog switch, the switch circuit 50 may also be applied to a higher-frequency scene to support transmission of a higher-speed signal.
It should be noted that, not only the transmission of the high-speed signal between the electronic device 100 and the external device can be completed through the switch circuit 50 including the low-speed analog switch, but also the transmission of the high-speed signal in the electronic device 100 can be completed through the switch circuit 50 including the low-speed analog switch, and the application scenario of the switch circuit 50 is not limited in the embodiment of the present application.
Further, as for the arrangement position of the impedance device 60, the above example shows only one arrangement position of the impedance device 60, that is, as shown IN fig. 8, the impedance device 60 is arranged between the ground node GND and the ground pin 2, the impedance device 60 is arranged between the enable node IN and the enable pin 4, and the impedance device 60 is arranged between the power supply node VCC and the power supply pin 5. However, the present application is not limited thereto, and it is sufficient if signal leakage can be reduced when a high-speed signal is transmitted through the analog switch 30.
In some possible implementations, the impedance device 60 is coupled between only one of the pins and the node corresponding to that pin.
In one example, referring to fig. 14, impedance device 60 is coupled between ground node GND and ground pin 2. The impedance device 60 between the ground node GND and the ground pin 2 increases the impedance of the high-frequency path, thereby preventing the high-speed signal from leaking through the path between the ground node GND and the ground pin 2.
In yet another example, referring to fig. 15, an impedance device 60 is coupled between the supply node VCC and the supply pin 5. The impedance of the high-frequency path is increased by the impedance device 60 between the power supply node VCC and the power supply pin 5, and the high-speed signal is prevented from leaking through the path between the power supply node VCC and the power supply pin 5.
IN yet another example, referring to fig. 16, an impedance device 60 is coupled between the enable node IN and the enable pin 4. The high frequency path impedance is increased by the impedance device 60 between the enable node IN and the enable pin 4, avoiding leakage of high speed signals through the path of the enable node IN and the enable pin 4.
In yet other possible implementations, the impedance device 60 is coupled between one of the pins and a node corresponding to the pin; and between the other pin and the node corresponding to the pin.
IN one example, referring to fig. 17, the impedance device 60 is coupled between the ground node GND and the ground pin 2, and the impedance device 60 is coupled between the enable node IN and the enable pin 4. The impedance device 60 between the ground node GND and the ground pin 2 increases the impedance of the high-frequency path, thereby preventing the high-speed signal from leaking through the path between the ground node GND and the ground pin 2. The high frequency path impedance is increased by the impedance device 60 between the enable node IN and the enable pin 4, avoiding leakage of high speed signals through the path of the enable node IN and the enable pin 4.
In yet another example, referring to fig. 18, impedance device 60 is coupled between ground node GND and ground pin 2, and impedance device 60 is coupled between power supply node VCC and power supply pin 5. The impedance device 60 between the ground node GND and the ground pin 2 increases the impedance of the high-frequency path, and prevents the high-speed signal from leaking through the path between the ground node GND and the ground pin 2. The impedance device 60 between the power supply node VCC and the power supply pin 5 increases the impedance of the high-frequency path, and prevents the high-speed signal from leaking through the path between the power supply node VCC and the power supply pin 5.
IN yet another example, referring to fig. 19, the impedance device 60 is coupled between the enable node IN and the enable pin 4, and the impedance device 60 is coupled between the power supply node VCC and the power supply pin 5. The high frequency path impedance is increased by the impedance device 60 between the enable node IN and the enable pin 4, avoiding leakage of high speed signals through the path of the enable node IN and the enable pin 4. The impedance of the high-frequency path is increased by the impedance device 60 between the power supply node VCC and the power supply pin 5, and the high-speed signal is prevented from leaking through the path between the power supply node VCC and the power supply pin 5.
IN the following examples, an impedance device 60 is provided between the ground node GND and the ground pin, an impedance device 60 is provided between the enable node IN and the enable pin, and an impedance device 60 is provided between the power supply node VCC and the power supply pin.
In addition, as for the type of the impedance device 60, the present embodiment does not limit the type of the impedance device 60.
In some possible implementations, referring to fig. 20, the impedance device 60 is, for example, an inductor. But is not limited to this application as long as the device that can increase the impedance on the path is within the scope of the present application. The impedance device 60 may also be a combination of an inductor and a capacitor, or a magnetic bead, for example.
In addition, as for the resistance value of the resistance device 60, the resistance value of the resistance device 60 is not limited in the embodiment of the present application. In some possible implementations, the impedance value of the impedance device 60 may be greater than 600 ohms, for example. When the impedance value of the impedance device 60 is greater than 600 ohms, it is better to prevent the high-speed signal from leaking through the path between the ground node GND and the ground pin 2, the path between the enable node IN and the enable pin 4, and the path between the power supply node VCC and the power supply pin 5.
It should be noted that, in the above example, only one switch is included in the analog switch 30, and the transmitted signal is a single-ended signal. Optionally, the analog switch 30 may further include a multi-way switch therein, and the signal transmitted through the analog switch 30 is a differential signal. For example, the analog switch 30 includes M-way switches therein, where M is a positive integer greater than or equal to 2. The analog switch 30 may include, for example, 2M input pins, M enable pins, and M common pins.
In some possible implementations, referring to fig. 21, the analog switch 30 illustratively includes a two-way switch therein. The analog switch 30 includes a first input pin 1, a second input pin 2, a ground pin 3, a third input pin 4, a fourth input pin 5, a first enable pin 6, a first common pin 7, a power supply pin 8, a second enable pin 9, and a second common pin 10. The switching circuit 50 includes the analog switch 30. The switch circuit 50 further includes an enable node IN, a power supply node VCC, a common node COM, a ground node GND, and an input node N. The input node N includes a first input node NO1, a second input node NO2, a third input node NC1, and a fourth input node NC2. The enable node IN includes a first enable node IN1 and a second enable node IN2. The common node COM includes a first common node COM1 and a second common node COM2. The first input pin 1 is coupled to a first input node NO1, the second input pin 2 is coupled to a third input node NC1, the ground pin 3 is coupled to a ground node GND, the third input pin 4 is coupled to a fourth input node NC2, the fourth input pin 5 is coupled to a second input node NO2, the first enable pin 6 is coupled to a first enable node IN1, the first common pin 7 is coupled to a first common node COM1, the power supply pin 8 is coupled to a power supply node VCC, the second enable pin 9 is coupled to a second enable node IN2, and the second common pin 10 is coupled to a second common node COM2.
Illustratively, the external interface 40 is, for example, USB 2.0. The USB signals include a positive differential signal USB _ DP and a negative differential signal USB _ DP. The low speed analog signals include a left channel signal L and a right channel signal R.
Illustratively, when the transmitted signals are a positive differential signal USB _ DP and a negative differential signal USB _ DP, the first input node NO1 transmits the received positive differential signal USB _ DP to the first input pin 1, the first enable node IN1 transmits the received first enable voltage to the first enable pin 6 to control the first common pin 7 to be conducted with the first input pin 1, and the positive differential signal USB _ DP is transmitted to the first common node COM1 through the analog switch 30 to be transmitted to an external device (e.g., a computer) through the first common node COM 1. Meanwhile, the second input node NO2 transmits the received negative differential signal USB _ DP to the fourth input pin 5, the second enable node IN2 transmits the received second enable voltage to the second enable pin 9 to control the second common pin 10 to be conducted with the fourth input pin 5, and the negative differential signal USB _ DP is transmitted to the second common node COM2 through the analog switch 30 to be transmitted to the external device through the second common node COM2. Thereby realizing the transmission of the USB signal.
When the transmitted signals are a left channel signal L and a right channel signal R, the third input node NC1 transmits the received left channel signal L to the second input pin 2, the first enable voltage received by the first enable node IN1 is transmitted to the first enable pin 6 to control the first common pin 7 to be conducted with the second input pin 2, and the left channel signal L is transmitted to the first common node COM1 through the analog switch 30 to be transmitted to an external device (e.g., a headset) through the first common node COM 1. Meanwhile, the fourth input node NC2 transmits the received right channel signal R to the third input pin 4, the second enable voltage received by the second enable node IN2 is transmitted to the second enable pin 9 to control the second common pin 10 to be conducted with the third input pin 4, and the right channel signal R is transmitted to the second common node COM2 through the analog switch 30 to be transmitted to the external device through the second common node COM2. Thereby realizing the transmission of the audio frequency analog signal.
In this way, when the switch circuit 50 is disposed in the electronic device 100, since the analog switch 30 of the switch circuit 50 can be a low-speed analog switch, that is, the switch circuit 50 including the low-speed analog switch completes transmission of a high-speed differential signal in the electronic device 100, or completes transmission of a high-speed differential signal between the electronic device 100 and an external device, the cost of the electronic device 100 can be reduced.
In addition, when the signals transmitted by the analog switch 30 are differential signals, in order to reduce mutual coupling inside the analog switch 30, the high-speed differential signals may also be transmitted on two independent low-speed analog switches, respectively, and optionally, the two low-speed analog switches may be in close proximity. That is, the switch circuit 50 may include only one analog switch 30, for example, see fig. 8, but does not constitute a limitation of the present application, and the switch circuit 50 may further include L analog switches, where L is a positive integer greater than or equal to 2.
In some possible implementations, referring to fig. 22, the switching circuit 50 includes two analog switches 30. The two analog switches 30 include a first analog switch 31 and a second analog switch 32. The first analog switch 31 and the second analog switch 32 are, for example, the same as the analog switch 30 in the corresponding embodiment of fig. 2, and reference may be specifically made to the description of each pin of the analog switch 30 in fig. 2, which is not described herein again. The switch circuit 50 further includes an enable node IN, a power supply node VCC, a common node COM, a ground node GND, and an input node N. The input node N includes a first input node NO1, a second input node NO2, a third input node NC1, and a fourth input node NC2. The enable nodes IN include a first enable node IN1 and a second enable node IN2. The common node COM includes a first common node COM1 and a second common node COM2. The ground nodes GND include a first ground node GND1 and a second ground node GND2. The power supply node VCC includes a first power supply node VCC1 and a second power supply node VCC2. A first input pin 1 corresponding to the first analog switch 31 is coupled to a first input node NO1, a ground pin 2 corresponding to the first analog switch 31 is coupled to a first ground node GND1, a second input pin 2 corresponding to the first analog switch 31 is coupled to a third input node NC1, an enable pin 4 corresponding to the first analog switch 31 is coupled to a first enable node IN1, a power supply pin 5 corresponding to the first analog switch 31 is coupled to a first power supply node VCC1, and a common pin 6 corresponding to the first analog switch 31 is coupled to a first common node COM 1. The first input pin 1 corresponding to the second analog switch 32 is coupled to the fourth input node NC2, the ground pin 2 corresponding to the second analog switch 32 is coupled to the second ground node GND2, the second input pin 3 corresponding to the second analog switch 32 is coupled to the second input node NO2, the enable pin 4 corresponding to the second analog switch 32 is coupled to the second enable node IN2, the power supply pin 5 corresponding to the second analog switch 32 is coupled to the second power supply node VCC2, and the common pin 6 corresponding to the second analog switch 32 is coupled to the second common node COM2.
Illustratively, the external interface 40 is, for example, USB 2.0. The USB signals include a positive differential signal USB _ DP and a negative differential signal USB _ DP. The low-speed analog signals include a left channel signal L and a right channel signal R.
Illustratively, when the transmitted signals are a positive differential signal USB _ DP and a negative differential signal USB _ DP, the first input node NO1 transmits the received positive differential signal USB _ DP to the first input pin 1 of the first analog switch 31, the first enable voltage received by the first enable node IN1 is transmitted to the enable pin 4 of the first analog switch 31 to control the common pin 6 of the first analog switch 31 to be conducted with the first input pin 1, and the positive differential signal USB _ DP is transmitted to the first common node COM1 through the analog switch 30 to be transmitted to an external device (e.g., a computer) through the first common node COM 1. Meanwhile, the second input node NO2 transmits the received negative differential signal USB _ DP to the second input pin 3 of the second analog switch 32, the second enable voltage received by the second enable node IN2 is transmitted to the enable pin 4 of the second analog switch 32 to control the common pin 6 of the second analog switch 32 to be conducted with the second input pin 3 of the second analog switch 32, and the negative differential signal USB _ DP is transmitted to the second common node COM2 through the analog switch 30 to be transmitted to the external device through the second common node COM2. Thereby realizing the transmission of the USB signal.
When the transmitted signals are a left channel signal L and a right channel signal R, the third input node NC1 transmits the received left channel signal L to the second input pin 3 of the first analog switch 31, the first enable voltage received by the first enable node IN1 is transmitted to the enable pin 4 of the first analog switch 31 to control the common pin 6 of the first analog switch 31 to be conducted with the second input pin 3, and the left channel signal L is transmitted to the first common node COM1 through the analog switch 30 to be transmitted to an external device (e.g., an earphone) through the first common node COM 1. Meanwhile, the fourth input node NC2 transmits the received right channel signal R to the first input pin 1 of the second analog switch 32, the second enable voltage received by the second enable node IN2 is transmitted to the enable pin 4 of the second analog switch 32 to control the common pin 6 of the second analog switch 32 to be conducted with the first input pin 1, and the right channel signal R is transmitted to the second common node COM2 through the analog switch 30 to be transmitted to the external device through the second common node COM2. Thereby realizing the transmission of the audio frequency analog signal.
Further, when the signal transmitted by the analog switch 30 is a differential signal, the above example (see fig. 22) is described by taking as an example that the impedance device 60 is coupled between the first ground node GND1 and the ground pin 2 of the first analog switch 31, the impedance device 60 is coupled between the first enable node IN1 and the enable pin 4 of the first analog switch 31, the impedance device 60 is coupled between the first power supply node VCC1 and the power supply pin 5 of the first analog switch 31, and the impedance device 60 is coupled between the second ground node GND2 and the ground pin 2 of the second analog switch 32, the impedance device 60 is coupled between the second enable node IN2 and the enable pin 4 of the second analog switch 32, and the impedance device 60 is coupled between the second power supply node VCC2 and the power supply pin 5 of the second analog switch 32. As can be seen from the foregoing, the impedance device 60 may also be coupled between only one of the pins and the node corresponding to that pin; alternatively, the impedance device 60 is coupled between one of the pins and a node corresponding to the pin; and between the other pin and the node corresponding to the pin. In this case, optionally, the number of the impedance devices 60 corresponding to the first analog switch 31 and the second analog switch 32 is the same, the types of the impedance devices 60 are the same, and the positions of the impedance devices 60 are the same, that is, the pins and the nodes corresponding to the impedance devices 60 are the same.
For example, referring to fig. 23, when the impedance device 60 is coupled between only one of the pins and a node corresponding to the pin, the impedance device 60 is coupled between the first ground node GND1 and the ground pin 2 of the first analog switch 31, and the impedance device 60 is coupled between the second ground node GND2 and the ground pin 2 of the second analog switch 32.
For another example, referring to FIG. 24, when an impedance device 60 is coupled between one of the pins and a node corresponding to the pin; and, when the impedance device 60 is coupled between another pin and a node corresponding to the pin, the impedance device 60 is coupled between the first ground node GND1 and the ground pin 2 of the first analog switch 31, the impedance device 60 is coupled between the first enable node IN1 and the enable pin 4 of the first analog switch 31, and the impedance device 60 is coupled between the second ground node GND2 and the ground pin 2 of the second analog switch 32, the impedance device 60 is coupled between the second enable node IN2 and the enable pin 4 of the second analog switch 32.
This is because the impedance device 60 corresponding to each analog switch 30 has the same influence (prevents signal leakage) on the differential signals (the positive differential signal USB _ DP and the negative differential signal USB _ DP), and the reliability of the signals is improved.
The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and these modifications or substitutions do not depart from the scope of the technical solutions of the embodiments of the present application.
Claims (9)
1. A switching circuit, comprising: at least one analog switch, an input node, a power supply node, a ground node, an enable node, a common node;
the analog switch comprises an input pin, a power supply pin, a grounding pin, an enabling pin and a public pin; the input pin is coupled with the input node, the power supply pin is coupled with the power supply node, the ground pin is coupled with the ground node, the enable pin is coupled with the enable node, and the common pin is coupled with the common node;
the switching circuit further includes: at least one impedance device; wherein the impedance device is coupled between at least one of the power pin and the power node, the ground pin and the ground node, and the enable pin and the enable node;
wherein the impedance device comprises an inductor, a magnetic bead, or a combination of an inductor and a capacitor;
when the analog switch is a low-speed analog switch, the switch circuit is used for transmitting a high-speed signal;
when the analog switch is a high-speed analog switch, the switch circuit is used for transmitting a higher-speed signal.
2. The switching circuit of claim 1, wherein the input node comprises a first input node and a second input node; the common nodes comprise a first common node and a second common node; the enabling nodes comprise a first enabling node and a second enabling node;
the first input node, the second input node, the first common node, the second common node, the first enable node, and the second enable node are coupled to different pins of the analog switch, respectively;
the first input node is for receiving a positive differential signal; the first enabling node is used for receiving a first enabling voltage and transmitting the first enabling voltage to an enabling pin coupled with the first enabling node so as to enable a common pin coupled with a first common node and an input pin coupled with the first input node to be conducted; a common pin coupled with the first common node for transmitting the positive differential signal to the first common node;
the second input node is for receiving a negative differential signal; the second enabling node is used for receiving a second enabling voltage and transmitting the second enabling voltage to an enabling pin coupled with the second enabling node so as to enable a common pin coupled with a second common node and an input pin coupled with the second input node to be conducted; a common pin coupled with the second common node is to transmit the negative differential signal to the second common node.
3. The switching circuit according to claim 2, comprising: at least two analog switches, including a first analog switch and a second analog switch;
the first input node is coupled with an input pin in the first analog switch, and the first common node is coupled with a common pin in the first analog switch;
the second input node is coupled to an input pin in the second analog switch, and the second common node is coupled to a common pin in the second analog switch.
4. The switch circuit of claim 3, wherein the number of the impedance devices corresponding to the first analog switch is the same as the number of the impedance devices corresponding to the second analog switch.
5. The switch circuit according to claim 3 or 4, wherein the position of the impedance device corresponding to the first analog switch and the position of the impedance device corresponding to the second analog switch are the same.
6. The switching circuit according to any of claims 1-4, wherein the switching speed of the analog switch is less than or equal to 100 MHz.
7. A switching circuit according to any one of claims 1-4, characterized in that the impedance value of the impedance device is larger than 600 ohms.
8. The switching circuit according to any one of claims 1 to 4, comprising: at least three of said impedance devices; three of the impedance devices are coupled between the ground node and the ground pin, between the enable node and the enable pin, and between the power node and the power pin, respectively.
9. An electronic device comprising the switching circuit according to any one of claims 1 to 8.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111235596.XA CN114039583B (en) | 2021-10-22 | 2021-10-22 | Switching circuit and electronic device |
| CN202211303211.3A CN116015258B (en) | 2021-10-22 | 2021-10-22 | Switching circuit and electronic device |
| PCT/CN2022/117899 WO2023065878A1 (en) | 2021-10-22 | 2022-09-08 | Switch circuit and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111235596.XA CN114039583B (en) | 2021-10-22 | 2021-10-22 | Switching circuit and electronic device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211303211.3A Division CN116015258B (en) | 2021-10-22 | 2021-10-22 | Switching circuit and electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114039583A CN114039583A (en) | 2022-02-11 |
| CN114039583B true CN114039583B (en) | 2022-10-28 |
Family
ID=80141766
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111235596.XA Active CN114039583B (en) | 2021-10-22 | 2021-10-22 | Switching circuit and electronic device |
| CN202211303211.3A Active CN116015258B (en) | 2021-10-22 | 2021-10-22 | Switching circuit and electronic device |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211303211.3A Active CN116015258B (en) | 2021-10-22 | 2021-10-22 | Switching circuit and electronic device |
Country Status (2)
| Country | Link |
|---|---|
| CN (2) | CN114039583B (en) |
| WO (1) | WO2023065878A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114039583B (en) * | 2021-10-22 | 2022-10-28 | 荣耀终端有限公司 | Switching circuit and electronic device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203537426U (en) * | 2013-09-13 | 2014-04-09 | 北京大明五洲科技有限公司 | Audio interface adjusting device and mobile terminal |
| CN106656132A (en) * | 2016-12-31 | 2017-05-10 | 唯捷创芯(天津)电子技术股份有限公司 | Extremely low current leakage analog switch, chip and communication terminal |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002208848A (en) * | 2001-01-10 | 2002-07-26 | Toshiba Microelectronics Corp | Semiconductor switching circuit |
| US7482853B2 (en) * | 2005-12-14 | 2009-01-27 | Intersil Americas Inc. | Method and apparatus for switching audio and data signals through a single terminal |
| JP2010220200A (en) * | 2009-02-19 | 2010-09-30 | Renesas Electronics Corp | Conduction switching circuit, conduction switching circuit block, and operation method for conduction switching circuit |
| US8344789B2 (en) * | 2010-01-20 | 2013-01-01 | Intersil Americas Inc. | Analog switch with internal device body control |
| CN102096651B (en) * | 2010-12-22 | 2016-03-30 | 努比亚技术有限公司 | Based on the handset port multiplex circuit of standard Micro USB interface |
| US8818298B2 (en) * | 2012-01-20 | 2014-08-26 | Samsung Electro-Mechanics Co., Ltd. | High frequency switch |
| JP2014135626A (en) * | 2013-01-10 | 2014-07-24 | Asahi Kasei Electronics Co Ltd | Analog switch circuit and variable attenuator using the same |
| US8836408B1 (en) * | 2013-03-15 | 2014-09-16 | Nxp B.V. | High-speed switch with signal-follower control offsetting effective visible-impedance loading |
| CN203870609U (en) * | 2014-04-08 | 2014-10-08 | 赛酷特(北京)信息技术有限公司 | Automatic USB communication and audio communication switching circuit |
| CN105979416B (en) * | 2016-05-30 | 2019-01-18 | 歌尔股份有限公司 | A kind of line control earphone |
| CN109286878B (en) * | 2017-07-21 | 2021-08-31 | 中兴通讯股份有限公司 | Signal transmission circuit |
| CN109885517B (en) * | 2017-12-06 | 2024-01-12 | 深圳市冠旭电子股份有限公司 | Switching circuit and terminal equipment |
| CN114039583B (en) * | 2021-10-22 | 2022-10-28 | 荣耀终端有限公司 | Switching circuit and electronic device |
-
2021
- 2021-10-22 CN CN202111235596.XA patent/CN114039583B/en active Active
- 2021-10-22 CN CN202211303211.3A patent/CN116015258B/en active Active
-
2022
- 2022-09-08 WO PCT/CN2022/117899 patent/WO2023065878A1/en unknown
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203537426U (en) * | 2013-09-13 | 2014-04-09 | 北京大明五洲科技有限公司 | Audio interface adjusting device and mobile terminal |
| CN106656132A (en) * | 2016-12-31 | 2017-05-10 | 唯捷创芯(天津)电子技术股份有限公司 | Extremely low current leakage analog switch, chip and communication terminal |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116015258B (en) | 2024-03-15 |
| CN114039583A (en) | 2022-02-11 |
| CN116015258A (en) | 2023-04-25 |
| WO2023065878A1 (en) | 2023-04-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104185955B (en) | There is the transceiver of the configurable passive network of integrated RX/TX | |
| CN109088626B (en) | Ultralow-power-consumption biased radio frequency switch | |
| US20210089100A1 (en) | Usb type-c signal interface circuit | |
| US6774701B1 (en) | Method and apparatus for electronic switching with low insertion loss and high isolation | |
| US9183162B2 (en) | Electronic device capable of being debugged via earphone port | |
| US9294598B2 (en) | Switch circuit | |
| US7664012B2 (en) | Solid-state ethernet by-pass switch circuitry | |
| CN114039583B (en) | Switching circuit and electronic device | |
| US11445276B2 (en) | Multiplexing circuit and mobile terminal | |
| CN110365360B (en) | Radio frequency switch circuit and radio frequency switch device | |
| US20120243712A1 (en) | Switch and switch circuit using the same | |
| CN201323446Y (en) | Static-free handheld mobile device with soft USB function | |
| WO2022042199A1 (en) | Interface circuit, protection method for same, and terminal device | |
| US11329647B2 (en) | Radio frequency switch circuit | |
| US20140380080A1 (en) | Energy-saving circuit for motherboard | |
| KR20190138550A (en) | Single-pole double-throw(spdt) switch and transmitting-receiving circuit with high linearity | |
| US20230318576A1 (en) | Switching circuit and front end circuit | |
| KR101921072B1 (en) | Switch circuit including switched inductor structure | |
| US8120421B2 (en) | Circuit structure free from test effect and testing method thereof | |
| CN207475884U (en) | A kind of interface test circuitry and interface test system | |
| KR20140086487A (en) | Radio frequency switch circuit | |
| CN219577036U (en) | Level conversion circuit from low voltage to positive and negative voltage | |
| CN115622586B (en) | High-integration radio frequency switch chip | |
| CN113014241A (en) | Broadband radio frequency switch architecture | |
| CN213152209U (en) | Interface circuit and interface circuit system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| REG | Reference to a national code |
Ref country code: HK Ref legal event code: DE Ref document number: 40069154 Country of ref document: HK |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |