CN114036087A - System for realizing data delay processing based on FPGA storage unit - Google Patents
System for realizing data delay processing based on FPGA storage unit Download PDFInfo
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- CN114036087A CN114036087A CN202111298358.3A CN202111298358A CN114036087A CN 114036087 A CN114036087 A CN 114036087A CN 202111298358 A CN202111298358 A CN 202111298358A CN 114036087 A CN114036087 A CN 114036087A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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Abstract
The invention relates to a system for realizing data delay processing based on an FPGA (field programmable gate array) storage unit, which comprises a data input control module, a data processing module and a data processing module, wherein the data input control module is used for selecting the storage unit and sequentially and circularly storing data blocks according to the sequence of the storage unit; the data storage module comprises a plurality of storage units, and the storage units are connected with the data input control module and used for sequentially and circularly storing the data blocks; the data output control module is connected with the plurality of storage units and is used for reading data in the storage module; and the data exchange output module is connected with the data output control module and is used for delaying the output data. The system for realizing data delay processing based on the FPGA storage unit adopts non-traditional delay in a non-shift register or counter mode, realizes delay by using data storage selection, determines the number of data delay according to the depth of the storage unit, can realize single-path data delay and multi-path data delay, and is flexible in configuration.
Description
Technical Field
The invention relates to the field of instruments and meters, in particular to the field of digital signal delay processing, and specifically relates to a system for realizing data delay processing based on an FPGA (field programmable gate array) storage unit.
Background
The Field Programmable Gate Array (FPGA) has the characteristics of high programming flexibility, short development period, high parallel computing efficiency and the like, and is widely applied to communication systems and various electronic devices. In digital signal processing, especially in digital filtering systems, a delay is artificially added to a signal to meet the computational requirements in design.
Generally, a time delay module adopts a shift register mode or a storage counting mode, and in some special applications, the time delay modes either consume a large amount of trigger resources or cannot output multi-path parallel time delay data, and resources of an FPGA cannot be well utilized. The invention adopts a brand-new design idea and combines ping-pong operation to realize the time delay of data. Not only can output single-path delay data, but also can output multi-path parallel delay data.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides the system for realizing the data delay processing based on the FPGA storage unit, which has the advantages of high accuracy, low consumption and wider application range.
In order to achieve the above object, the system for implementing data delay processing based on the FPGA storage unit of the present invention is as follows:
the system for realizing data delay processing based on the FPGA storage unit is mainly characterized by comprising the following components:
the data input control module is used for selecting the storage units and sequentially storing the storage units into the data blocks in a circulating manner according to the sequence of the storage units;
the data storage module comprises a plurality of storage units, and the storage units are connected with the data input control module and used for sequentially and circularly storing data blocks in sequence;
the data output control module is connected with the plurality of storage units and is used for reading data in the storage module;
and the data exchange output module is connected with the data output control module and is used for delaying the output data.
Preferably, the data input control module buffers the data blocks to the storage units in sequence, and if all the storage units are full, the data in the storage units are overwritten from the first storage unit in sequence.
Preferably, the data output control module finds out the currently written storage unit according to the control signal, excludes the currently written storage unit from the read list, and reads the data after updating the data block to obtain the delayed output.
Preferably, the data exchange output module maps the read data to the output port according to the actual output sequence, and realizes the delayed output at the parallel output end.
Preferably, the number of the storage units is N, the number of parallel data output paths is N-1, and the depth of the storage units is the number of data of the data blocks.
The system for realizing data delay processing based on the FPGA storage unit adopts the non-traditional delay of a non-shift register or a counter mode and realizes the delay by utilizing data storage selection. The invention determines the number of data delay according to the depth of the storage unit, can realize single-path data delay and multi-path data delay, and has flexible configuration.
Drawings
Fig. 1 is an overall block diagram of a delay structure of a system for implementing data delay processing based on an FPGA storage unit according to the present invention.
Detailed Description
In order to more clearly describe the technical contents of the present invention, the following further description is given in conjunction with specific embodiments.
The system for realizing data delay processing based on the FPGA storage unit comprises:
the data input control module is used for selecting the storage units and sequentially storing the storage units into the data blocks in a circulating manner according to the sequence of the storage units;
the data storage module comprises a plurality of storage units, and the storage units are connected with the data input control module and used for sequentially and circularly storing data blocks in sequence;
the data output control module is connected with the plurality of storage units and is used for reading data in the storage module;
and the data exchange output module is connected with the data output control module and is used for delaying the output data.
In a preferred embodiment of the present invention, the data input control module sequentially buffers the data blocks in the storage units, and sequentially overwrites the data in the storage units from the first storage unit if all the storage units are full.
As a preferred embodiment of the present invention, the data output control module finds out a currently written storage unit according to the control signal, excludes the currently written storage unit from the read list, and reads data after updating the data block to obtain the delayed output.
As a preferred embodiment of the present invention, the data exchange output module maps the read data to the output port according to the actual output sequence, and realizes the delayed output at the parallel output port.
In a preferred embodiment of the present invention, the number of the storage units is N, the number of parallel data output paths is N-1, and the depth of the storage units is the number of data in the data block.
In the specific implementation mode of the invention, a plurality of logic storage units are used, and a serial data input and multi-path parallel delay data output delay structure is completed through selection signal control in a ping-pong operation-like mode.
The invention adopts the following technical scheme for solving the technical problems:
the invention provides a digital signal delay scheme, which has a composition structure as shown in figure 1 and mainly comprises four parts: the device comprises a data input control module, a data storage module, a data output control module and a data exchange output module. And selecting units for storage through the input control module, and sequentially storing the units in a circulating manner according to the sequence of the storage units. In order to prevent the simultaneous occurrence of data writing and reading operations on the storage units, one storage unit is added according to the number of delays to form a mode similar to ping-pong operation, and the storage units which are being written in can be avoided by reading control whenever the reading operation is performed, so that the integrity of data is ensured. Because the sequential combination of the reading units is a loop sequence formed by the storage units, the output is adjusted according to the reading units, thereby ensuring that the time delay between the parallel data is output in order.
As shown in fig. 1, the input data may be a single serial data or a group of data may be transmitted in a serial manner. After receiving the data, the input control module buffers a data or a group of data into the storage unit 1, and at this time, the data or the group of data is called a data block. When the second data block arrives, the data input control module buffers the second data block into the storage unit 2, each subsequent data block is sequentially buffered into the storage unit, and when all the storage units are full, the data of the storage unit is sequentially overwritten by the future data from the beginning. The number of the storage units is reduced by one to represent the number of paths of parallel output data, and the depth of the storage units represents the number of data of one data block.
Assuming that the number of the storage units is N, the number of the parallel data output paths is N-1, and the purpose of doing so is to protect the module currently writing data from being read in a ping-pong operation-like manner, thereby ensuring the integrity of the data.
The data output control module is used for reading data in the storage module, the reading principle is that a currently written storage unit is found out according to a control signal and is excluded from the row of the reading module, and data is read once after a new data block is followed each time, so that N-1 paths of delay output are obtained.
The data delay lengths read by the data output control module are not necessarily arranged in order, and at the moment, the data exchange output module is needed to map the read data to the output ports according to the actual output sequence of the data, so that the delay output is realized at the parallel output ends. The default condition is multi-path delay output, and when only one path of delay output is needed, only the data port is needed to be connected to the corresponding delay port.
The system for realizing data delay processing based on the FPGA storage unit adopts the non-traditional delay of a non-shift register or a counter mode and realizes the delay by utilizing data storage selection. The invention determines the number of data delay according to the depth of the storage unit, can realize single-path data delay and multi-path data delay, and has flexible configuration.
In this specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (5)
1. A system for realizing data delay processing based on FPGA memory cell is characterized in that the system comprises:
the data input control module is used for selecting the storage units and sequentially storing the storage units into the data blocks in a circulating manner according to the sequence of the storage units;
the data storage module comprises a plurality of storage units, and the storage units are connected with the data input control module and used for sequentially and circularly storing data blocks in sequence;
the data output control module is connected with the plurality of storage units and is used for reading data in the storage module;
and the data exchange output module is connected with the data output control module and is used for delaying the output data.
2. The system for realizing data delay processing based on the FPGA storage unit as recited in claim 1, wherein the data input control module sequentially buffers the data blocks into the storage units, and if all the storage units are full, the data in the storage units are sequentially overwritten from the first storage unit.
3. The system according to claim 1, wherein the data output control module finds a currently written memory cell according to the control signal, excludes the currently written memory cell from the read list, and reads data after updating the data block to obtain the delayed output.
4. The system according to claim 1, wherein the data switching output module maps the read data to the output ports according to the actual output sequence, and implements the delayed output at the parallel output ports.
5. The system for realizing data delay processing based on the FPGA storage unit as recited in claim 1, wherein the number of the storage units is N, the number of parallel data output paths is N-1, and the depth of the storage units is the number of data of the data blocks.
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| CN202111298358.3A CN114036087A (en) | 2021-11-04 | 2021-11-04 | System for realizing data delay processing based on FPGA storage unit |
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| CN202111298358.3A CN114036087A (en) | 2021-11-04 | 2021-11-04 | System for realizing data delay processing based on FPGA storage unit |
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