CN114024433A - Jitter frequency period control method and related device - Google Patents

Jitter frequency period control method and related device Download PDF

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Publication number
CN114024433A
CN114024433A CN202210005145.5A CN202210005145A CN114024433A CN 114024433 A CN114024433 A CN 114024433A CN 202210005145 A CN202210005145 A CN 202210005145A CN 114024433 A CN114024433 A CN 114024433A
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value
pwm
prd
period
counting
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CN202210005145.5A
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CN114024433B (en
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谢谦
张煌玉
李晨光
张凯旋
张宇星
陈余金
邓智伟
朱建国
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Shenzhen Winline Technology Co Ltd
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Shenzhen Winline Technology Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H02M3/33515—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with digital control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/3353—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having at least two simultaneously operating switches on the input side, e.g. "double forward" or "double (switched) flyback" converter

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The application provides a frequency jittering period control method and a related device, wherein the method is applied to a switching power supply circuit, the switching power supply circuit comprises a controller, a multi-channel Pulse Width Modulation (PWM) control circuit and a plurality of primary side control switch tubes, the controller is connected with the multi-channel PWM control circuit, the multi-channel PWM control circuit is connected with the plurality of primary side control switch tubes, and the method comprises the following steps: obtaining the period value PRD of the multi-channel pulse width modulation PWM control circuit; judging whether the period value PRD needs to be updated or not; if the period value PRD needs to be updated, judging whether the value of at least one PWM carrier counter is larger than a preset value; and if the value of at least one PWM carrier counter is larger than a preset value, updating the period value PRD. By the method, the wave-generating abnormity can be avoided, and the related power supply equipment can be protected.

Description

Jitter frequency period control method and related device
Technical Field
The application belongs to the field of switching power supply circuit control, and particularly relates to a frequency jittering period control method and a related device.
Background
At present, the frequency of the internal switching tube is changed periodically by updating the period value of a PWM signal transmitted by Pulse Width Modulation (PWM) to achieve a "frequency jitter" effect, but there may be a situation that the period values of multiple PWMs are not updated in the same period when the PWM period value is updated, which causes PWM wave-sending abnormality and easily causes damage to power equipment.
Disclosure of Invention
The application provides a frequency jittering period control method and a related device, which are used for avoiding the situation of abnormal wave generation and protecting related power supply equipment.
In a first aspect, an embodiment of the present application provides a method for controlling a jitter frequency period, where the method is applied to a switching power supply circuit, the switching power supply circuit includes a controller, a multi-channel PWM control circuit, and a plurality of primary side control switching tubes, the controller is connected to the multi-channel PWM control circuit, and the multi-channel PWM control circuit is connected to the plurality of primary side control switching tubes, and the method includes:
obtaining the period value PRD of the multi-channel pulse width modulation PWM control circuit;
judging whether the period value PRD needs to be updated or not;
if the period value PRD needs to be updated, judging whether the value of at least one PWM carrier counter is larger than a preset value, the preset value is used for indicating a target time interval, the target time interval is a union of a plurality of sub-time intervals corresponding to a plurality of zero-counting time nodes, the plurality of zero-counting time nodes correspond to a plurality of paths of PWM control circuits for performing PWM control on the plurality of primary side control switch tubes one by one, the zero-counting time node is a time node corresponding to the position of a counting 0 point of a carrier counter in the process of outputting a PWM signal by each path of PWM control circuit, and the time starting point of the target time interval is a first zero-counting time node of a first PWM control circuit PWM1 in the multi-path PWM control circuit, any zero-counting time node except the first zero-counting time node in the plurality of zero-counting time nodes and the first zero-counting time node do not have other zero-counting time nodes of the local path;
and if the value of at least one PWM carrier counter is greater than a preset value, updating the period value PRD, wherein the value of the PWM carrier counter is greater than the preset value and is used for indicating that the current time node is in any time node outside the target time period.
In a second aspect, an embodiment of the present application provides a jitter cycle control apparatus, including:
the acquisition unit is used for acquiring the period value PRD of the multi-channel pulse width modulation PWM control circuit; a first judging unit, configured to judge whether the period value PRD needs to be updated; a second determining unit, configured to determine whether there is at least one carrier counter of the PWM having a value greater than a preset value when the period value PRD needs to be updated, the preset value is used for indicating a target time interval, the target time interval is a union of a plurality of sub-time intervals corresponding to a plurality of zero-counting time nodes, the plurality of zero-counting time nodes correspond to a plurality of paths of PWM control circuits for performing PWM control on the plurality of primary side control switch tubes one by one, the zero-counting time node is a time node corresponding to the position of a counting 0 point of a carrier counter in the process of outputting a PWM signal by each path of PWM control circuit, and the time starting point of the target time interval is a first zero-counting time node of a first PWM control circuit PWM1 in the multi-path PWM control circuit, any zero-counting time node except the first zero-counting time node in the plurality of zero-counting time nodes and the first zero-counting time node do not have other zero-counting time nodes of the local path; and the updating unit is used for updating the period value PRD when the value of at least one PWM carrier counter is larger than a preset value, wherein the value of the PWM carrier counter is larger than the preset value and is used for indicating that the current time node is positioned at any time node outside the target time period.
In a third aspect, an embodiment of the present application provides an electronic device, including a processor, a memory, a communication interface, and one or more programs, stored in the memory and configured to be executed by the processor, the programs including instructions for performing the steps in the first aspect of the embodiment of the present application.
In a fourth aspect, the present application provides a computer storage medium, which is characterized by storing a computer program for electronic data exchange, wherein the computer program enables a computer to perform some or all of the steps described in the first aspect of the present embodiment.
In a fifth aspect, embodiments of the present application provide a computer program product, where the computer program product includes a non-transitory computer-readable storage medium storing a computer program, where the computer program is operable to cause a computer to perform some or all of the steps as described in the first aspect of the embodiments of the present application.
It can be seen that, in the embodiment of the present application, a period value PRD of a multi-channel PWM control circuit in a switching power supply circuit is first obtained, and then it is determined whether the period value PRD needs to be updated, and if the period value PRD needs to be updated, it is determined whether a value of at least one PWM carrier counter is greater than a preset value, where the preset value is used to indicate a target time period, a wave-sending abnormal situation may occur when the period value is updated in the target time period, and if the value of the at least one PWM carrier counter is greater than the preset value, the period value PRD is updated, and the value of the PWM carrier counter is greater than the preset value and is used to indicate that a current time node is located at any time node outside the target time period. Therefore, by comparing the magnitude relation between the carrier counter value and the preset value, the periodic value is ensured to be updated outside the target time period, so that the wave-sending abnormity is avoided, and the related power supply equipment is prevented from being damaged.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a switching power supply circuit according to an embodiment of the present application;
fig. 2 is a flowchart illustrating a method for controlling a dithering cycle according to an embodiment of the present application;
FIG. 3 is a block diagram of a characterization target period provided by an embodiment of the present application;
fig. 4 is a diagram of a two-way two-level phase-shifted full bridge according to an embodiment of the present application;
fig. 5 is a wave-sending control diagram of a two-way interleaved parallel phase-shifted full bridge according to an embodiment of the present application;
fig. 6 is a block diagram illustrating functional units of a jitter cycle control apparatus according to an embodiment of the present disclosure;
fig. 7 is a block diagram of an electronic device according to an embodiment of the present disclosure.
Detailed Description
In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
The following description will first be made with respect to terms related to the present application.
Pulse Width Modulation (PWM): the switching regulator is an analog control mode, and the bias of a transistor base electrode or an MOS tube grid electrode is modulated according to the change of corresponding load to change the conduction time of the transistor or the MOS tube, so that the change of the output of the switching regulator is realized; the pulse train with equal pulse width is used as PWM waveform, frequency modulation is realized by changing the period of the pulse train, voltage regulation is realized by changing the width or duty ratio of the pulse, and the voltage and the frequency can be changed coordinately by adopting a proper control method. The purpose of controlling the charging current can be achieved by adjusting the period of PWM and the duty ratio of PWM.
Frequency jittering: the method refers to that the frequency of an internal switching tube in a switching power supply circuit is changed periodically, and is mainly realized by updating the period value of PWM.
Dead time: the PWM output is a protection period set for preventing the upper and lower tubes of the H-bridge or half H-bridge from being turned on simultaneously due to the off delay problem of the switch, and is also generally referred to as PWM response time.
At present, the frequency of an internal switching tube in a switching power supply circuit is changed periodically by updating the period value of PWM (pulse width modulation), so that frequency jitter is realized, the period value of the PWM is updated and then acts after a carrier counter of the PWM passes 0, and ideally, assignment of the period value of each PWM can be completed in a very short time. If the carrier counter crosses zero before the period value of the PWM is updated in this period, the period value of the PWM is actually effective only after the carrier crosses zero next time, which may cause abnormal PWM wave generation and damage to the related power supply devices.
To solve the above problem, embodiments of the present application provide a method for controlling a jitter period, which can be applied to a switching power supply circuit controlled by interleaving multiple phases. By selecting the updating time point of the period value, the condition that all carrier wave counters have zero crossing in the updating process is ensured, and the period values of all paths can be synchronously updated. The application is suitable for the power module for realizing the frequency jittering control through digital control, and particularly comprises but is not limited to application scenes such as an electric automobile charging module and a digital power supply.
The following describes a switching power supply circuit architecture according to an embodiment of the present application.
Referring to fig. 1, fig. 1 is a schematic diagram of a switching power supply circuit according to an embodiment of the present disclosure. The switching power supply circuit comprises a controller 100, a multi-path Pulse Width Modulation (PWM) control circuit 101 and a plurality of primary side control switching tubes 102, wherein the controller 100 is connected with the multi-path PWM control circuit 101, and the multi-path PWM control circuit 101 is connected with the primary side control switching tubes 102. The controller 100 may be a combinational logic controller or a micro-program controller.
A method for controlling a jitter period according to an embodiment of the present application is described below.
Referring to fig. 2, fig. 2 is a schematic flow chart of a frequency jittering period control method provided in an embodiment of the present application, where the frequency jittering period control method is applied to a switching power supply circuit, the switching power supply circuit includes a controller, a multi-channel PWM control circuit, and a plurality of primary side control switching tubes, the controller is connected to the multi-channel PWM control circuit, and the multi-channel PWM control circuit is connected to the plurality of primary side control switching tubes. As shown in the figure, the jitter frequency period control method includes:
step 201, obtaining the period value PRD of the multi-channel PWM control circuit.
The multi-channel Pulse Width Modulation (PWM) control circuit can be set by a user according to needs, the setting content comprises the number of the primary side control switch tubes and the number of the PWM control circuits, and the PWM control circuits are exemplarily set as PWM1, PWM2, PWM3 and PWM4, and eight primary side control switch tubes are set as Q1/Q2/Q3/Q4/Q5/Q6/Q7/Q8. The period value PRD may be calculated according to a type of a Digital Signal processing chip (DSP) selected by a user and a switching frequency, for example, the DSP may select 28035, the frequency is 60M, the switching frequency is 70K, and the PWM carrier counter selects an increment or decrement mode, so that the corresponding PRD period value is 60M/70K/2= 428.
Step 202, determine whether the period value PRD needs to be updated.
Step 203, if the period value PRD needs to be updated, it is determined whether the value of at least one PWM carrier counter is greater than a preset value.
The preset value is used for indicating a target time period, the target time period is a union set of a plurality of sub-time periods corresponding to a plurality of zero-counting time nodes, the plurality of zero-counting time nodes are in one-to-one correspondence with a plurality of primary-side control switching tubes (PWM) controlled multi-path PWM control circuits, the zero-counting time node is a time node corresponding to a counting 0 point of a carrier counter in a process of outputting a PWM signal by each path of PWM control circuit, a time starting point of the target time period is a first zero-counting time node of a first path PWM1 in the multi-path PWM control circuits, and other zero-counting time nodes of the path do not exist between any zero-counting time node except the first zero-counting time node and the first zero-counting time node.
When the period value PRD is updated at a certain time node in the target time period, the wave-sending abnormity can occur. To assist understanding, please refer to fig. 3, fig. 3 is a diagram for characterizing a target time period according to an embodiment of the present application. As shown in fig. 3, the time node when the carrier counter of PWM1 is 0 is t1, the time node when the carrier counter of PWM2 is 0 is t2, the time node when the carrier counter of PWM3 is 0 is t3, the time period from t1 to t2 represents the sub-time period for PWM1 and PWM2, and a wave-making abnormal situation may occur when the PWM1 and PWM2 update the period value in this time period; likewise, t2 to t3 represent sub-periods for PWM2 and PWM3, and t1 to t3 represent sub-periods for PWM1 and PWM3, if the above-mentioned PWM1, PWM2 and PWM3 exist at the same time, the target periods are the union of the above-mentioned sub-period t1 to t2 period, sub-period t2 to t3 period and sub-period t1 to t3 period, that is, t1 to t3 period.
In step 204, if the value of at least one of the PWM carrier counters is greater than a preset value, the period value PRD is updated.
And the value of the carrier counter of the PWM is greater than the preset value and is used for indicating that the current time node is located at any time node outside the target time interval.
When the value of each path of PWM carrier counter is smaller than the preset value, the current time node is in the target time interval; when the value of at least one PWM carrier counter is larger than a preset value, the current time node is represented to be any time node outside the target time period, and the situation of wave generation abnormity can be avoided by updating the period value.
It can be seen that, in this example, a period value PRD of a multi-channel PWM control circuit is first obtained, and then it is determined whether the period value PRD needs to be updated, if the period value PRD needs to be updated, it is determined whether a value of at least one carrier counter of the PWM is greater than a preset value, where the preset value is used to indicate a target time period, when the period value is updated in the target time period, a wave-sending abnormal situation may occur, and if the value of the at least one carrier counter of the PWM is greater than the preset value, the period value PRD is updated, and the value of the carrier counter of the PWM is greater than the preset value and is used to indicate that a current time node is located at any time node outside the target time period. Therefore, by comparing the magnitude relation between the carrier counter value and the preset value, the periodic value is ensured to be updated outside the target time period, so that the wave-sending abnormity is avoided, and the related power supply equipment is prevented from being damaged.
In one possible example, the multi-channel PWM control circuit includes the first PWM control circuit PWM1, a PWMx in phase with PWM1, and a PWMy lagging PWM1 α degrees in phase, the PWMy being offset from the PWM1 by a phase offset P, where P = (α/360) × 2 × PRD, 1< P < PRD-t, t is a time margin required to load the PWM cycle PRD.
With PWM1 as the main component, after PWM1 sends out a synchronization signal, the carrier counters of the other PWMs are synchronized to a set phase value, which is the phase offset P. Illustratively, PWM2 is in phase with PWM1, PWM3 is in phase with PWM4, and PWM3 and PWM4 lag PWM1 and PWM2 by 90 degrees in phase, i.e., the phase offset P =90/360 × 2 × 428=214, i.e., the carrier counter synchronization of PWM3 and PWM4 has a phase value of 214.
It can be seen that, in this example, the phase staggering between the PWMs is realized by changing the synchronous phase value of the PWM, so that the frequency of the internal switching tube is periodically changed by updating the period value of the PWM in the following, thereby realizing the frequency jitter.
In one possible example, after the obtaining the period value PRD of the multiple PWM control circuits, the method further includes: enabling the PWM control circuit, wherein the carrier counter of the PWM1 starts counting from 0, the upper limit of the counting is the period value PRD, and when the counting value of the carrier counter of the PWM1 is the period value PRD, the counting direction is changed, namely, the counting is carried out from the period value PRD to 0; when the count value of the carrier counter of the PWM1 is 0, the PWM1 sends a synchronization signal; when the PWMx receives the synchronization signal, the carrier counter of the PWMx has a value of 0, and the count direction is the same as the count direction of the carrier counter of the PWM1, i.e., the count direction is from 0 to the period value PRD, and when the count value of the carrier counter of the PWMx is 0, the count direction is changed, i.e., the count direction is from the period value PRD to 0; when the PWMy receives the synchronization signal, the carrier counter of the PWMy takes the value of the phase offset P, and the count direction is opposite to the count direction of the carrier counter of the PWM1, i.e. counting from P to 0, and when the count value of the carrier counter of the PWMy is 0, the count direction is changed, i.e. counting from 0 to the period value PRD.
After the PWM control circuit is enabled, the carrier counter of the main PWM1 starts to count from 0 to the period value PRD, changes the counting direction when reaching the period value PRD, and counts from the period value PRD to 0, and when reaching 0 again, completes one period. Each time the carrier counter of PWM1 counts to 0, a synchronization signal is sent, and when the other PWM receives the synchronization signal, its own carrier counter synchronizes to the phase offset P. For example, if the phases of PWM2 and PWM1 are the same, the initial count value and the count direction of the PWM2 carrier counter are completely the same as those of PWM1, and are not described herein again; PWM3 and PWM4 lag PWM1 by 90 degrees in phase angle and P =214, then PWM3 and PWM4 carrier counter sync value is 214, count direction is opposite to PWM1, i.e., count from 214 to 0, when 0 is reached, change count direction, count from 0 to period value 428, when period value 428 is reached, change count direction again, count from 428 to 0, where one period is completed when 214 is reached again in the process of counting from 428 to 0. In other words, when each PWM carrier counter goes through 856 steps, one cycle is completed.
In this example, the carrier counter of each PWM is in an increment or decrement mode, and the PWM1 sends a synchronization signal to enable other PWMs to synchronize the phase offset and the counting direction of the carrier counter according to the phase relationship with the PWM1, thereby ensuring the stability of the whole circuit.
In one possible example, after enabling the PWM control circuit, PWMn sends a PWM signal in a preset signaling manner, n being a positive integer.
Here, PWMn may be PWM1, PWMx having the same phase as PWM1, or PWMy having a lagging PWM1 phase angle degree of α degrees. Illustratively, n =1,2,3,4, i.e., PWM1, PWM2, PWM3, PWM4, transmit respective PWM signals in a preset signaling manner.
In one possible example, said PWMn sending PWM signals in a preset signaling manner after said enabling said PWM control circuit, n being a positive integer, comprises: the PWMn is divided into PWMnA and PWMnB, the PWMnA controls a first level switch of a first primary side control switch tube, the PWMnB controls a second level switch of a second primary side control switch tube, and the level switches comprise: the first primary side control switch tube is set to be at a high level when the count value of the PWMn carrier counter is a first comparison value, and is set to be at a low level when the count value of the PWMn carrier counter is a second comparison value; the second primary side control switch tube is set to be at a high level when the count value of the PWMn carrier counter is a third comparison value, and is set to be at a low level when the count value of the PWMn carrier counter is a fourth comparison value; and the PWMn transmits the PWM signal by controlling the level conversion of the primary side control switching tube.
To assist understanding, please refer to fig. 4, fig. 4 is a diagram of a two-way two-level phase-shifted full bridge according to an embodiment of the present application. As shown in fig. 4, the circuit main components include: inputting a direct current positive bus voltage Vbus +; inputting a direct current bus voltage Vbus-; inputting a bus capacitor Cin; an upper circuit primary side control switch tube Q1/Q2/Q3/Q4, a lower circuit primary side control switch tube Q5/Q6/Q7/Q8; an upper circuit primary side resonant capacitor Cr1, an upper circuit primary side resonant inductor Lr1, an upper circuit main transformer T1, a lower circuit primary side resonant capacitor Cr2, a lower circuit primary side resonant inductor Lr2 and a lower circuit main transformer T2; an upper secondary side full-bridge rectifier diode D1/D2/D3/D4, an upper output filter inductor Lf1, a lower secondary side full-bridge rectifier diode D5/D6/D7/D8 and a lower output filter inductor Lf 2; an output filter capacitor Cout; and outputting an equivalent load Rout.
The PWM configuration wave-emitting mode is as follows, PWMn is divided into PWMnA and PWMnB, the PWMnA and the PWMnB are designed to complement wave-emitting, and the wave-emitting is prevented from having an overlapping part by setting dead time. Illustratively, PWM1A controls Q1, PWM2A controls Q4, PWM3A controls Q5, and PWM4A controls Q8. PWM1B controls Q2 wave generation, PWM2B controls Q3 wave generation, PWM3B controls Q6 wave generation, and PWM4B controls Q7 wave generation.
After each PWM is enabled, the carrier counter is always updated, and in order to generate the PWM signal, a comparison value CMP (compare) is generally set, and when the value of the carrier counter matches the comparison value CMP, a high level or a low level corresponding to the PWM output may be set. For each timing period, the value of the corresponding comparator is changed, so that signals with different pulse widths can be obtained, and a duty ratio signal is generated to control the MOSFET to be switched off and switched on. For example, the PWM1A to PWM4A all issue a high level when their carrier counter is at a rising edge and reaches a value corresponding to the comparison value CMPA, and issue a low level when their carrier counter is at a falling edge and reaches a value corresponding to the comparison value CMPB. The PWM 1B-PWM 4B are all in the state that the carrier counter of the PWM 1-PWM 4-PWM controller sends out low level when the carrier counter is at the rising edge and reaches the value corresponding to the comparison value CMPA, and sends out high level when the carrier counter is at the falling edge and reaches the value corresponding to the comparison value CMPB.
To assist understanding, please refer to fig. 5, in which fig. 5 is a wave-sending control diagram of a two-way interleaved parallel phase-shifted full bridge according to an embodiment of the present application. As shown in fig. 5, cnt (count) indicates the value of the carrier counter. The dead time is set to t2+ t3, the comparison value CMPA of the PWM1 is fixed to the period value PRD, 428, and the comparison value CMPB is fixed to 0. Then Q1 is set high at PRD and low at 0, Q2 is set low at PRD-t2 and high at t 3. For convenience of description, in this example, the dead time is not considered, and Q1 is set to high when the carrier counter is PRD =428 and low when 0 is set, and Q2 is set to low when the carrier counter is PRD =428 and high when 0 is set. The comparison value CMPA of the PWM2 is the loop calculation result Piout, and the comparison value CMPB is the period value PRD-Piout. Then Q4 handles high for Piout at the carrier counter and low at PRD-Piout. Q3 handles low for Piout at the carrier counter and high at PRD-Piout. The waveforms of PWM3, PWM4 and PWM1, 2 are identical, but phase-delayed by 90 degrees. Q5 handles high for PRD at the carrier counter and low at 0. Q6 handles low for PRD at the carrier counter and high at 0. Q8 handles high for Piout at the carrier counter and low at PRD-Piout. Q7 handles low for Piout at the carrier counter and high at PRD-Piout.
Continuing with FIG. 5, it can be seen that if the PWM period values are updated within the time periods T1-T2, the carrier timers of PWM1 and PWM2 have passed zero, and the PWM period values are not updated in the present period, which is still 70K (428). And PWM3 and PWM4 lag by 90 degrees, so the update period value is zero-crossed after the carrier counter has gone through 214 steps. For example, the period is changed from 70K (428) to 70.16K (429). After the PWM1 sends out the synchronization signal at the zero crossing of the next cycle, the carrier timers of PWM3 and PWM4 go 856 steps, but the value of the carrier counter is 216, and then the time of 215 in the carrier counter is skipped directly, and the synchronization is performed to 214 directly. When the output voltage and current of the switching power supply are different, the corresponding duty ratio is also changed. If the value of the duty ratio Piout calculated by the loop is 214, then for the PWM4, the PRD-Piout value is 429-214=215, Q7 needs to be high at the time when the carrier counter is 215, Q8 needs to be low at the time when the carrier counter is 215, and since this time has been skipped, Q7 is still low and Q8 is still high, the problem of abnormal wave generation is caused, and there is a safety hazard. In fact, due to the arrangement of the dead zone, only one of the wave transmissions of Q7 and Q8 is abnormal in the same period.
It can be seen that, in this example, the PWM is caused to emit waves by configuring the wave emitting manner and level conversion, and staggered wave emitting is implemented based on the PWM with different phases, which is beneficial to improving the stability of the circuit.
In one possible example, before the determining whether the period value PRD needs to be updated, the method further includes: acquiring program running time, wherein the program starts to run when the PWM control circuit is enabled; and when the program running time reaches the preset time, the program is suspended from running.
The preset time can be set through the time _ isr function, after a fixed time interval, the running of the program is suspended, a subsequent judgment strategy is entered, whether the period value PRD needs to be updated or not is judged, if the period value needs to be updated at the time node, a subsequent judgment process is entered, if the condition is met, the period value is allowed to be updated, and if the condition is not met, the period value is not allowed to be updated.
It can be seen that, in this example, by adding the method of suspending program operation to update the period value only outside the target time period, the wave-emitting abnormality can be effectively avoided.
In a possible example, the determining whether the value of at least one carrier counter of the PWM is greater than a preset value if the period value PRD needs to be updated includes: the preset value is the sum of a phase offset Pmax corresponding to the PWM with the maximum phase offset in the PWM and a time margin t required for loading the PWM period value PRD.
As can be seen from FIG. 5, the time period between the target time periods T1-T2 is expressed as: (PWM1 Carrier counter < (214+ t) & & PWM4 Carrier counter < (214+ t)). Considering that loading PWM requires a time margin t, a wave-launching exception can be avoided as long as the PWM period value is updated within the period of time (PWM1 carrier counter > (214+ t) | (PWM4 carrier counter >214+ t)), where "& &" "| is a logical operation symbol," & "represents" and "" | "represents" or ". The time margins t of different program loaded PWMs are different, and actual simulation confirmation is required, which is not limited in this embodiment.
It should be noted that, in other embodiments, there may be a plurality of PWMy lagging the PWM1 by different phase angles, and there may be a plurality of phase offsets P, 1< P < PRD-t, and at this time, it is only necessary to satisfy that the value of the carrier counter in which at least one PWM exists is greater than the sum of the phase offset Pmax corresponding to the PWM with the largest phase offset and the time margin t, that is, the value of the carrier counter in which at least one PWM exists is greater than the sum of any phase offset P and the time margin t, that is, the value of the carrier counter in which at least one PWM exists is greater than a preset value.
It can be seen that, in this example, whether the time node is outside the target time period is determined by determining a relationship between a value of the carrier counter and a preset value when the period value needs to be updated, and if the time node is outside the target time period, the period value is updated, so as to avoid abnormal wave generation and protect the related power devices.
Referring to fig. 6, in accordance with the above-mentioned embodiments, fig. 6 is a block diagram illustrating functional units of a jitter cycle control apparatus according to an embodiment of the present application, where the jitter cycle control apparatus 600 includes: an obtaining unit 601, configured to obtain a period value PRD of the multi-channel PWM control circuit; a first determining unit 602, configured to determine whether the period value PRD needs to be updated; a second determining unit 603, configured to determine whether there is at least one carrier counter of the PWM having a value greater than a preset value when the period value PRD needs to be updated, the preset value is used for indicating a target time interval, the target time interval is a union of a plurality of sub-time intervals corresponding to a plurality of zero-counting time nodes, the plurality of zero-counting time nodes correspond to a plurality of paths of PWM control circuits for performing PWM control on the plurality of primary side control switch tubes one by one, the zero-counting time node is a time node corresponding to the position of a counting 0 point of a carrier counter in the process of outputting a PWM signal by each path of PWM control circuit, and the time starting point of the target time interval is a first zero-counting time node of a first PWM control circuit PWM1 in the multi-path PWM control circuit, any zero-counting time node except the first zero-counting time node in the plurality of zero-counting time nodes and the first zero-counting time node do not have other zero-counting time nodes of the local path; an updating unit 604, configured to update the period value PRD when there is at least one PWM carrier counter whose value is greater than a preset value, where the PWM carrier counter whose value is greater than the preset value is used to indicate that the current time node is already at any time node outside the target time period.
In one possible example, the obtaining unit 601 is specifically configured to: obtaining the first PWM control circuit PWM1, the PWMx with the same phase as the PWM1 and the PWMy with the lagging PWM1 alpha degree phase, wherein the phase offset of the PWMy relative to the PWM1 is P, wherein P = (alpha/360) × 2 × PRD, 1< P < PRD-t, and t is the time margin required for loading the PWM cycle PRD.
In one possible example, the jitter frequency period control means 600 is further configured to: after the period value PRD of the multi-channel Pulse Width Modulation (PWM) control circuit is obtained, the PWM control circuit is enabled, the carrier counter of the PWM1 starts counting from 0, the upper limit of the counting is the period value PRD, and the counting direction is changed when the counting value of the carrier counter of the PWM1 is the period value PRD, namely, the counting is carried out from the period value PRD to 0; when the count value of the carrier counter of the PWM1 is 0, the PWM1 sends a synchronization signal; when the PWMx receives the synchronization signal, the carrier counter of the PWMx has a value of 0, and the count direction is the same as the count direction of the carrier counter of the PWM1, i.e., the count direction is from 0 to the period value PRD, and when the count value of the carrier counter of the PWMx is 0, the count direction is changed, i.e., the count direction is from the period value PRD to 0; when the PWMy receives the synchronization signal, the carrier counter of the PWMy takes the value of the phase offset P, and the count direction is opposite to the count direction of the carrier counter of the PWM1, i.e. counting from P to 0, and when the count value of the carrier counter of the PWMy is 0, the count direction is changed, i.e. counting from 0 to the period value PRD.
In one possible example, the jitter frequency period control means 600 is further configured to: and controlling the PWMn to send a PWM signal according to a preset signal, wherein n is a positive integer. The PWMn is divided into PWMnA and PWMnB, the PWMnA controls a first level switch of a first primary side control switch tube, the PWMnB controls a second level switch of a second primary side control switch tube, and the level switches comprise: the first primary side control switch tube is set to be at a high level when the count value of the PWMn carrier counter is a first comparison value, and is set to be at a low level when the count value of the PWMn carrier counter is a second comparison value; the second primary side control switch tube is set to be at a high level when the count value of the PWMn carrier counter is a third comparison value, and is set to be at a low level when the count value of the PWMn carrier counter is a fourth comparison value; and the PWMn transmits the PWM signal by controlling the level conversion of the primary side control switching tube.
In one possible example, the jitter frequency period control means 600 is further configured to: before the period value PRD is judged to need updating, acquiring program running time, wherein the program starts to run when the PWM control circuit is enabled; and when the program running time reaches the preset time, the program is suspended from running.
In a possible example, in the aspect that, if the period value PRD needs to be updated, it is determined whether the value of at least one carrier counter of the PWM is greater than a preset value, the second determining unit 603 is specifically configured to: and judging whether the value of at least one carrier counter of the PWM is larger than the sum of the phase offset Pmax corresponding to the PWM with the maximum phase offset in the PWM and the time margin t required for loading the PWM period value PRD.
It can be understood that, since the method embodiment and the apparatus embodiment are different presentation forms of the same technical concept, the content of the method embodiment portion in the present application should be synchronously adapted to the apparatus embodiment portion, and is not described herein again.
Fig. 7 is a block diagram of an electronic device according to an embodiment of the present disclosure. As shown in fig. 7, electronic device 700 may include one or more of the following components: a processor 701, a memory 702 coupled to the processor 701, wherein the memory 702 may store one or more computer programs that may be configured to implement the methods described in the embodiments above when executed by the one or more processors 701.
Processor 701 may include one or more processing cores. The processor 701 interfaces with various components throughout the electronic device 700 using various interfaces and circuitry to perform various functions of the electronic device 700 and process data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 702 and invoking data stored in the memory 702. Alternatively, the processor 701 may be implemented in hardware using at least one of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 701 may integrate one or a combination of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing display content; the modem is used to handle wireless communications. It is understood that the modem may not be integrated into the processor 701, but may be implemented by a communication chip.
The Memory 702 may include a Random Access Memory (RAM) or a Read-Only Memory (ROM). The memory 702 may be used to store instructions, programs, code, sets of codes, or sets of instructions. The memory 702 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described above, and the like. The storage data area may also store data created during use by the electronic device 700, and the like.
It is understood that the electronic device 700 may include more or less structural elements than those shown in the above structural block diagrams, for example, a power module, a physical button, a WiFi (Wireless Fidelity) module, a speaker, a bluetooth module, a sensor, etc., and is not limited herein.
The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. The procedures or functions according to the embodiments of the present application are wholly or partially generated when the computer instructions or the computer program are loaded or executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire or wirelessly. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more collections of available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. The semiconductor medium may be a solid state disk.
Embodiments of the present application also provide a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program enables a computer to execute part or all of the steps of any one of the methods as described in the above method embodiments.
Embodiments of the present application also provide a computer program product comprising a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods as described in the above method embodiments.
It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
In the several embodiments provided in the present application, it should be understood that the disclosed method, apparatus and system may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative; for example, the division of the unit is only a logic function division, and there may be another division manner in actual implementation; for example, various elements or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be physically included alone, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute some steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: u disk, removable hard disk, magnetic disk, optical disk, volatile memory or non-volatile memory. The non-volatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. Volatile memory can be Random Access Memory (RAM), which acts as external cache memory. By way of example, but not limitation, many forms of Random Access Memory (RAM) are available, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (ddr data rate SDRAM), Enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct bus RAM (DRRAM). And the like, which may store program code.
Although the present application is disclosed above, the present application is not limited thereto. Various changes and modifications can be easily made by those skilled in the art without departing from the spirit and scope of the present application, and it is intended to cover various combinations of functions, implementation steps, software and hardware, which are described above, and embodiments of the present application.

Claims (10)

1. A frequency jittering period control method is characterized by being applied to a switching power supply circuit, wherein the switching power supply circuit comprises a controller, a plurality of paths of Pulse Width Modulation (PWM) control circuits and a plurality of primary side control switching tubes, the controller is connected with the plurality of paths of Pulse Width Modulation (PWM) control circuits, the plurality of paths of Pulse Width Modulation (PWM) control circuits are connected with the plurality of primary side control switching tubes, and the method comprises the following steps:
obtaining the period value PRD of the multi-channel pulse width modulation PWM control circuit;
judging whether the period value PRD needs to be updated or not;
if the period value PRD needs to be updated, judging whether the value of at least one PWM carrier counter is larger than a preset value, the preset value is used for indicating a target time interval, the target time interval is a union of a plurality of sub-time intervals corresponding to a plurality of zero-counting time nodes, the plurality of zero-counting time nodes correspond to a plurality of paths of PWM control circuits for performing PWM control on the plurality of primary side control switch tubes one by one, the zero-counting time node is a time node corresponding to the position of a counting 0 point of a carrier counter in the process of outputting a PWM signal by each path of PWM control circuit, and the time starting point of the target time interval is a first zero-counting time node of a first PWM control circuit PWM1 in the multi-path PWM control circuit, any zero-counting time node except the first zero-counting time node in the plurality of zero-counting time nodes and the first zero-counting time node do not have other zero-counting time nodes of the local path;
and if the value of at least one PWM carrier counter is greater than a preset value, updating the period value PRD, wherein the value of the PWM carrier counter is greater than the preset value and is used for indicating that the current time node is in any time node outside the target time period.
2. The method of claim 1, wherein the multi-channel PWM control circuit comprises the first PWM control circuit PWM1, a PWMx in phase with PWM1, and a PWMy lagging in phase with PWM1a degrees, the phase offset of the PWMy from the PWM1 is P, wherein P = (a/360) × 2 PRD, 1< P < PRD-t, t is a time margin required to load the PWM cycle PRD.
3. The method according to claim 2, wherein after said obtaining the period value PRD of the multi-channel PWM control circuit, the method further comprises:
enabling the PWM control circuit, wherein the carrier counter of the PWM1 starts counting from 0, the upper limit of the counting is the period value PRD, and when the counting value of the carrier counter of the PWM1 is the period value PRD, the counting direction is changed, namely, the counting is carried out from the period value PRD to 0;
when the count value of the carrier counter of the PWM1 is 0, the PWM1 sends a synchronization signal;
when the PWMx receives the synchronization signal, the carrier counter of the PWMx has a value of 0, and the count direction is the same as the count direction of the carrier counter of the PWM1, i.e., the count direction is from 0 to the period value PRD, and when the count value of the carrier counter of the PWMx is 0, the count direction is changed, i.e., the count direction is from the period value PRD to 0;
when the PWMy receives the synchronization signal, the carrier counter of the PWMy takes the value of the phase offset P, and the count direction is opposite to the count direction of the carrier counter of the PWM1, i.e. counting from P to 0, and when the count value of the carrier counter of the PWMy is 0, the count direction is changed, i.e. counting from 0 to the period value PRD.
4. The method of claim 3, further comprising:
after the PWM control circuit is enabled, PWMn sends PWM signals according to a preset signal sending mode, and n is a positive integer.
5. The method of claim 4, wherein said PWMn sending PWM signals in a preset signaling scheme after said enabling of said PWM control circuit, n being a positive integer, comprises:
the PWMn is divided into PWMnA and PWMnB, the PWMnA controls a first level switch of a first primary side control switch tube, the PWMnB controls a second level switch of a second primary side control switch tube, and the level switches comprise:
the first primary side control switch tube is set to be at a high level when the count value of the PWMn carrier counter is a first comparison value, and is set to be at a low level when the count value of the PWMn carrier counter is a second comparison value;
the second primary side control switch tube is set to be at a high level when the count value of the PWMn carrier counter is a third comparison value, and is set to be at a low level when the count value of the PWMn carrier counter is a fourth comparison value;
and the PWMn transmits the PWM signal by controlling the level conversion of the primary side control switching tube.
6. The method according to claim 3, wherein before said determining whether the period value PRD needs to be updated, the method further comprises:
acquiring program running time, wherein the program starts to run when the PWM control circuit is enabled;
and when the program running time reaches the preset time, the program is suspended from running.
7. The method of claim 2, wherein the determining whether the value of at least one carrier counter of the PWM is greater than a predetermined value if the period value PRD needs to be updated comprises:
the preset value is the sum of a phase offset Pmax corresponding to the PWM with the maximum phase offset in the PWM and a time margin t required for loading the PWM period value PRD.
8. An apparatus for controlling a dithering cycle, the apparatus comprising:
the acquisition unit is used for acquiring the period value PRD of the multi-channel pulse width modulation PWM control circuit;
a first judging unit, configured to judge whether the period value PRD needs to be updated;
a second determining unit, configured to determine whether there is at least one carrier counter of the PWM having a value greater than a preset value when the period value PRD needs to be updated, the preset value is used for indicating a target time interval, the target time interval is a union of a plurality of sub-time intervals corresponding to a plurality of zero-counting time nodes, the plurality of zero-counting time nodes correspond to a plurality of paths of PWM control circuits for performing PWM control on the plurality of primary side control switch tubes one by one, the zero-counting time node is a time node corresponding to the position of a counting 0 point of a carrier counter in the process of outputting a PWM signal by each path of PWM control circuit, and the time starting point of the target time interval is a first zero-counting time node of a first PWM control circuit PWM1 in the multi-path PWM control circuit, any zero-counting time node except the first zero-counting time node in the plurality of zero-counting time nodes and the first zero-counting time node do not have other zero-counting time nodes of the local path;
and the updating unit is used for updating the period value PRD when the value of at least one PWM carrier counter is larger than a preset value, wherein the value of the PWM carrier counter is larger than the preset value and is used for indicating that the current time node is positioned at any time node outside the target time period.
9. An electronic device comprising a processor, a memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing the steps in the method of any of claims 1-7.
10. A computer-readable storage medium, characterized in that a computer program for electronic data exchange is stored, wherein the computer program causes a computer to perform the method according to any one of claims 1-7.
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CN111030649A (en) * 2019-12-27 2020-04-17 上海东软载波微电子有限公司 Random jitter frequency circuit, control method, control device and medium thereof
CN111600464A (en) * 2020-06-30 2020-08-28 上海晶丰明源半导体股份有限公司 Multi-phase power supply dynamic response control circuit and control method

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