CN114007347A - Preparation method of packaging substrate circuit - Google Patents
Preparation method of packaging substrate circuit Download PDFInfo
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- CN114007347A CN114007347A CN202111281206.2A CN202111281206A CN114007347A CN 114007347 A CN114007347 A CN 114007347A CN 202111281206 A CN202111281206 A CN 202111281206A CN 114007347 A CN114007347 A CN 114007347A
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- dielectric layer
- circuit
- opening
- copper
- layer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
Abstract
The invention discloses a preparation method of a packaging substrate circuit, which comprises the following steps: providing a circuit board, wherein the surface of the circuit board is provided with a conductive copper layer; forming a first dielectric layer on the surface of the conductive copper layer, and forming a first opening in the first dielectric layer; forming a conductive circuit in the first opening by chemical deposition; removing the first dielectric layer and the conductive copper layer covered by the first dielectric layer to form a circuit covered on the surface of the circuit board; forming a second dielectric layer on the surface of the circuit board; forming a third dielectric layer on the surface of the second dielectric layer, and forming a second opening and a third opening in the third dielectric layer at intervals; and forming a metallization circuit layer in the second opening and the third opening. The method increases the bonding area of the multi-layer metal plating circuit layer and the first dielectric layer by increasing the formation of multi-layer metal plating in the first dielectric layer in a chemical deposition mode to form the multi-layer metal plating circuit layer, so that the bonding force between the second dielectric layer and the circuit structure is better, and the uniformity of the thickness of the circuit structure is better.
Description
Technical Field
The invention relates to the technical field of PCB (printed circuit board), in particular to a preparation method of a packaging substrate circuit.
Background
With the continuous development of finer circuit precision of circuit board lines, the lines formed on the circuit board are thinner, and the gaps between the lines are narrower, so that when the circuit layer is added on the circuit layer subsequently, the gaps between the lines are not easily filled up by the dielectric layer, and bubbles are easily left in the gaps, which seriously affects the reliability of the formed circuit board. And because the line width of the thin line is thinner, the area of the combination of the bottom and the dielectric layer is smaller, and the problem of poor combination exists. And because the conducting layer is used as a current conducting path during electroplating, the current density flowing through different parts of the conducting layer is different, so that the thickness of a circuit layer formed by electroplating metal on the conducting layer is uneven, the smoothness of the surface of the circuit layer is influenced, and the electrical quality is further influenced.
Disclosure of Invention
In order to overcome the defects in the prior art, embodiments of the present invention provide a method for manufacturing a circuit of a package substrate, which is used to solve at least one of the above problems.
The embodiment of the application discloses a preparation method of a packaging substrate circuit, which increases the bonding force between a second dielectric layer and a circuit structure by increasing the formation of multi-layer metallization in a chemical deposition mode in the first dielectric layer to form a multi-layer metallization circuit layer and increasing the bonding area between the multi-layer metallization circuit layer and the first dielectric layer; and the defect that the dielectric layer is not easy to fill in the gap of the circuit and bubbles remain in the circuit board is avoided. In addition, this application adopts the chemical deposition mode to form the line structure, compares in prior art and enables the homogeneity of line structure thickness better so that form thinner circuit.
The preparation method of the packaging substrate circuit comprises the following steps:
providing a circuit board, wherein a conductive copper layer is arranged on the surface of the circuit board;
forming a first dielectric layer on the surface of the conductive copper layer, and forming a first opening in the first dielectric layer to expose a part of the surface of the conductive copper layer;
forming a conductive circuit in the first opening in a chemical deposition mode;
removing the first dielectric layer and the conductive copper layer covered by the first dielectric layer to form a circuit covered on the surface of the circuit board;
forming a second dielectric layer on the surface of the circuit board;
forming a third dielectric layer on the surface of the second dielectric layer, and forming a second opening and a third opening in the third dielectric layer at intervals;
and forming a metallization circuit layer in the second opening and the third opening.
Further, in the step of removing the first dielectric layer and the conductive copper layer covered thereby to form a circuit covered on the surface of the circuit board, the first dielectric layer and the conductive copper layer covered thereby are removed by chemical cleaning.
Further, after the step of forming the second dielectric layer on the surface of the circuit board, the method comprises the following steps:
forming a fourth opening in the second dielectric layer to expose a part of the surface of the circuit;
and forming a conductive blind hole in the fourth opening in a chemical deposition mode.
Further, after the step of forming the second dielectric layer on the surface of the circuit board, the method comprises the following steps:
forming a fourth opening in the second dielectric layer to expose a part of the surface of the circuit;
and forming a third dielectric layer on the second dielectric layer and the exposed part of the surface of the circuit.
Further, after the step of forming the second dielectric layer on the surface of the circuit board, the method comprises the following steps:
and forming a third dielectric layer on the surface of the second dielectric layer.
After the step of forming a third dielectric layer on the surface of the second dielectric layer and forming a second opening and a third opening at an interval in the third dielectric layer, the method further comprises the following steps of:
forming a fourth opening in the second dielectric layer in the second opening to expose the circuit layer;
and forming a conductive blind hole in the fourth opening.
Further, the conductive line is made of one of three layers of metal of copper (Cu) \ nickel (Ni) \ copper (Cu), four layers of metal of copper (Cu) \ nickel (Ni) \ gold (Au) \ copper (Cu), and five layers of metal of copper (Cu) \ nickel (Ni) \ palladium (Pd) \ gold (Au) \ copper (Cu), and the conductive blind via is made of one of three layers of metal of copper (Cu) \\ nickel (Ni) \ copper (Cu), four layers of metal of copper (Cu) \\ nickel (Ni) \ gold (Au) \\ copper (Cu), and five layers of metal of copper (Cu) \\ nickel (Ni) \ palladium (Pd) \ gold (Au) \ copper (Cu).
Further, the first opening, the second opening and the third opening can be formed by laser drilling or exposure development.
Furthermore, the first dielectric layer, the second dielectric layer and the third dielectric layer can be made of photosensitive or non-photosensitive materials.
Furthermore, the metallization circuit layer is formed by chemical deposition, and the material of the metallization circuit layer is one of three layers of metal of copper (Cu) \ nickel (Ni) \ copper (Cu), four layers of metal of copper (Cu)/nickel (Ni) \ gold (Au) \ copper (Cu), and five layers of metal of copper (Cu) \ nickel (Ni) \ palladium (Pd) \ gold (Au) \ copper (Cu).
The invention has the following beneficial effects:
the preparation method increases the adhesion area of the multilayer metallization circuit layer and the first dielectric layer by increasing the formation of the multilayer metallization in the first dielectric layer in a chemical deposition mode so as to form the multilayer metallization circuit layer, so that the bonding force between the second dielectric layer and the circuit structure is better compared with the prior art in which the multilayer metallization is formed in the second dielectric layer only in a chemical deposition mode; and the defect that the dielectric layer is not easy to fill in the gap of the circuit and bubbles remain in the circuit board is avoided. In addition, this application adopts the chemical deposition mode to form the line structure, compares in prior art and enables the homogeneity of line structure thickness better so that form thinner circuit.
In order to make the aforementioned and other objects, features and advantages of the invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIGS. 1A to 1H are process diagrams for the preparation of example 1 of the present invention;
FIGS. 2A to 2D are partial preparation process diagrams of example 2 of the present invention;
fig. 3A to 3D are partial preparation process diagrams of example 3 of the present invention.
Reference numerals of the above figures: 10. a circuit board; 11. a conductive copper layer; 12. a first dielectric layer; 120. a first opening; 13. A conductive circuit; 14. a line; 15. a second dielectric layer; 150. a fourth opening; 16. a conductive blind hole; 17. a third dielectric layer; 170. a second opening; 171. a third opening; 18. and metallizing the metal circuit layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature.
According to the preparation method of the packaging substrate circuit, the multilayer metallization formed in the first dielectric layer in a chemical deposition mode is added to form the multilayer metallization circuit layer, the adhesion area of the multilayer metallization circuit layer and the first dielectric layer is increased, and compared with the prior art that the multilayer metallization is formed in the second dielectric layer only in a chemical deposition mode, the bonding force between the second dielectric layer and the circuit structure is better; and the defect that the dielectric layer is not easy to fill in the gap of the circuit and bubbles remain in the circuit board is avoided. In addition, this application adopts the chemical deposition mode to form the line structure, compares in prior art and enables the homogeneity of line structure thickness better so that form thinner circuit.
The present invention will be described in detail below with reference to the accompanying drawings and examples.
The preparation method of the circuit of the package substrate in the embodiment includes the following steps:
providing a circuit board, wherein a conductive copper layer is arranged on the surface of the circuit board;
forming a first dielectric layer on the surface of the conductive copper layer, and forming a first opening in the first dielectric layer to expose a part of the surface of the conductive copper layer;
forming a conductive circuit in the first opening in a chemical deposition mode;
removing the first dielectric layer and the conductive copper layer covered by the first dielectric layer to form a circuit covered on the surface of the circuit board;
forming a second dielectric layer on the surface of the circuit board;
forming a third dielectric layer on the surface of the second dielectric layer, and forming a second opening and a third opening in the third dielectric layer at intervals;
and forming a metallization circuit layer in the second opening and the third opening.
Example 1:
with reference to fig. 1A to fig. 1H, the method for manufacturing a circuit of a package substrate includes the following steps:
first, a worker provides a circuit board. And a conductive copper layer is arranged on the surface of the circuit board.
And secondly, forming a first dielectric layer on the surface of the conductive copper layer. The first dielectric layer may be made of a photosensitive or non-photosensitive material, and specifically may be made of ABF (Ajinomotobuild-up film), Epoxy resin (Epoxy resin), polyacetamide (Polyimide), cyanoester (Cyanate Ester), glass fiber, Bismaleimide/Triazine (BT), or FR5 material formed by mixing Epoxy resin and glass fiber. And forming a first opening in the first dielectric layer to expose a part of the surface of the conductive copper layer. The first opening is formed by laser drilling or exposure development.
Then, a conductive circuit is formed in the first opening by chemical deposition. The material of the conductive circuit is one of three layers of metal of copper (Cu) \\ nickel (Ni) \ copper (Cu), four layers of metal of copper (Cu) \ nickel (Ni) \ gold (Au) \ copper (Cu), and five layers of metal of copper (Cu) \ nickel (Ni) \ palladium (Pd) \ gold (Au) \ copper (Cu).
And secondly, removing the first dielectric layer and the conductive copper layer covered by the first dielectric layer in a chemical cleaning mode, and only retaining the conductive circuit and the conductive copper layer in contact with the conductive circuit, thereby forming a circuit covered on the surface of the circuit board.
Then, a second dielectric layer is formed on the surface of the circuit board. And opening a fourth opening in the second dielectric layer to expose a portion of the surface of the circuit. The fourth opening is formed by laser drilling or exposure and development. And forming a conductive blind hole in the fourth opening by chemical deposition.
And then, forming a third dielectric layer on the surface of the second dielectric layer. And a second opening and a third opening are formed in the third dielectric layer at an interval. The second opening corresponds to the first opening so as to expose the upper surface of the conductive blind hole. The second opening and the third opening are formed by laser drilling or exposure development.
And finally, forming a plated metal circuit layer in the second opening and the third opening, so that the multilayered plated metal circuit layer is electrically connected with the conductive blind hole and further electrically connected with the circuit layer of the circuit board, and the multilayered plated metal circuit layer is electrically connected with the circuit layer of the additional circuit board through the conductive blind hole.
Example 2:
with reference to fig. 1A to 1D and fig. 2A to 2D, the method for manufacturing a circuit of a package substrate includes the following steps:
first, a worker provides a circuit board. And a conductive copper layer is arranged on the surface of the circuit board.
And secondly, forming a first dielectric layer on the surface of the conductive copper layer. The first dielectric layer may be made of a photosensitive or non-photosensitive material, and specifically may be made of ABF (Ajinomotobuild-up film), Epoxy resin (Epoxy resin), polyacetamide (Polyimide), cyanoester (Cyanate Ester), glass fiber, Bismaleimide/Triazine (BT), or FR5 material formed by mixing Epoxy resin and glass fiber. And forming a first opening in the first dielectric layer to expose a part of the surface of the conductive copper layer. The first opening is formed by laser drilling or exposure development.
Then, a conductive circuit is formed in the first opening by chemical deposition. The material of the conductive circuit is one of three layers of metal of copper (Cu) \\ nickel (Ni) \ copper (Cu), four layers of metal of copper (Cu) \ nickel (Ni) \ gold (Au) \ copper (Cu), and five layers of metal of copper (Cu) \ nickel (Ni) \ palladium (Pd) \ gold (Au) \ copper (Cu).
And secondly, removing the first dielectric layer and the conductive copper layer covered by the first dielectric layer in a chemical cleaning mode, and only retaining the conductive circuit and the conductive copper layer in contact with the conductive circuit, thereby forming a circuit covered on the surface of the circuit board.
Then, a second dielectric layer is formed on the surface of the circuit board. And forming a fourth opening in the second dielectric layer to expose a part of the surface of the circuit. The fourth opening is formed through laser drilling or exposure development. And forming a third dielectric layer on the second dielectric layer and the exposed part of the surface of the circuit.
And then, forming a third dielectric layer on the surface of the second dielectric layer. And a second opening and a third opening are formed in the third dielectric layer at an interval. The second opening corresponds to the fourth opening to expose the upper surface of the conductive blind hole. The second opening and the third opening are formed through laser drilling or exposure development.
Finally, a metallization circuit layer is formed in the second opening and the third opening. And forming a conductive blind hole in the fourth opening to electrically connect the circuit layer, so that the multilayered metal-plated circuit layer is electrically connected with the circuit layer of the additional circuit board through the conductive blind hole.
Example 3:
with reference to fig. 1A to 1D and fig. 3A to 3D, the method for manufacturing a circuit of a package substrate includes the following steps:
first, a worker provides a circuit board. And a conductive copper layer is arranged on the surface of the circuit board.
And secondly, forming a first dielectric layer on the surface of the conductive copper layer. The first dielectric layer may be made of a photosensitive or non-photosensitive material, and specifically may be made of ABF (Ajinomotobuild-up film), Epoxy resin (Epoxy resin), polyacetamide (Polyimide), cyanoester (Cyanate Ester), glass fiber, Bismaleimide/Triazine (BT), or FR5 material formed by mixing Epoxy resin and glass fiber. And forming a first opening in the first dielectric layer to expose a part of the surface of the conductive copper layer. The first opening is formed by laser drilling or exposure development.
Then, a conductive circuit is formed in the first opening by chemical deposition. The material of the conductive circuit is one of three layers of metal of copper (Cu) \\ nickel (Ni) \ copper (Cu), four layers of metal of copper (Cu) \ nickel (Ni) \ gold (Au) \ copper (Cu), and five layers of metal of copper (Cu) \ nickel (Ni) \ palladium (Pd) \ gold (Au) \ copper (Cu).
And secondly, removing the first dielectric layer and the conductive copper layer covered by the first dielectric layer in a chemical cleaning mode, and only retaining the conductive circuit and the conductive copper layer in contact with the conductive circuit, thereby forming a circuit covered on the surface of the circuit board.
Then, a second dielectric layer is formed on the surface of the circuit board. And forming a third dielectric layer on the surface of the second dielectric layer. And a second opening and a third opening are formed in the third dielectric layer at an interval. And forming a fourth opening in the second dielectric layer in the second opening to expose the circuit layer. The second opening, the third opening and the fourth opening are formed in a laser drilling or exposure developing mode.
And finally, forming a conductive blind hole in the fourth opening in a chemical deposition mode so as to be electrically connected with the circuit layer. And forming a metallized circuit layer in the second opening and the third opening so that the multilayered metallized circuit layer is electrically connected with the circuit layer of the additional circuit board through the conductive blind hole.
Specifically, in this embodiment, the material of the conductive line is one of three layers of metal of copper (Cu) \ nickel (Ni) \ copper (Cu), four layers of metal of copper (Cu) \ nickel (Ni) \ gold (Au) \ copper (Cu), and five layers of metal of copper (Cu) \ nickel (Ni) \ palladium (Pd) \ gold (Au) \ copper (Cu).
In a preferred embodiment, the material of the conductive via is one of three layers of metal of copper (Cu) \ nickel (Ni) \ copper (Cu), four layers of metal of copper (Cu) \ nickel (Ni) \ gold (Au) \ copper (Cu), and five layers of metal of copper (Cu) \ nickel (Ni) \ palladium (Pd) \ gold (Au) \ copper (Cu).
Specifically, in this embodiment, the first opening, the second opening, and the third opening are formed by laser drilling or exposure and development.
Specifically, in the present embodiment, the first dielectric layer, the second dielectric layer and the third dielectric layer may be made of photosensitive or non-photosensitive materials.
Specifically, in this embodiment, the metallization circuit layer is formed by chemical deposition, and the material of the metallization circuit layer is one of three layers of metal, copper (Cu)/nickel (Ni) \ copper (Cu), four layers of metal, and five layers of metal, copper (Cu) \ nickel (Ni) \ palladium (Pd) \ gold (Au) \ copper (Cu).
The preparation method increases the adhesion area of the multilayer metallization circuit layer and the first dielectric layer by increasing the formation of the multilayer metallization in the first dielectric layer in a chemical deposition mode so as to form the multilayer metallization circuit layer, so that the bonding force between the second dielectric layer and the circuit structure is better compared with the prior art in which the multilayer metallization is formed in the second dielectric layer only in a chemical deposition mode; and the defect that the dielectric layer is not easy to fill in the gap of the circuit and bubbles remain in the circuit board is avoided. In addition, this application adopts the chemical deposition mode to form the line structure, compares in prior art and enables the homogeneity of line structure thickness better so that form thinner circuit.
The principle and the implementation mode of the invention are explained by applying specific embodiments in the invention, and the description of the embodiments is only used for helping to understand the technical scheme and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A preparation method of a packaging substrate circuit is characterized by comprising the following steps:
providing a circuit board, wherein a conductive copper layer is arranged on the surface of the circuit board;
forming a first dielectric layer on the surface of the conductive copper layer, and forming a first opening in the first dielectric layer to expose a part of the surface of the conductive copper layer;
forming a conductive circuit in the first opening in a chemical deposition mode;
removing the first dielectric layer and the conductive copper layer covered by the first dielectric layer to form a circuit covered on the surface of the circuit board;
forming a second dielectric layer on the surface of the circuit board;
forming a third dielectric layer on the surface of the second dielectric layer, and forming a second opening and a third opening in the third dielectric layer at intervals;
and forming a metallization circuit layer in the second opening and the third opening.
2. The method for manufacturing the circuit of the package substrate as claimed in claim 1, wherein in the step of removing the first dielectric layer and the conductive copper layer covered thereby to form the circuit covered on the surface of the circuit board, the first dielectric layer and the conductive copper layer covered thereby are removed by chemical cleaning.
3. The method for manufacturing the circuit of the package substrate as claimed in claim 1, wherein the method comprises the following steps after the step of forming the second dielectric layer on the surface of the circuit board:
forming a fourth opening in the second dielectric layer to expose a part of the surface of the circuit;
and forming a conductive blind hole in the fourth opening in a chemical deposition mode.
4. The method for manufacturing the circuit of the package substrate as claimed in claim 1, wherein the method comprises the following steps after the step of forming the second dielectric layer on the surface of the circuit board:
forming a fourth opening in the second dielectric layer to expose a part of the surface of the circuit;
and forming a third dielectric layer on the second dielectric layer and the exposed part of the surface of the circuit.
5. The method for manufacturing the circuit of the package substrate as claimed in claim 1, wherein the method comprises the following steps after the step of forming the second dielectric layer on the surface of the circuit board:
and forming a third dielectric layer on the surface of the second dielectric layer.
6. The method for manufacturing a circuit on a package substrate according to claim 5, wherein after the step of forming a third dielectric layer on the surface of the second dielectric layer and forming a second opening and a third opening at an interval in the third dielectric layer, the method further comprises the steps of:
forming a fourth opening in the second dielectric layer in the second opening to expose the circuit layer;
and forming a conductive blind hole in the fourth opening.
7. The method of claim 6, wherein the conductive trace is made of one of three layers of copper (Cu) \ nickel (Ni) \ copper (Cu) and five layers of copper (Cu) \ nickel (Ni) \ gold (Au) \ copper (Cu), and the conductive blind via is made of one of three layers of copper (Cu) \ nickel (Ni) \ palladium (Pd) \ gold (Au) \ copper (Cu), four layers of copper (Cu) \\ nickel (Ni) \ copper (Cu) and five layers of copper (Cu) \ nickel (Ni) \\ gold (Au) \ copper (Cu) and five layers of copper (Cu) \\ nickel (Pd) \ gold (Au) \ gold (Cu).
8. The method of claim 1, wherein the first opening, the second opening and the third opening are formed by laser drilling or exposure development.
9. The method as claimed in claim 1, wherein the first, second and third dielectric layers are made of photosensitive or non-photosensitive materials.
10. The method for manufacturing the package substrate circuit according to claim 1, wherein the metallization layer is formed by chemical deposition, and the material of the metallization layer is one of three layers of copper (Cu) \ nickel (Ni) \ copper (Cu), four layers of copper (Cu)/nickel (Ni) \ gold (Au) \ copper (Cu), and five layers of copper (Cu) \ nickel (Ni) \ palladium (Pd) \ gold (Au) \ copper (Cu).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111281206.2A CN114007347A (en) | 2021-11-01 | 2021-11-01 | Preparation method of packaging substrate circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111281206.2A CN114007347A (en) | 2021-11-01 | 2021-11-01 | Preparation method of packaging substrate circuit |
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| CN114007347A true CN114007347A (en) | 2022-02-01 |
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| CN202111281206.2A Pending CN114007347A (en) | 2021-11-01 | 2021-11-01 | Preparation method of packaging substrate circuit |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW592010B (en) * | 2003-09-29 | 2004-06-11 | Phoenix Prec Technology Corp | Method for fabricating patterned fine pitch circuit layer of semiconductor package substrate |
| US20090071704A1 (en) * | 2007-09-19 | 2009-03-19 | Phoenix Precision Technology Corporation | Circuit board and method for fabricating the same |
| CN102056398A (en) * | 2009-11-06 | 2011-05-11 | 欣兴电子股份有限公司 | Circuit board structure and making method thereof |
-
2021
- 2021-11-01 CN CN202111281206.2A patent/CN114007347A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW592010B (en) * | 2003-09-29 | 2004-06-11 | Phoenix Prec Technology Corp | Method for fabricating patterned fine pitch circuit layer of semiconductor package substrate |
| US20090071704A1 (en) * | 2007-09-19 | 2009-03-19 | Phoenix Precision Technology Corporation | Circuit board and method for fabricating the same |
| CN102056398A (en) * | 2009-11-06 | 2011-05-11 | 欣兴电子股份有限公司 | Circuit board structure and making method thereof |
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