CN114005831B - Process integration method for improving electric leakage between NAND flash word lines - Google Patents
Process integration method for improving electric leakage between NAND flash word lines Download PDFInfo
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- CN114005831B CN114005831B CN202111265240.0A CN202111265240A CN114005831B CN 114005831 B CN114005831 B CN 114005831B CN 202111265240 A CN202111265240 A CN 202111265240A CN 114005831 B CN114005831 B CN 114005831B
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- 238000000034 method Methods 0.000 title claims abstract description 63
- 230000010354 integration Effects 0.000 title claims abstract description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 41
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 38
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 23
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 claims abstract description 21
- 238000000137 annealing Methods 0.000 claims abstract description 13
- PCLURTMBFDTLSK-UHFFFAOYSA-N nickel platinum Chemical compound [Ni].[Pt] PCLURTMBFDTLSK-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000004140 cleaning Methods 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000000126 substance Substances 0.000 claims abstract description 7
- 238000005498 polishing Methods 0.000 claims abstract description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 229910005883 NiSi Inorganic materials 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 2
- 230000009977 dual effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 14
- 238000007667 floating Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910018098 Ni-Si Inorganic materials 0.000 description 1
- 229910018529 Ni—Si Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- -1 titanium nitrides Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
Abstract
A process integration method for improving leakage between NANDflash word lines comprises the following steps: providing a silicon-based substrate, and forming a block area word line and a selection tube grid; forming an oxide layer at the word line structure and the select pipe gate; filling a silicon nitride layer at the gaps of the word line structure and the select tube gate and forming a side wall; forming an oxide layer and a silicon nitride layer thereon; setting an oxide layer on the silicon nitride layer, filling gaps between the selective tube gates, and performing chemical mechanical polishing; etching back the word line structure and exposing the top area of the grid electrode by the selective tube grid; removing the silicon nitride layer between the word line structures; depositing nickel-platinum and titanium nitride, and carrying out first annealing and nickel-platinum metal silicide cleaning; depositing a dielectric layer to form an air gap; and (5) carrying out secondary annealing on the nickel silicon compound. The invention not only has strong process compatibility, but also can reduce wet cleaning and effectively reduce the possibility of collapse of the word line structure by carrying out the second annealing of the nickel silicon compound after the air gap of the word line structure is formed, thereby improving the condition of electric leakage among the word line structures.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a process integration method for improving electric leakage between NAND flash word lines.
Background
NAND flash is an important flash memory device, and because of its extremely high cell density, it can achieve a higher storage density, and at the same time, it has extremely fast writing and erasing speeds, so it is widely used in various memory cards, and is gradually replacing the solid state hard disk of the mechanical hard disk.
As device dimensions shrink, the size of the word line pitch of NAND device block areas also decreases, which can cause serious inter-cell coupling interference problems for floating gate memories, affecting the magnitude of the cell threshold voltage, programming and reading speeds of the memory array. In order to solve the problem, a process of an air gap (Airgap) isolation technology is introduced into the manufacture of NAND flash, and a substance with the lowest dielectric constant, namely air, is introduced between a floating gate electrode and a floating gate electrode, so that the capacitive coupling effect between floating gate electrodes of a word line of a device is improved.
As one skilled in the art will readily appreciate, in 1X NAND, the size of the wordline pitch of the block is reduced, and after the wordline etch process and removal of silicon nitride prior to formation of the air gap (Airgap), the aspect ratio is even greater than 10, and such high aspect ratio patterns are relatively fragile, and the wordlines can easily topple over in subsequent processes, resulting in wordline leakage.
The search for a process integration method which is simple to manufacture, has strong process compatibility and can effectively reduce the collapse of word lines has become one of the technical problems to be solved urgently by those skilled in the art.
Therefore, in order to solve the problems in the prior art, the present designer actively researches and improves the process by virtue of years of experience in the industry, and the process integration method for improving the electric leakage between NAND flash word lines is provided.
Disclosure of Invention
The invention provides a process integration method for improving the leakage among NAND flash word lines, aiming at the defects that in the prior art, the size of the word line spacing of a block area is reduced, after a word line etching process and silicon nitride removal before an air gap (Airgap) is formed, the depth-to-width ratio is even more than 10, the graph with the high depth-to-width ratio is fragile, the word line is easy to topple in the subsequent process, the leakage condition among the word lines is caused, and the like.
In order to achieve the object of the present invention, the present invention provides a process integration method for improving the leakage between NAND flash word lines, the process integration method for improving the leakage between NAND flash word lines, comprising:
step S1 is executed: providing a silicon-based substrate, and forming a block area word line and selection tube grids positioned at two sides of the block area word line on the silicon-based substrate;
step S2 is executed: forming a first oxide layer on the bottom and side walls of the word line structure and the side walls of the select pipe gate;
step S3 is executed: filling a first silicon nitride layer in gaps among the word line structures, among the word line structures and the selection tube grids and among the selection tube grids, wherein the first silicon nitride layer is positioned on the first oxide layer, and etching the first silicon nitride layer on the side wall of the selection tube grid to form a side wall;
step S4 is executed: forming a second oxide layer on one side of the block word line and the selection tube gate, which is different from the silicon-based substrate, and forming a second silicon nitride layer on one side of the second oxide layer, which is different from the silicon-based substrate;
step S5 is executed: setting a third oxide layer on the second silicon nitride layer, filling the gap of the selection tube gate by the third oxide layer, carrying out chemical mechanical polishing on the third oxide layer, and flattening the third oxide layer to the upper surface of the second silicon nitride layer;
step S6 is executed: etching the word line structure and the selection tube grid back, and exposing the top area of the grid;
step S7 is executed: removing the first silicon nitride layer between the word line structures;
step S8 is executed: depositing nickel-platinum and titanium nitride in the top area of the grid electrode, and carrying out first annealing on nickel-silicon compound and cleaning nickel-platinum metal silicide;
step S9 is performed: depositing a dielectric layer to cover the top regions of the gates of the word line structures so as to form air gaps between the word line structures;
step S10 is performed: a second anneal of the nickel silicon compound is performed to form a metal silicide in the top region of the gate of the wordline structure.
Optionally, the block word line further includes word line structures having uniformly spaced apart pitch dimensions.
Alternatively, the block word line and the select pipe gate are manufactured by a self-aligned double patterning process.
Optionally, the functional structure layers of the selection tube gate are stacked longitudinally, and include a first polysilicon layer, an ONO layer (silicon oxide layer-silicon nitride layer-silicon oxide layer), and a second polysilicon layer sequentially from bottom to top. Optionally, the first oxide layer is a silicon dioxide layer.
Optionally, a second oxide layer and the first oxide layer formed on one side of the block word line and the selection tube gate different from the silicon-based substrate are in a surrounding structure.
Optionally, the nickel silicon compound is annealed for the first time to form Ni 2 Si。
Optionally, the nickel silicon compound is annealed a second time to form NiSi.
The process integration method for improving the electric leakage between NAND flash word lines, disclosed by the invention, has the advantages that the nickel silicon compound is annealed for the second time after the air gap of the word line structure is formed, so that the process compatibility is strong, the wet cleaning is reduced, the possibility of collapse of the word line structure is effectively reduced, and the electric leakage situation between the word line structures is improved.
Drawings
FIG. 1 is a flow chart of a process integration method for improving the leakage between NAND flash word lines;
FIG. 2 is a schematic diagram of a block word line and a select transistor gate formed on a silicon-based substrate according to the present invention;
FIG. 3 is a schematic diagram of the structure of the bottom and the sidewall of the word line structure of the present invention, and the sidewall of the select transistor gate, forming a first oxide layer and a first nitride layer, and etching to form the sidewall;
FIG. 4 is a schematic diagram of a structure of the present invention after forming a second silicon nitride layer, filling a third oxide layer between select gates, and performing chemical mechanical polishing;
FIG. 5 is a schematic diagram of the structure of the top region of the gate of the select transistor with the word line structure etched back and exposed in accordance with the present invention;
FIG. 6 is a schematic diagram of the structure of the present invention for removing the first silicon nitride layer between the word line structures;
FIG. 7 is a schematic diagram showing the structure of depositing Ni-Pt and Ti nitrides on the top region of the gate electrode, and performing a first annealing of Ni-Si compound and cleaning of Ni-Pt metal silicide;
FIG. 8 is a schematic diagram of a deposited dielectric layer covering the top region of the gate of the word line structure to form an air gap in accordance with the present invention;
FIG. 9 is a schematic view showing a structure of the second annealing of the nickel silicon compound of the present invention.
Detailed Description
For a detailed description of the technical content, constructional features, achieved objects and effects of the present invention, the following detailed description will be given with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a flowchart of a process integration method for improving leakage between NAND flash word lines according to the present invention. The process integration method for improving the electric leakage between NAND flash word lines comprises the following steps:
step S1 is executed: providing a silicon substrate, and forming a block area word line and selection tube gates positioned on two sides of the block area word line on the silicon substrate. The block area word line further comprises word line structures with uniformly spaced intervals. The block word lines and the select pipe gates are fabricated by a self-aligned dual pattern process.
Step S2 is executed: a first oxide layer is formed at the bottom and sidewalls of the word line structure, and the sidewalls of the select pipe gate.
Step S3 is executed: and filling a first silicon nitride layer in gaps among the word line structures, between the word line structures and the selection tube gates and among the selection tube gates, wherein the first silicon nitride layer is positioned on the first oxide layer, and etching the first silicon nitride layer on the side wall of the selection tube gate to form a side wall.
Step S4 is executed: a second oxide layer is formed on a side of the block word line and the select pipe gate, which is different from the silicon substrate, and a second silicon nitride layer is formed on a side of the second oxide layer, which is different from the silicon substrate. Wherein, the second oxide layer and the first oxide layer formed on one side of the block word line and the selection tube grid, which is different from the silicon substrate, are in a enclosing structure.
Step S5 is executed: and setting a third oxide layer on the second silicon nitride layer, filling the gap of the selection tube gate by the third oxide layer, carrying out chemical mechanical polishing on the third oxide layer, and flattening the third oxide layer to the upper surface of the second silicon nitride layer.
Step S6 is executed: and etching back the word line structure and the selection tube gate, and exposing the top area of the gate.
Step S7 is executed: and removing the first silicon nitride layer between the word line structures.
Step S8 is executed: and depositing nickel-platinum and titanium nitride on the top area of the grid electrode, and carrying out first annealing of nickel-silicon compound and cleaning of nickel-platinum metal silicide.
Step S9 is performed: a dielectric layer is deposited overlying the gate top regions of the word line structures such that an air gap is formed between the word line structures.
Step S10 is performed: a second anneal of the nickel silicon compound is performed to form a metal silicide in the top region of the gate of the wordline structure.
In order to more intuitively disclose the technical scheme of the invention and highlight the beneficial effects of the invention, the specific steps and the staged structure of the process integration method for improving the electric leakage between NAND flash word lines are described with reference to specific embodiments. In the specific embodiments, the size, specification, film thickness, etc. of the functional structure are only listed, and should not be construed as limiting the technical scheme of the present invention.
Referring to fig. 2 in combination with fig. 1, fig. 2 is a schematic diagram illustrating a structure of forming a block word line and a select transistor gate on a silicon substrate according to the present invention. In step S1, a silicon-based substrate 1 is provided, and a block word line 2 and select gates 3 located on both sides of the block word line 2 are formed on the silicon-based substrate 1. Wherein the block word line 2 further comprises word line structures 20 with uniformly spaced pitch sizes. The block word line 2 and the select pipe gate 3 are manufactured by a self-aligned double patterning process. The functional structure layers of the selection tube gate 3 are longitudinally overlapped, and sequentially comprise a first polysilicon layer, an ONO layer (silicon oxide layer-silicon nitride layer-silicon oxide layer) and a second polysilicon layer from bottom to top.
Referring to fig. 3 in combination with fig. 1 and 2, fig. 3 is a schematic structural diagram of a bottom and a sidewall of a word line structure and a sidewall of a select gate to form a first oxide layer and a first nitride layer, and etching to form a sidewall. In step S2, a first oxide layer 40 is formed on the bottom and sidewalls of the word line structure 20, and the sidewalls of the select pipe gate 3. Wherein the first oxide layer 40 is a silicon dioxide layer.
In step S3, the first silicon nitride layer 50 is filled in the gaps between the word line structures 20, between the word line structures 20 and the select pipe gates 3, and between the select pipe gates 3, and the first silicon nitride layer 50 is located on the first oxide layer 40, and the first silicon nitride layer 50 on the sidewalls of the select pipe gates 3 is etched to form the sidewalls 51.
Referring to fig. 4 in combination with fig. 1 to 3, the structure of the second silicon nitride layer of the present invention shown in fig. 4 is schematically illustrated after filling a third oxide layer between the select gates and performing chemical mechanical polishing. In step S4, a second oxide layer 41 having a closed structure with the first oxide layer 40 is formed on a side of the block word line 2 and the select pipe gate 3 different from the silicon substrate 1, and a second silicon nitride layer 52 is formed on a side of the second oxide layer 41 different from the silicon substrate 1. Wherein the second oxide layer 41 and the first oxide layer 40 formed on the side of the block word line 2 and the select pipe gate 3 different from the silicon substrate 1 have a closed structure.
In step S5, a third oxide layer 42 is disposed on the second silicon nitride layer 52, and the third oxide layer 42 fills the gap of the select pipe gate 3, and the third oxide layer 42 is polished chemically and mechanically to planarize to the upper surface of the second silicon nitride layer 52.
Referring to fig. 5 in combination with fig. 1 to 4, fig. 5 is a schematic diagram illustrating a structure of a gate top region etched back and exposed by a word line structure and a select transistor gate according to the present invention. In step S6, the word line structure 20 and the select transistor gate 3 are etched back, and the gate top region 6 is exposed.
Referring to fig. 6, fig. 6 is a schematic diagram illustrating a structure for removing the first silicon nitride layer between the word line structures according to the present invention. Step S7, removing the first silicon nitride layer 50 between the word line structures 20.
Referring to fig. 7, fig. 7 is a schematic diagram showing the structure of depositing nickel-platinum and titanium nitrides on the top region of the gate electrode, and performing a first annealing of nickel-silicon compounds and cleaning of nickel-platinum metal silicides. And S8, depositing nickel-platinum and titanium nitride in the top area 6 of the grid, and carrying out first annealing of nickel-silicon compound and cleaning of nickel-platinum metal silicide. The nickel silicon compound is annealed for the first time to form Ni 2 Si。
Referring to fig. 8, fig. 8 is a schematic diagram illustrating a structure in which a dielectric layer is deposited to cover a top region of a gate of a word line structure to form an air gap. In step S9, a dielectric layer 7 is deposited overlying the gate top regions 6 of the word line structures 20 such that air gaps 21 are formed between the word line structures 20. Wherein, the dielectric layer 7 is a silicon dioxide layer.
Referring to fig. 9, fig. 9 is a schematic diagram showing a second annealing structure of the nickel silicon compound according to the present invention. In step S10, a second anneal of the nickel silicon compound is performed to form a metal silicide 8 on the gate top region 6 of the word line structure 20. The nickel silicon compound is annealed a second time to form NiSi.
Obviously, the process integration method for improving the electric leakage between NAND flash word lines of the invention not only has strong process compatibility, but also can reduce wet cleaning and effectively reduce the possibility of collapse of the word line structures 20 by carrying out the second annealing of the nickel silicon compound after the air gaps 21 of the word line structures 20 are formed, thereby improving the electric leakage condition between the word line structures 20.
In summary, the process integration method for improving the electric leakage between NAND flash word lines of the invention not only has strong process compatibility, but also can reduce wet cleaning and effectively reduce the possibility of collapse of the word line structures by carrying out the second annealing of the nickel silicon compound after the air gap of the word line structures is formed, thereby improving the situation of electric leakage between the word line structures.
It will be appreciated by those skilled in the art that various modifications and variations can be made to the invention without departing from the spirit or scope of the invention. Accordingly, the present invention is deemed to cover any modifications and variations, if they fall within the scope of the appended claims and their equivalents.
Claims (8)
1. The process integration method for improving the electric leakage between the NAND flash word lines is characterized by comprising the following steps of:
step S1 is executed: providing a silicon-based substrate, and forming a block area word line and selection tube grids positioned at two sides of the block area word line on the silicon-based substrate;
step S2 is executed: forming a first oxide layer on the bottom and side walls of the word line structure and the side walls of the select pipe gate;
step S3 is executed: filling a first silicon nitride layer in gaps among the word line structures, among the word line structures and the selection tube grids and among the selection tube grids, wherein the first silicon nitride layer is positioned on the first oxide layer, and etching the first silicon nitride layer on the side wall of the selection tube grid to form a side wall;
step S4 is executed: forming a second oxide layer on one side of the block word line and the selection tube gate, which is different from the silicon-based substrate, and forming a second silicon nitride layer on one side of the second oxide layer, which is different from the silicon-based substrate;
step S5 is executed: setting a third oxide layer on the second silicon nitride layer, filling the gap of the selection tube gate by the third oxide layer, carrying out chemical mechanical polishing on the third oxide layer, and flattening the third oxide layer to the upper surface of the second silicon nitride layer;
step S6 is executed: etching the word line structure and the selection tube grid back, and exposing the top area of the grid;
step S7 is executed: removing the first silicon nitride layer between the word line structures;
step S8 is executed: depositing nickel-platinum and titanium nitride in the top area of the grid electrode, and carrying out first annealing on nickel-silicon compound and cleaning nickel-platinum metal silicide;
step S9 is performed: depositing a dielectric layer to cover the top regions of the gates of the word line structures so as to form air gaps between the word line structures;
step S10 is performed: a second anneal of the nickel silicon compound is performed to form a metal silicide in the top region of the gate of the wordline structure.
2. The process integration method for improving leakage between NAND flash word lines of claim 1, wherein the block area word lines further comprise word line structures with uniformly spaced apart pitch dimensions.
3. The process integration method for improving leakage between NAND flash wordlines of claim 1, wherein the block area wordlines and the select pipe gates are fabricated by a self-aligned dual pattern process.
4. The process integration method for improving the leakage between NAND flash word lines of claim 1, wherein the functional structure layers of the select transistor gates are stacked vertically and comprise a first polysilicon layer, an ONO layer (silicon oxide layer-silicon nitride layer-silicon oxide layer), and a second polysilicon layer in sequence from bottom to top.
5. The process integration method for improving leakage between NAND flash word lines of claim 4, wherein the first oxide layer is a silicon dioxide layer.
6. The process integration method for improving leakage between NAND flash word lines of claim 1, wherein a second oxide layer formed on a side of the block word line and the select pipe gate different from the silicon-based substrate is in a closed structure with the first oxide layer.
7. The process integration method for improving leakage between NAND flash word lines as recited in claim 1, wherein said nickel silicon compound is first annealed to form Ni 2 Si。
8. The process integration method for improving leakage between NAND flash word lines of claim 1, wherein the NiSi compound is annealed a second time to form NiSi.
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| CN101127304A (en) * | 2006-08-14 | 2008-02-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device making method |
| CN104505342A (en) * | 2014-11-28 | 2015-04-08 | 上海华力微电子有限公司 | Method for improving metal silicides |
| CN105097477A (en) * | 2015-06-29 | 2015-11-25 | 上海华力微电子有限公司 | Preparation method of nickel silicide |
| CN112530962A (en) * | 2020-12-21 | 2021-03-19 | 上海华力微电子有限公司 | Method for improving inter-control-gate morphology of NAND flash |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2010205782A (en) * | 2009-02-27 | 2010-09-16 | Renesas Electronics Corp | Method of manufacturing semiconductor device |
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|---|---|---|---|---|
| CN101127304A (en) * | 2006-08-14 | 2008-02-20 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device making method |
| CN104505342A (en) * | 2014-11-28 | 2015-04-08 | 上海华力微电子有限公司 | Method for improving metal silicides |
| CN105097477A (en) * | 2015-06-29 | 2015-11-25 | 上海华力微电子有限公司 | Preparation method of nickel silicide |
| CN112530962A (en) * | 2020-12-21 | 2021-03-19 | 上海华力微电子有限公司 | Method for improving inter-control-gate morphology of NAND flash |
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| Title |
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| 杂质分凝技术对肖特基势垒高度的调制;毛淑娟;罗军;闫江;;半导体技术;20130103(第01期);全文 * |
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