CN114004191A - Method, system, device and medium for extracting delay circuit macro model - Google Patents

Method, system, device and medium for extracting delay circuit macro model Download PDF

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CN114004191A
CN114004191A CN202111161438.4A CN202111161438A CN114004191A CN 114004191 A CN114004191 A CN 114004191A CN 202111161438 A CN202111161438 A CN 202111161438A CN 114004191 A CN114004191 A CN 114004191A
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matrix
delay circuit
parameters
transfer function
macro model
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邱志勇
郭振华
赵雅倩
李仁刚
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Suzhou Inspur Intelligent Technology Co Ltd
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    • G06F30/39—Circuit design at the physical level
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Abstract

The invention discloses a method for extracting a macro model of a delay circuit, which comprises the following steps: obtaining a delay circuit of a macro model to be extracted; embedding the delay circuit into preset parameters to obtain a delay circuit with parameters; calculating a transfer function of the delay circuit with the parameters and calculating all moments of the transfer function; constructing a projection matrix according to all moments of the transfer function; projecting the delay circuit with parameters in the projection matrix to obtain a macro model. The invention also discloses a system, a computer device and a readable storage medium. The scheme provided by the invention solves the problem of simulation analysis complexity in a high-speed integrated circuit by reducing the order of the model, and can reduce the calculation amount under the condition of keeping a certain calculation precision.

Description

Method, system, device and medium for extracting delay circuit macro model
Technical Field
The invention relates to the field of integration, in particular to a method, a system, equipment and a storage medium for extracting a macro model of a delay circuit.
Background
In the design process of the integrated circuit, one of the essential links is to perform simulation verification on the integrated circuit. With the increasing scale of integrated circuits, simulation verification is an important factor restricting the development of integrated circuits. The EDA software also provides various methods for simulation analysis of large-scale integrated circuits to quickly and accurately perform simulation verification on the designed circuits. However, as the operating frequency of the chip is higher and the number of components is higher, simulation analysis becomes a great challenge in the design process of the integrated circuit. For simulation analysis of large-scale analog integrated circuits, accurate mathematical modeling of original circuits is required, and various effects in the circuit operation process, such as transmission delay of signals, parasitic parameters of devices, and the like, need to be taken into consideration. The mathematical models of integrated circuits that take into account a number of factors are large and complex. It is time consuming to directly solve the exception, sometimes even impossible, which presents a significant challenge to EDA software.
Establishing a macro model of an original large-scale circuit becomes an important means for solving the problems of circuit simulation and analysis. Model reduction is an effective way to find circuit macro models. The main purpose of model order reduction is to provide redundant information in the original large-scale system and find an approximate smaller order reduction system, which can well approximate the input-output relationship of the original system and can retain the main properties of the original system, such as passivity, stability and the like. Therefore, the scale of the original system can be reduced to a great extent, and the simulation analysis difficulty and complexity of the original system are reduced. The main mechanism is that the main information of the high-dimensional space can be often represented through the low-dimensional space, and the original system is approximately represented in the low-dimensional space by constructing a proper low-dimensional space.
High speed interconnect circuits need to take the delay of the signal into account, so their mathematical model is typically a system of delayed differential equations. Directly solving a large-scale delay differential equation set is time-consuming, and the simulation analysis timeliness of the original delay circuit is seriously influenced. At present, a macro model establishing method for a large-scale delay circuit system mainly comprises a Taylor expansion method and a Laguerre expansion method, but the methods are not high enough in precision, and the obtained macro model cannot well approximate the input and output characteristics of an original system and the important properties of stability passivity and the like, so that the effective macro model establishing method for the delay circuit system is a problem which needs to be solved urgently in the field of circuit analysis and simulation at present.
Integrated circuit interconnect systems can generally be mathematically modeled using Differential Equations (differentials) but as the operating frequencies of integrated circuits increase, the propagation time of signals on the interconnect lines needs to be taken into account to meet timing requirements in high speed circuits, so that the entire integrated circuit interconnect system is built up as a system of delayed Differential Equations. The simulation analysis of the circuit needs to solve the delay differential equation set, and in the case of a large-scale integrated circuit interconnection system, the solution of the delay differential equation set is usually time-consuming and seriously affects the development cycle of the integrated circuit design. Particularly, in a differential algebra delay system, the solving process is more complex, and the working efficiency of the EDA software is seriously influenced.
Disclosure of Invention
In view of the above, in order to overcome at least one aspect of the above problems, an embodiment of the present invention provides a method for extracting a macro model of a delay circuit, including:
obtaining a delay circuit of a macro model to be extracted;
embedding the delay circuit into preset parameters to obtain a delay circuit with parameters;
calculating a transfer function of the delay circuit with the parameters and calculating all moments of the transfer function;
constructing a projection matrix according to all moments of the transfer function;
projecting the delay circuit with parameters in the projection matrix to obtain a macro model.
In some embodiments, in obtaining the delay circuit of the macro model to be extracted, the delay circuit is:
Figure BDA0003290064810000021
wherein the matrix E ∈ Rn×nIs a singular matrix formed by inductance L and capacitance C, the matrix A belongs to Rn×nIs composed of resistance, conductance values and correlation matrix between devices, matrix Ad∈Rn×nFormed by values of parasitic parameters in the interconnection line, B ∈ Rn×1Is an input matrix, u (t) is an input, C ∈ R1×nFor the output matrix, the unknown variable x (t) e Rn×1N is the order of the circuit system, namely the unknown quantity in the whole delay circuit, and tau is the signal transmission delay.
In some embodiments, the delay circuit is embedded with preset parameters to obtain a delay circuit with parameters, the delay circuit with parameters is:
Figure BDA0003290064810000031
wherein, the matrix E0Is composed of
Figure BDA0003290064810000032
n1+n2＝n，
Figure BDA0003290064810000033
Is of size n2The unit matrix of (2).
In some embodiments, calculating a transfer function of the delay circuit with the parameters and calculating all moments of the transfer function further comprises:
calculating a laplace transform of the delay circuit with the parameter, wherein the laplace transform of the delay circuit with the parameter is H (s, epsilon) ═ C (s (E + epsilon E)0)-A-Ade-sτ)-1B；
Computing a Taylor expansion of the Laplace transformed delay circuit with the parameters, wherein the Taylor expansion is
Figure BDA0003290064810000035
Taking the first three terms of Taylor expansion as e-sτIn which, among others,
Figure BDA0003290064810000036
e is to be-sτLaplace transform derivation with parametric delay circuits
Figure BDA0003290064810000037
Figure BDA0003290064810000038
Using (s, epsilon) as parameter pair
Figure BDA0003290064810000039
Figure BDA00032900648100000310
Performing Taylor expansion to obtain
Figure BDA00032900648100000311
Wherein, therein
Figure BDA00032900648100000312
Is the (i, j) th moment of the transfer function H (s, epsilon) and the matrix C is constant, then
Figure BDA00032900648100000313
Can be expressed as
Figure BDA0003290064810000041
By using
Figure BDA0003290064810000042
Figure BDA0003290064810000043
And
Figure BDA0003290064810000044
to obtain
Figure BDA0003290064810000045
Figure BDA0003290064810000046
In some embodiments, further comprising calculating
Figure BDA0003290064810000047
The recurrence relation of (1):
Figure BDA0003290064810000048
in some embodiments, constructing a projection matrix from all moments of the transfer function further comprises:
by using
Figure BDA0003290064810000049
Is converted into a matrix
Figure BDA00032900648100000410
Constructing a second-order Krylov subspace about the R matrix:
Figure BDA00032900648100000411
wherein i is 1,2, …, p0+1,j＝1,2,…,q0+1；
When j is 1, an orthogonal basis matrix V of a first row matrix in the matrix R is calculated1：
Figure BDA00032900648100000412
Wherein,
Figure BDA00032900648100000413
Figure BDA00032900648100000414
when j is 2, …, q0When +1, calculate the orthogonal base matrix L formed by the jth row matrix in the matrix RjThe j-th row matrix satisfies the following second-order Krylov subspace relationship:
Figure BDA0003290064810000051
Figure BDA0003290064810000052
wherein i is 1,2, …, p0+1；
Orthogonalizing the jth row matrix by using a second-order Arnoldi algorithm to obtain an orthogonal base matrix
Figure BDA0003290064810000053
For matrix
Figure BDA0003290064810000054
Partitioning:
Figure BDA0003290064810000055
wherein
Figure BDA0003290064810000056
Figure BDA0003290064810000057
Calculating an orthogonal base matrix L of a jth row matrix in a matrix Rj：
colspan{Q2}＝colspan{Lj}
Using the first j-1 row orthogonal matrix Vj-1And LjConstruction of a New matrix [ V ]j-1 Lj]To matrix [ V ]j-1 Lj]Orthogonalizing to obtain VjAccording to j 2, …, q0+1 calculation matrix R front q0Orthogonal basis matrix of +1 row matrix, Vj＝orth([Vj-1Lj])。
In some embodiments, projecting the delay circuit with parameters in the projection matrix to obtain a macro model, further comprises:
using projection matrices VjReducing the order of the delay circuit with parameters to obtain a macro model:
Figure BDA0003290064810000058
wherein,
Figure BDA0003290064810000059
Figure BDA00032900648100000510
the value of R is determined according to p in the matrix R0And q is0And (4) determining.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a delay circuit macro model extraction system, including:
the acquisition module is configured to acquire a delay circuit of the macro model to be extracted;
the parameter embedding module is configured to embed the delay circuit into preset parameters to obtain the delay circuit with parameters;
a calculation module configured to calculate a transfer function of the delay circuit with the parameters and to calculate all moments of the transfer function;
a construction module configured to construct a projection matrix from all moments of the transfer function;
a projection module configured to project the delay circuit with parameters in the projection matrix to obtain a macro model.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer apparatus, including:
at least one processor; and
a memory storing a computer program operable on the processor, wherein the processor executes the program to perform any of the steps of the delay circuit macro model extraction method described above.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer-readable storage medium storing a computer program, which when executed by a processor performs the steps of any one of the methods for extracting a delay circuit macro model as described above.
The invention has one of the following beneficial technical effects: the scheme provided by the invention solves the problem of simulation analysis complexity in a high-speed integrated circuit by reducing the order of the model, and can reduce the calculation amount under the condition of keeping a certain calculation precision.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
Fig. 1 is a schematic flowchart of a method for extracting a macro model of a delay circuit according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating relative errors between a reduced order system and an original system according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a delay circuit macro model extraction system according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a computer device provided in an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
According to an aspect of the present invention, an embodiment of the present invention provides a method for extracting a macro model of a delay circuit, as shown in fig. 1, which may include the steps of:
s1, obtaining a delay circuit of the macro model to be extracted;
s2, embedding the delay circuit into preset parameters to obtain a delay circuit with parameters;
s3, calculating the transfer function of the delay circuit with parameters and calculating all moments of the transfer function;
s4, constructing a projection matrix according to all moments of the transfer function;
s5, projecting the delay circuit with parameters in the projection matrix to obtain a macro model.
In some embodiments, in obtaining the delay circuit of the macro model to be extracted, the delay circuit is:
Figure BDA0003290064810000071
wherein the matrix E ∈ Rn×nIs a singular matrix composed of inductance L and capacitance C, and n belongs to Rn×nIs composed of resistance, conductance values and correlation matrix between devices, matrix Ad∈Rn×nFormed by values of parasitic parameters in the interconnection line, B ∈ Rn×1Is an input matrix, u (t) is an input, C ∈ R1×nFor the output matrix, the unknown variable x (t) e Rn×1As nodes in a circuitVoltage or branch current, n is the order of the circuit system, that is, the unknown quantity in the whole delay circuit, and τ is the signal transmission delay.
In some embodiments, the delay circuit is embedded with preset parameters to obtain a delay circuit with parameters, the delay circuit with parameters is:
Figure BDA0003290064810000081
wherein, the matrix E0Is composed of
Figure BDA0003290064810000082
n1+n2＝n，
Figure BDA0003290064810000083
Is of size n2The unit matrix of (2).
In some embodiments, calculating a transfer function of the delay circuit with the parameters and calculating all moments of the transfer function further comprises:
calculating a laplace transform of the delay circuit with the parameter, wherein the laplace transform of the delay circuit with the parameter is H (s, epsilon) ═ C (s (E + epsilon E)0)-A-Ade-sτ)-1B；
Computing a Taylor expansion of the Laplace transformed delay circuit with the parameters, wherein the Taylor expansion is
Figure BDA0003290064810000085
Taking the first three terms of Taylor expansion as e-sτIn which, among others,
Figure BDA0003290064810000086
e is to be-sτLaplace transform derivation with parametric delay circuits
Figure BDA0003290064810000087
Figure BDA0003290064810000088
Using (s, epsilon) as parameter pair
Figure BDA0003290064810000089
Figure BDA00032900648100000810
Performing Taylor expansion to obtain
Figure BDA00032900648100000811
Wherein, therein
Figure BDA00032900648100000812
Is the (i, j) th moment of the transfer function H (s, epsilon) and the matrix C is constant, then
Figure BDA00032900648100000813
Can be expressed as
Figure BDA00032900648100000814
By using
Figure BDA0003290064810000091
Figure BDA0003290064810000092
And
Figure BDA0003290064810000093
to obtain
Figure BDA0003290064810000094
Figure BDA0003290064810000095
In some embodiments, further comprising calculating
Figure BDA0003290064810000096
The recurrence relation of (1):
Figure BDA0003290064810000097
in some embodiments, constructing a projection matrix from all moments of the transfer function further comprises:
by using
Figure BDA0003290064810000098
Is converted into a matrix
Figure BDA0003290064810000099
Constructing a second-order Krylov subspace about the R matrix:
Figure BDA00032900648100000910
wherein i is 1,2, …, p0+1,j＝1,2,…,q0+1；
When j is 1, an orthogonal basis matrix V of a first row matrix in the matrix R is calculated1：
Figure BDA00032900648100000911
Wherein,
Figure BDA00032900648100000912
Figure BDA00032900648100000913
when j is 2, …, q0When +1, calculate the orthogonal base matrix L formed by the jth row matrix in the matrix RjThe j-th row matrix satisfies the following second-order Krylov subspace relationship:
Figure BDA0003290064810000101
Figure BDA0003290064810000102
wherein i is 1,2, …, p0+1；
Orthogonalizing the jth row matrix by using a second-order Arnoldi algorithm to obtain an orthogonal base matrix
Figure BDA0003290064810000103
For matrix
Figure BDA0003290064810000104
Partitioning:
Figure BDA0003290064810000105
wherein
Figure BDA0003290064810000106
Figure BDA0003290064810000107
Calculating an orthogonal base matrix L of a jth row matrix in a matrix Rj：
colspan{Q2}＝colspan{Lj}
Using the first j-1 row orthogonal matrix Vj-1And LjConstruction of a New matrix [ V ]j-1 Lj]To matrix [ V ]j-1 Lj]Orthogonalizing to obtain VjAccording to j 2, …, q0+1 calculation matrix R front q0Orthogonal basis matrix of +1 row matrix, Vj＝orth([Vj-1Lj])。
In some embodiments, projecting the delay circuit with parameters in the projection matrix to obtain a macro model, further comprises:
using projection matrices VjReducing the order of the delay circuit with parameters to obtain a macro model:
Figure BDA0003290064810000108
wherein,
Figure BDA0003290064810000109
Figure BDA00032900648100001010
the value of R is determined according to p in the matrix R0And q is0And (4) determining.
In the embodiment of the invention, in order to solve the problem of complexity of simulation analysis in a high-speed integrated circuit, a novel model order reduction method for reducing the calculated amount under the condition of keeping a certain calculation precision is provided.
Firstly, establishing a mathematical model of an original large-scale delay circuit, wherein the mathematical model is a delay differential algebraic system:
Figure BDA0003290064810000111
in the formula (1), the matrix E is formed by Rn×nIs a singular matrix formed by inductance L and capacitance C, the matrix A belongs to Rn×nIs composed of resistance, conductance values and correlation matrix between devices, matrix Ad∈Rn×nIs formed by the values of the parasitic parameters in the interconnect lines. B is belonged to Rn×1Is an input matrix, u (t) is an input, C ∈ R1×nIs an output matrix; unknown variable x (t) e Rn×1Is the node voltage or branch current in the circuit. n is the order of the circuit system, namely the unknown quantity number of the whole system equation (1), and tau is the signal transmission delay.
Because E is a singular matrix, the solution of the differential algebraic system, especially the differential algebraic system with high index, is time-consuming, so that the conversion of the differential algebraic system into the ordinary differential system is an effective method for solving the problem. The invention uses epsilon embedding technology to convert the differential algebraic delay system into a differential delay system with parameters, and uses a model order reduction method to reduce the order of the differential algebraic delay system, and the reduced system can be well approximate to an original large-scale differential algebraic system.
Considering a differential algebraic delay system as in equation (1), where the coefficient matrix E is a singular matrix, which is converted to a nonsingular matrix using an epsilon embedding technique, a delay system of the form (2) with parameters epsilon can be obtained, where the values of the parameters epsilon satisfy epsilon >0 and epsilon < 1.
Figure BDA0003290064810000112
Here matrix E0Is composed of
Figure BDA0003290064810000113
n1+n2＝n,
Figure BDA0003290064810000114
Is of size n2The unit matrix of (2). Laplace transformation of system (2)
H(s,ε)＝C(s(E+εE0)-A-Ade-sτ)-1B (3)
And (3) referring to a transfer function of the system (2), wherein the transfer function is an expression form of the system (2) in a frequency domain, next, extracting important information of the system (2) from the formula (3), and performing model reduction on the parameter system (2) so as to extract a macro model of the original circuit system.
Taylor expansion is carried out on the formula (3), a Taylor expansion coefficient is called as a moment of the system (3), the moment contains important information of the original system (2), and as long as the macro model contains most moment information of the original system, input and output information and basic properties of the original large-scale circuit system can be well reflected. The taylor expansion of the exponential term in equation (3) is:
Figure BDA0003290064810000121
taking the first three items as e-sτApproximation of
Figure BDA0003290064810000122
Bringing formula (4) into (3) yields:
Figure BDA0003290064810000123
taylor expansion is performed on equation (5) using (s, ε) as a parameter:
Figure BDA0003290064810000124
wherein
Figure BDA0003290064810000125
Is the (i, j) th moment of the transfer function H (s, epsilon) and the matrix C is constant, then
Figure BDA0003290064810000126
Can be expressed as
Figure BDA0003290064810000127
Further, in the present invention,
Figure BDA0003290064810000128
can be expressed as:
Figure BDA0003290064810000129
following search based on equation (7)
Figure BDA00032900648100001210
When i is 0 and j is 0
Figure BDA00032900648100001211
When i >0, j >0
Figure BDA00032900648100001212
Figure BDA00032900648100001213
Figure BDA00032900648100001214
Figure BDA00032900648100001215
Figure BDA00032900648100001216
Figure BDA00032900648100001217
According to the above relation, it can be summarized
Figure BDA0003290064810000131
The recurrence relation of (1):
Figure BDA0003290064810000132
at this point, all moments in equation (6) can be determined by recursion of equation (8)
Figure BDA0003290064810000133
After all moments in the transfer function (6) are obtained, the original system (2) is reduced by a moment matching model reduction technique. Moment matching technique to
Figure BDA0003290064810000134
Constructing a projection matrix V based on the moment information, and further constructing a projection matrix V based on the moment informationThe original system (2) is projected in a V-spanned space, whereby a reduced-order system of the original system (2), i.e. a macro-model of the original circuitry, is obtained. The procedure for solving the projection matrix V is given below, and
Figure BDA0003290064810000135
a matrix written in the form:
Figure BDA0003290064810000136
constructing a second-order Krylov subspace about the R matrix:
Figure BDA0003290064810000137
wherein i is 1,2, …, p0+1,j＝1,2,…,q0+1
Then, the first row matrix in the R matrix is calculated
Figure BDA0003290064810000138
The space formed by stretching
Figure BDA0003290064810000139
Obtaining an orthogonal basis matrix V1：
Figure BDA00032900648100001310
Wherein,
Figure BDA00032900648100001311
Figure BDA00032900648100001312
when j is 2,3, … q0When +1, the space spanned by the j-th row is marked as:
Figure BDA0003290064810000141
in solving for
Figure BDA0003290064810000142
In the process, it is found that
Figure BDA0003290064810000143
Conforms to a new recursion relational expression
Figure BDA0003290064810000144
In the formula (10), the compound represented by the formula (10),
Figure BDA0003290064810000145
Figure BDA0003290064810000146
(10) the formula can be constructed as a second order Krylov subspace
Figure BDA0003290064810000147
I.e. the orthogonal basis matrix L formed by the jth row matrixjThe j-th row matrix satisfies the following second-order Krylov subspace relationship:
Figure BDA0003290064810000148
(11) in the formula
Figure BDA0003290064810000149
The present invention uses a second order Arnoldi methodBy orthogonalizing equation (11), an orthogonal basis matrix can be obtained
Figure BDA00032900648100001410
For orthogonal matrix
Figure BDA00032900648100001411
Is divided into blocks to obtain
Figure BDA00032900648100001412
In formula (12):
Figure BDA0003290064810000151
according to the formulas (11) and (8), the compounds are obtained
colspan{Q2}＝colspan{Lj}
So far, an orthogonal matrix L can be obtainedjAccording to the obtained orthogonal matrix Vj-1And LjConstruction of a New matrix [ V ]j-1Lj]To matrix [ V ]j-1 Lj]Orthogonalizing to obtain Vj
Vj＝orth([Vj-1 Lj])
VjIs a space base matrix formed by the matrix of the first j rows in the formula (9). Sequentially calculating in a recursion way to obtain an orthogonal matrix V formed by all the matrixes in the formula (9), and obtaining a reduced-order matrix by taking V as a system (2)
Figure BDA0003290064810000152
In the formula (13)
Figure BDA0003290064810000153
Figure BDA0003290064810000154
The system (13) is a reduced order system of the system (2), wherein the value of r is according to p in the formula (9)0And q is0And (4) determining.
The system (13) can well approximate the original delay differential algebraic system (1), and the system (13) is called a macro model of the original large-scale delay circuit, and the macro model can keep important properties of the input-output relation, passivity and the like of the original circuit.
In the RLC circuit, a newly proposed algorithm and a reference algorithm reduce the original system from 607 th order to 36 th order, and a macro model is an efficient approximate system of the original large-scale system, so that an error exists in the approximate process. The invention compares the output of the obtained macro model with the output of the original large-scale system, and calculates the relative error of the output of the macro model, and the relative error calculation mode is as follows:
Figure BDA0003290064810000161
as shown in FIG. 2, y is the output of the original system, yrIs the output of the macro model. It can be observed that the relative error between the output of the macro model obtained by the present invention and the original system output is controlled at 10-5And the higher accuracy is achieved.
The scheme provided by the invention solves the problem of simulation analysis complexity in a high-speed integrated circuit by reducing the order of the model, and can reduce the calculation amount under the condition of keeping a certain calculation precision. Therefore, model reduction is carried out on the large-scale differential algebraic delay system, and a differential algebraic system with a smaller scale is searched to approximate the original large-scale system, so that the main properties of the original large-scale system are reserved.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a delay circuit macro model extraction system 400, as shown in fig. 3, including:
an obtaining module 401 configured to obtain a delay circuit of a macro model to be extracted;
a parameter embedding module 402 configured to embed the delay circuit into a preset parameter to obtain a delay circuit with a parameter;
a calculation module 403 configured to calculate a transfer function of the delay circuit with the parameters and to calculate all moments of the transfer function;
a construction module 404 configured to construct a projection matrix from all moments of the transfer function;
a projection module 405 configured to project the delay circuit with parameters in the projection matrix to obtain a macro model.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 4, an embodiment of the present invention further provides a computer apparatus 501, including:
at least one processor 520; and
the memory 510, the memory 510 stores a computer program 511 that is executable on the processor, and the processor 520 executes the program to perform any of the steps of the method for extracting a macro model of a delay circuit as described above.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 5, an embodiment of the present invention further provides a computer-readable storage medium 601, where the computer-readable storage medium 601 stores computer program instructions 610, and the computer program instructions 610, when executed by a processor, perform the steps of any one of the methods for extracting a delay circuit macro model as above.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims (10)

1. A method for extracting a macro model of a delay circuit is characterized by comprising the following steps:
obtaining a delay circuit of a macro model to be extracted;
embedding the delay circuit into preset parameters to obtain a delay circuit with parameters;
calculating a transfer function of the delay circuit with the parameters and calculating all moments of the transfer function;
constructing a projection matrix according to all moments of the transfer function;
projecting the delay circuit with parameters in the projection matrix to obtain a macro model.
2. The method of claim 1, wherein in obtaining the delay circuit of the macro model to be extracted, the delay circuit is:
Figure FDA0003290064800000011
wherein the matrix E ∈ Rn×nIs a singular matrix formed by inductance L and capacitance C, the matrix A belongs to Rn×nIs composed of resistance, conductance values and correlation matrix between devices, matrix Ad∈Rn×nFormed by values of parasitic parameters in the interconnection lines, B∈Rn×1Is an input matrix, u (t) is an input, C ∈ R1×nFor the output matrix, the unknown variable x (t) e Rn×1N is the order of the circuit system, namely the unknown quantity in the whole delay circuit, and tau is the signal transmission delay.
3. The method of claim 2, wherein the delay circuit is embedded with preset parameters to obtain a parameterized delay circuit, the parameterized delay circuit being:
Figure FDA0003290064800000012
wherein, the matrix E0Is composed of
Figure FDA0003290064800000013
n1+n2＝n，
Figure FDA0003290064800000014
Is of size n2The unit matrix of (2).
4. The method of claim 3, wherein calculating a transfer function of the delay circuit with the parameters and calculating all moments of the transfer function, further comprises:
calculating a laplace transform of the delay circuit with the parameter, wherein the laplace transform of the delay circuit with the parameter is H (s, epsilon) ═ C (s (E + epsilon E)0)-A-Ade-sτ)-1B；
Computing a Taylor expansion of the Laplace transformed delay circuit with the parameters, wherein the Taylor expansion is
Figure FDA0003290064800000021
Taking the first three terms of Taylor expansion as e-sτIn which, among others,
Figure FDA0003290064800000022
e is to be-sτLaplace transform derivation with parametric delay circuits
Figure FDA0003290064800000023
Figure FDA0003290064800000024
Using (s, epsilon) as parameter pair
Figure FDA0003290064800000025
Performing Taylor expansion to obtain
Figure FDA0003290064800000026
Wherein, therein
Figure FDA0003290064800000027
Is the (i, j) th moment of the transfer function H (s, epsilon) and the matrix C is constant, then
Figure FDA0003290064800000028
Can be expressed as
Figure FDA0003290064800000029
By using
Figure FDA00032900648000000210
Figure FDA00032900648000000211
And
Figure FDA00032900648000000212
to obtain
Figure FDA00032900648000000213
Figure FDA00032900648000000214
5. The method of claim 4, further comprising computing
Figure FDA00032900648000000215
The recurrence relation of (1):
Figure FDA00032900648000000216
6. the method of claim 5, wherein constructing a projection matrix from all moments of the transfer function further comprises:
by using
Figure FDA00032900648000000217
Is converted into a matrix
Figure FDA00032900648000000218
Constructing a second-order Krylov subspace about the R matrix:
Figure FDA0003290064800000031
wherein i is 1,2, …, p0+1，j＝1，2，…，q0+1；
When j is 1, an orthogonal basis matrix V of a first row matrix in the matrix R is calculated1：
Figure FDA0003290064800000032
Wherein,
Figure FDA0003290064800000033
Figure FDA0003290064800000034
when j is 2, …, q0When +1, calculate the orthogonal base matrix L formed by the jth row matrix in the matrix RjThe j-th row matrix satisfies the following second-order Krylov subspace relationship:
Figure FDA0003290064800000035
wherein i is 1,2, …, p0+1；
Orthogonalizing the jth row matrix by using a second-order Amoldi algorithm to obtain an orthogonal base matrix
Figure FDA0003290064800000036
For matrix
Figure FDA0003290064800000037
Partitioning:
Figure FDA0003290064800000038
wherein
Figure FDA0003290064800000039
Calculating an orthogonal base matrix L of a jth row matrix in a matrix Rj：
colspan{Q2}＝colspan{Lj}
Using the first j-1 row orthogonal matrix Vj-1And LjConstruction of a New matrix [ V ]j-1 Lj]To matrix [ V ]j-1 Lj]Orthogonalizing to obtain VjAccording to j 2, …, q0+1 calculation matrix R front q0Orthogonal basis matrix of +1 row matrix, Vj＝orth([Vj-1 Lj])。
7. The method of claim 6, wherein projecting the delay circuit with parameters in the projection matrix to obtain a macro model, further comprises:
using projection matrices VjReducing the order of the delay circuit with parameters to obtain a macro model:
Figure FDA0003290064800000041
wherein,
Figure FDA0003290064800000042
Figure FDA0003290064800000043
the value of R is determined according to p in the matrix R0And q is0And (4) determining.
8. A delay circuit macro model extraction system, comprising:
the acquisition module is configured to acquire a delay circuit of the macro model to be extracted;
the parameter embedding module is configured to embed the delay circuit into preset parameters to obtain the delay circuit with parameters;
a calculation module configured to calculate a transfer function of the delay circuit with the parameters and to calculate all moments of the transfer function;
a construction module configured to construct a projection matrix from all moments of the transfer function;
a projection module configured to project the delay circuit with parameters in the projection matrix to obtain a macro model.
9. A computer device, comprising:
at least one processor; and
memory storing a computer program operable on the processor, wherein the processor executes the program to perform the steps of the method according to any of claims 1-7.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the steps of the method according to any one of claims 1 to 7.
CN202111161438.4A 2021-09-30 2021-09-30 Method, system, device and medium for extracting delay circuit macro model Pending CN114004191A (en)

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