CN116151324A - RC interconnection delay prediction method based on graph neural network - Google Patents
RC interconnection delay prediction method based on graph neural network Download PDFInfo
- Publication number
- CN116151324A CN116151324A CN202310177071.8A CN202310177071A CN116151324A CN 116151324 A CN116151324 A CN 116151324A CN 202310177071 A CN202310177071 A CN 202310177071A CN 116151324 A CN116151324 A CN 116151324A
- Authority
- CN
- China
- Prior art keywords
- graph
- neural network
- path
- layer
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/049—Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/08—Learning methods
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biomedical Technology (AREA)
- Biophysics (AREA)
- General Health & Medical Sciences (AREA)
- Data Mining & Analysis (AREA)
- Evolutionary Computation (AREA)
- Computational Linguistics (AREA)
- Molecular Biology (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Artificial Intelligence (AREA)
- Neurology (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention provides an RC interconnection delay prediction method based on a graph neural network, which comprises the steps of firstly searching a plurality of RC paths based on a DFS (DepthFirstSearch) algorithm according to a SPEF parasitic parameter netlist, and carrying out graph representation on each RC path, wherein nodes in the RC paths correspond to nodes of a graph, connection relations among the nodes correspond to edges of the graph, and a capacitance to ground value and a coupling resistance value are respectively defined as node attributes and edge attributes of the graph; and then carrying out time delay reasoning through a reasoning framework based on the graph convolution neural network to obtain a result. The method comprises two parts: SPEF analysis module, graph neural network prediction module. Compared with the method using an Elmore model and a D2M model, the method uses the proper graph neural network to conduct graph modeling on the RC path, can predict the delay of the RC interconnection line more rapidly and accurately, find out timing violations early, and shorten convergence time.
Description
Technical Field
The invention belongs to the field of chip interconnection line delay prediction, and particularly relates to an RC interconnection delay prediction method based on a graph neural network.
Background
The path delay calculation in the traditional design flow is solved by an accurate model, and the efficiency of the path delay calculation is more limited along with the increase of the circuit scale. The line delay in the advanced process has higher proportion in the time sequence, and causes long iteration period and more times in the design process. The conventional interconnection line timing calculation method includes Wire-loadModels, elmoledelay and the like. The time delay of the interconnection line greatly influences the accurate calculation of the time delay precision due to factors such as different lengths, different densities, different distributions, different equivalent models, different propagation methods and the like of the winding wires. And the circuit simulation software such as HSPICE is used for calculating the interconnection line delay, so that huge time consumption is brought.
Disclosure of Invention
The invention aims to provide an RC interconnection delay prediction method based on a graph neural network, which aims to solve the technical problem that RC interconnection delay can be rapidly and accurately predicted in a layout and wiring stage.
In order to solve the technical problems, the specific technical scheme of the invention is as follows:
RC interconnection delay prediction method based on Graph neural network, wherein the Graph neural network is Graph ConvolutionalNetwork, GCN; RC interconnection delay is delay of signal transmission carriers among unit circuits, in modules and among multi-chip assemblies after the integrated circuit is laid out and wired; the method comprises the following steps:
s1: searching RC paths corresponding to source points to destination points through depth-first search principle according to the standard parasitic exchange format StandardParasiticExtraction Format netlist related information extracted after layout and wiring, and constructing graph topology information of the RC paths to be predicted and characteristic information of nodes and edges; obtaining a label value of RC path delay through HSPICE;
s2: taking the graph topology information, the characteristic information of nodes and edges and the label value of each RC path in the step S1 as the input of a graph rolling neural network, wherein the network is trained to establish the relation between graph representation information and delay information acquired from the RC path and serve as the model parameters of the graph rolling neural network;
s3: and (2) generating graph topology information, node and side characteristic information of the RC path to be predicted by using the step S1, and taking the trained graph convolution neural network model parameters in the step S2 as the input of the graph convolution neural network to perform reasoning of RC interconnection delay.
Further, the step S1 specifically includes the following steps:
s11: reading a SPEF netlist, generating a corresponding RCT structure body for each RC network in a SPEF file, and storing the corresponding RCT structure body into the RCT_MAP structure body;
s12: traversing each RCT in the RCT_MAP structure body, searching out an RC Path RC_Path from a starting point sourcepoint to a finishing point by a DFS algorithm, then expanding a one-hop 1-hop node, and storing RC Path information into the RC_Path structure body; if the RCT has a plurality of endpoints, repeatedly executing the RC path searching process;
s13: converting each RC path into a directed Graph to generate a corresponding adjacency matrix; defining a capacitance to ground as a node characteristic in Graph, expressing a coupling resistance as an edge characteristic in Graph, extracting a port capacitance pin_cap from a cell library, accumulating the port capacitance pin_cap into end point characteristic information, and generating a corresponding characteristic matrix;
s14: performing RC interconnection delay calculation on the SPEF netlist through HSPICE, wherein the obtained delay information of each RC path is used as a label value for graph convolution neural network training;
s15: the adjacency matrix, the feature matrix and the label value of each RC path are used as input information for graph convolution neural network training.
Further, the step S3 specifically includes the following steps:
s31: taking the adjacency matrix used for representing the topology information of the graph and the feature matrix used for representing the node and the side information obtained in the step S1 as the input of the graph neural network; the graphic neural network architecture consists of a graphic convolution layer GraphConvolutional Layer, a graphic pooling layer GraphPoolingLayer and a full connection layer Fully-ConnectedLayer;
s32: in a multi-layer graph convolution layer, a first layer takes graph data formed by an adjacent matrix and a feature matrix as input, carries out neighborhood aggregation and message transmission, and calculates to obtain a new node embedding; starting from the second layer, the output of each layer of graph convolution layer is the input of the next layer, and the output of the last layer of graph convolution layer obtains the final node embedding;
s33: inputting the output of the last graph convolution layer in the step S32 to a graph pooling layer, and downsampling an RC path graph with the latest node embedded information to obtain a single vector for representing the characteristics of the overall graph of the RC path;
s34: and sending the output of the pooling layer into a full-connection layer for dimension transformation to obtain the delay output of the RC path.
Further, in step S3, the graph convolution neural network adopts a main neighborhood aggregation graph convolution, so that the RC path delay data characteristic can be accurately represented.
The RC interconnection delay prediction method based on the graph neural network has the following advantages:
1. the invention provides an intelligent time sequence RC interconnection delay prediction method based on a graph convolution neural network. The SPEF netlist is simulated by using a circuit analysis tool HSPICE to establish a sample data set for training. And performing characteristic engineering on the RC path in the SPEF netlist, and characterizing delay information of the RC path through a graph neural network method.
2. The method adopts a graph convolutional neural network method, and can obtain better model fitting effect and running speed when selecting proper hidden layer channel number and layer number.
3. The invention relates to modeling RC interconnection into graph structure data, and directly modeling interconnection delay by using a graph neural network, and the method has good interpretability.
Therefore, the method can rapidly and accurately realize the prediction of RC interconnection delay, and has good practical application value.
Drawings
FIG. 1 is a schematic diagram of an RC interconnect delay prediction framework of the present invention;
FIG. 2 is a SPEF parsing flow diagram of the present invention;
FIG. 3 is a schematic illustration of a main neighborhood aggregation graph convolution of the present invention;
FIG. 4 is a schematic diagram of a graph roll-up neural network model according to the present invention.
Detailed Description
In order to better understand the purpose, structure and function of the present invention, the RC interconnection delay prediction method based on the graph neural network is described in further detail below with reference to the accompanying drawings.
In this embodiment, an RC interconnection delay prediction method based on a graph neural network is provided, which is specifically divided into the following steps:
s1: finding RC paths corresponding to source points (source points) to destination points (endpoint) according to SPEF (StandardParasiticExtractionFormat) netlist related information extracted after layout and wiring, and constructing graph topology information of the RC paths to be predicted and characteristic information of nodes and edges. Obtaining a label value of RC path delay through HSPICE;
s2: taking the graph topology information, the characteristic information of nodes and edges and the label value of each RC path in the step S1 as the input of a graph rolling neural network, wherein the network is trained to establish the relation between graph representation information and delay information acquired from the RC path and serve as the model parameters of the graph rolling neural network;
s3: and (2) generating graph topology information, node and side characteristic information of the RC path to be predicted by using the step S1, and taking the trained graph convolution neural network model parameters in the step S2 as the input of the graph convolution neural network to perform reasoning of RC interconnection delay.
The step S1 specifically includes the following:
s11: reading a SPEF netlist, generating a corresponding RCT structure body for each RC network in a SPEF file, and storing the corresponding RCT structure body into the RCT_MAP structure body;
s12: traversing each RCT in the RCT_MAP structure, searching out an RC Path (RC_Path) from a starting point (sourcepoint) to an ending point (ends) through a DFS algorithm, then expanding a one-hop (1-hop) node, and storing RC Path information in the RC_Path structure. If the RCT has multiple endpoints, then the process described above in S12 is repeated;
s13: converting each RC path into a directed Graph to generate a corresponding adjacency matrix; defining the capacitance to ground as node characteristics in Graph, expressing the coupling resistance as edge characteristics in Graph, extracting port capacitance (pin_cap) from a cell library, accumulating the port capacitance (pin_cap) into end point characteristic information, and generating a corresponding characteristic matrix;
s14: performing RC interconnection delay calculation on the SPEF netlist through HSPICE, wherein the obtained delay information of each RC path is used as a label value for graph convolution neural network training;
s15: the adjacency matrix, the feature matrix and the label value of each RC path are used as input information for graph convolution neural network training;
the step S3 specifically includes the following:
s31: and (3) taking the adjacency matrix used for representing the topology information of the graph and the feature matrix used for representing the node and the side information obtained in the step (S1) as the input of the graph neural network. The graphic neural network architecture consists of a graphic convolution layer (GraphConvolutional Layer), a graphic pooling layer (graphpooling layer) and a full-connection layer (full-connection layer);
s32: in a multi-layer graph convolution layer (graphConvolution layer), a first layer takes graph data composed of an adjacent matrix and a feature matrix as input, performs neighborhood aggregation and message transmission, and calculates a new node embedding (node embedding). Starting from the second layer, the output of each layer of graph convolution layer is the input of the next layer, and the output of the last layer of graph convolution layer obtains the final node embedding;
s33: inputting the output of the last graph convolution layer in the step S32 to a graph pooling layer (GraphPoolingLayer), and downsampling an RC path graph with the latest node embedded information to obtain a single vector for representing the characteristics of the overall graph of the RC path;
s34: the output of the pooling layer is sent into a full-connection layer (Fully-ConnectedLayer), and the dimension transformation is carried out to obtain the delay output of the RC path;
for example: the constructed graph convolution neural network uses a main neighborhood aggregation graph convolution (PNAConv), the number of layers of the graph neural network is 3, the number of neurons of a hidden layer is 64, the number of layers of a graph pooling layer is 3, the number of predicted full-connection layers is 3, the dimension of edge characteristics is 1, and the dimension of node characteristics is 1. Then calculating the average absolute value error between the predicted value and the true value of the network; the model parameters are then optimized by an adaptive moment estimation optimizer Adam to minimize the mean absolute value error. For example: the training parameters of the graph neural network are 128 training batches, the initial learning rate is 0.001, the optimizer selects the adaptive moment estimation optimizer Adam, and the loss function selects the average absolute value error function.
It will be understood that the invention has been described in terms of several embodiments, and that various changes and equivalents may be made to these features and embodiments by those skilled in the art without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (4)
1. The RC interconnection delay prediction method based on the graph neural network is characterized in that the graph neural network is a graph roll-up neural network GCN; the RC interconnection delay is the delay of signal transmission carriers among unit circuits, in modules and among multi-chip assemblies after the integrated circuit is laid out and wired; the method comprises the following steps:
s1: finding RC paths corresponding to source points to destination points according to the information related to a SPEF netlist in a standard parasitic exchange format extracted after layout and wiring by a depth-first search Depth First Search principle, and constructing graph topology information and characteristic information of nodes and edges of the RC paths to be predicted; obtaining a label value of RC path delay through HSPICE;
s2: taking the graph topology information, the characteristic information of nodes and edges and the label value of each RC path in the step S1 as the input of a graph rolling neural network, wherein the network is trained to establish the relation between graph representation information and delay information acquired from the RC path and serve as the model parameters of the graph rolling neural network;
s3: and (2) generating graph topology information, node and side characteristic information of the RC path to be predicted by using the step S1, and taking the trained graph convolution neural network model parameters in the step S2 as the input of the graph convolution neural network to perform reasoning of RC interconnection delay.
2. The method for predicting RC interconnection delay based on the graph neural network according to claim 1, wherein the step S1 specifically includes the following steps:
s11: reading a SPEF netlist, generating a corresponding RCT structure body for each RC network in a SPEF file, and storing the corresponding RCT structure body into the RCT_MAP structure body;
s12: traversing each RCT in the RCT_MAP structure body, searching out an RC Path RC_Path from a starting point sourcepoint to a finishing point by a DFS algorithm, then expanding a one-hop 1-hop node, and storing RC Path information into the RC_Path structure body; if the RCT has a plurality of endpoints, repeatedly executing the RC path searching process;
s13: converting each RC path into a directed Graph to generate a corresponding adjacency matrix; defining a capacitance to ground as a node characteristic in Graph, expressing a coupling resistance as an edge characteristic in Graph, extracting a port capacitance pin_cap from a cell library, accumulating the port capacitance pin_cap into end point characteristic information, and generating a corresponding characteristic matrix;
s14: performing RC interconnection delay calculation on the SPEF netlist through HSPICE, wherein the obtained delay information of each RC path is used as a label value for graph convolution neural network training;
s15: the adjacency matrix, the feature matrix and the label value of each RC path are used as input information for graph convolution neural network training.
3. The method for predicting RC interconnection delay based on the graph neural network according to claim 2, wherein the step S3 specifically includes the following steps:
s31: taking the adjacency matrix used for representing the topology information of the graph and the feature matrix used for representing the node and the side information obtained in the step S1 as the input of the graph neural network; the graph neural network architecture consists of a graph convolution Layer Graph Convolutional Layer, a graph pooling Layer Graph Pooling Layer and a full connection Layer Fully-Connected Layer;
s32: in the multi-layer graph convolution layer Graph Convolutional Layer, a first layer takes graph data formed by an adjacent matrix and a feature matrix as input, carries out neighborhood aggregation and message transmission, and calculates to obtain a new node embedding; starting from the second layer, the output of each layer of graph convolution layer is the input of the next layer, and the output of the last layer of graph convolution layer obtains the final node embedding;
s33: inputting the output of the last graph convolution layer in the step S32 to a graph pooling layer Graph Pooling Layer, and downsampling an RC path graph with the latest node embedded information to obtain a single vector for representing the characteristics of the overall graph of the RC path;
s34: and sending the output of the pooling Layer into a full-Connected Layer for dimension transformation to obtain the delay output of the RC path.
4. The method for predicting the RC interconnection delay based on the graph neural network according to claim 2, wherein in the step S3, the graph convolution neural network adopts a main neighborhood aggregation graph convolution, so that the RC path delay data characteristic can be accurately represented.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310177071.8A CN116151324A (en) | 2023-02-28 | 2023-02-28 | RC interconnection delay prediction method based on graph neural network |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310177071.8A CN116151324A (en) | 2023-02-28 | 2023-02-28 | RC interconnection delay prediction method based on graph neural network |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116151324A true CN116151324A (en) | 2023-05-23 |
Family
ID=86359901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310177071.8A Pending CN116151324A (en) | 2023-02-28 | 2023-02-28 | RC interconnection delay prediction method based on graph neural network |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116151324A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116522999A (en) * | 2023-06-26 | 2023-08-01 | 深圳思谋信息科技有限公司 | Model searching and time delay predictor training method, device, equipment and storage medium |
| CN116861782A (en) * | 2023-07-05 | 2023-10-10 | 南京邮电大学 | Line delay prediction method based on machine learning and node effective capacitance |
| CN117709258A (en) * | 2023-12-12 | 2024-03-15 | 南京邮电大学 | Path time sequence prediction method based on graph neural network |
| CN117829083A (en) * | 2024-03-01 | 2024-04-05 | 上海励驰半导体有限公司 | Routing method and device based on neural network, electronic equipment and storage medium |
-
2023
- 2023-02-28 CN CN202310177071.8A patent/CN116151324A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116522999A (en) * | 2023-06-26 | 2023-08-01 | 深圳思谋信息科技有限公司 | Model searching and time delay predictor training method, device, equipment and storage medium |
| CN116522999B (en) * | 2023-06-26 | 2023-12-15 | 深圳思谋信息科技有限公司 | Model searching and time delay predictor training method, device, equipment and storage medium |
| CN116861782A (en) * | 2023-07-05 | 2023-10-10 | 南京邮电大学 | Line delay prediction method based on machine learning and node effective capacitance |
| CN116861782B (en) * | 2023-07-05 | 2024-04-02 | 南京邮电大学 | Line delay prediction method based on machine learning and node effective capacitance |
| CN117709258A (en) * | 2023-12-12 | 2024-03-15 | 南京邮电大学 | Path time sequence prediction method based on graph neural network |
| CN117829083A (en) * | 2024-03-01 | 2024-04-05 | 上海励驰半导体有限公司 | Routing method and device based on neural network, electronic equipment and storage medium |
| CN117829083B (en) * | 2024-03-01 | 2024-05-28 | 上海励驰半导体有限公司 | Routing method and device based on neural network, electronic equipment and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN116151324A (en) | RC interconnection delay prediction method based on graph neural network | |
| Lu et al. | TP-GNN: A graph neural network framework for tier partitioning in monolithic 3D ICs | |
| CN112382082A (en) | Method and system for predicting traffic running state in congested area | |
| Liu et al. | PSO-based power-driven X-routing algorithm in semiconductor design for predictive intelligence of IoT applications | |
| CN103905246B (en) | Link prediction method based on grouping genetic algorithm | |
| CN113762595B (en) | Traffic time prediction model training method, traffic time prediction method and equipment | |
| CN114303150A (en) | Machine learning driven prediction in integrated circuit design | |
| CN109787821B (en) | Intelligent prediction method for large-scale mobile client traffic consumption | |
| CN115146580A (en) | Integrated circuit path delay prediction method based on feature selection and deep learning | |
| CN110674326A (en) | Neural network structure retrieval method based on polynomial distribution learning | |
| CN115017850A (en) | Digital integrated circuit optimization method | |
| CN112464611A (en) | Automatic PCB wiring system based on cloud-end collaborative intelligent processing | |
| CN104486222B (en) | Small time delay defect test critical path system of selection based on ant colony optimization algorithm | |
| CN115660135A (en) | Traffic flow prediction method and system based on Bayes method and graph convolution | |
| CN104156462A (en) | Complex network community mining method based on cellular automatic learning machine | |
| CN115797732B (en) | Image retrieval model training method and system for open class scene | |
| CN109740221B (en) | Intelligent industrial design algorithm based on search tree | |
| CN116129648A (en) | Road network congestion key node identification method, equipment and medium | |
| US20220391566A1 (en) | Machine learning models for predicting detailed routing topology and track usage for accurate resistance and capacitance estimation for electronic circuit designs | |
| CN115270686A (en) | Chip layout method based on graph neural network | |
| CN114707460A (en) | Optimal method for layout planning area based on neural network and sequence pair | |
| CN114254199A (en) | Course recommendation method based on bipartite graph projection and node2vec | |
| CN114566048A (en) | Traffic control method based on multi-view self-adaptive space-time diagram network | |
| CN117709258B (en) | Path time sequence prediction method based on graph neural network | |
| CN114398823A (en) | Method for predicting circuit congestion degree by using complex network and machine learning |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |