CN116861782A - Line delay prediction method based on machine learning and node effective capacitance - Google Patents
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Abstract
The invention discloses a line delay prediction method based on machine learning and node effective capacitance, belonging to the technical field of calculation, calculation or counting. The method comprises the following steps: reading in a SPEF parasitic file, a netlist file and a time sequence library file; SPICE simulation is adopted to measure the node line delay of the sink end, and a line delay standard sample set is established; processing the SPEF parasitic file and the netlist file, and calculating the node line delay and conversion time of the sink end and the effective capacitance of all nodes; and processing to obtain the characteristics required by machine learning model training, using a cross-validation training model, calculating a node line delay average value of a receiving end and a conversion time average value as evaluation indexes of model performance, comparing errors between the node line delay calculated value of the receiving end and the line delay measured by SPICE simulation, and finally determining a characteristic parameter unified value. The method can rapidly and accurately predict the unit delay, and further improve the prediction speed and the prediction precision by optimizing the prediction result through machine learning.
Description
Technical Field
The invention relates to an integrated circuit design technology, in particular to a line delay prediction technology, discloses a line delay prediction method based on machine learning and node effective capacitance, and belongs to the technical field of calculation, calculation or counting.
Background field
In physical design, network topology typically varies among iterations, and timing optimization also requires multiple iterations to achieve timing convergence. With the continued advancement of process technology, the wiring delays are increasingly heavier in duty cycle throughout the timing sequence, resulting in longer and more frequent iterations of the design process. Achieving timing closure typically requires multiple analyses, optimizations, and verifications, and is therefore a difficult and time-consuming process. In order to speed up timing closure, faster, more accurate static timing analysis techniques are needed.
Delay calculations are typically performed in stages, the delay of the computation unit and interconnect, and the transition time. Currently, nonlinear delay models and current source models are widely used for cell timing modeling. However, these models cannot be used directly when the load at the output includes interconnect resistance. Thus, the "effective capacitance" approach is employed to address the effects of interconnect resistance. The effective capacitance method attempts to find a capacitance that can be used as an equivalent load to ensure that the original design is similar in timing at the cell output to a design with an equivalent capacitive load, referred to as an "effective capacitance", which is a function of the input impedance of the drive cell and its load. Cell delay and transition time can be easily calculated by using a look-up table comprising effective capacitances in the cell library.
In the field of online delay computation, past studies have used simple but computationally efficient lumped RC delay models or Elmore delay models to calculate interconnect delays quickly, or delay metrics based on higher order moments to provide higher accuracy, elmore delay models consider the first moment of the impulse response, while other higher order methods such as AWE, arnoldi, etc. can match the higher order response moments. The accuracy of the interconnect delay calculation can be improved by higher order estimation, but the calculation amount is too large for the comprehensive application in layout driving, and the use of only the closed approximation method is insufficient for timing estimation. Studies have shown that when a network has many branches, the metrics of Elmore, D2M, etc. differ from SPICE simulation results.
Disclosure of Invention
The invention aims to overcome the defects of the background technology, provide a line delay prediction method based on machine learning and node effective capacitance, realize the aim of rapidly and accurately predicting the interconnection line delay, and solve the technical problems that the calculation precision and calculation speed of the existing line delay prediction technology are to be improved.
The invention adopts the following technical scheme for realizing the purposes of the invention:
a line delay prediction method based on machine learning and node effective capacitance comprises the following steps:
step 1, reading a SPEF parasitic file, a netlist file and a time sequence library file;
step 2, adopting SPICE simulation to measure the node line delay of the receiving end, and establishing a line delay standard sample set;
step 3, calculating the line delay of the receiving end node, the conversion time of the receiving end node and the effective capacitance of all nodes according to the SPEF parasitic file and the netlist file read in the step 1 and combining the time sequence library file;
and 4, inputting the conversion time of the driving unit, the number of nodes from the source end to the receiving end of the RC network, the effective capacitance of all the nodes on the path from the source end to the receiving end of the RC network, the line delay of the receiving end nodes calculated in the step 3 and the conversion time of the receiving end nodes into characteristic data, taking the number of the nodes on the path from the source end to the receiving end of the RC network as characteristic parameters, and training a machine learning model according to the characteristic data and the line delay standard sample set.
As a further optimization scheme of the line delay prediction method based on machine learning and node effective capacitance, the SPEF parasitic file includes: SPEF winding name, network node name, node coupling capacitance value, winding total capacitance value and node resistance value; the netlist file includes: pin information, transition time.
As a still further optimization scheme of the line delay prediction method based on machine learning and node effective capacitance, the specific method for calculating the line delay of the receiving end node, the conversion time of the receiving end node and the effective capacitance of all nodes in step 3 is as follows:
step 3-1, when the SPEF wire winding is a tree-type RC network, turning to step 3-2; when the SPEF winding is a non-tree type RC network, converting the SPEF winding into a tree type RC network, and then converting into the step 3-2;
step 3-2, initializing the conversion time of the source end node and the effective capacitance of each node;
step 3-3, forward propagation conversion time from the source end node, calculating delay from the source end node to each node of the tree RC network, and obtaining conversion time of each node;
step 3-4, the fan-out node resistance shielding effect is considered, the effective capacitance is reversely propagated from the receiving end node to the source end node, and the effective capacitance of each node is updated;
and step 3-5, acquiring a source node conversion time update value according to the source node effective capacitor updated in the step 3-4, returning to the step 3-3 when the source node conversion time update value is not converged, and ending the step 3 when the source node conversion time update value is converged.
As a still further optimization scheme of the line delay prediction method based on machine learning and node effective capacitance, in the step 3-2, the method for initializing the conversion time of the source end node is as follows: inquiring source node effective capacitance and/or source node conversion time corresponding to the driving unit input conversion time in a time sequence library file; the method for initializing the effective capacitance of each node comprises the following steps: the downstream total capacitance of each node is taken as the initial value of the effective capacitance of each node.
As a still further optimization scheme of the line delay prediction method based on machine learning and node effective capacitance, step 3-3 calculates the distance from the source node to the treeThe expression of the delay of each node of the RC network is as follows: t (T) 0-i ＝∑ all node i R i-1→i C eff i Wherein T is 0-i R is the delay from the source end node to the ith node i-1→i C is the resistance between the i-1 th node and the i-th node eff i Is the effective capacitance of the i-th node.
As a still further optimization scheme of the line delay prediction method based on machine learning and node effective capacitance, the expression of the conversion time of each node obtained in step 3-3 is as follows:wherein S is i For the transition time of the ith node, S i-1 For the transition time of the i-1 th node, C i Is the ground capacitance of the i-th node.
As a still further optimization scheme of the line delay prediction method based on machine learning and node effective capacitance, the expression of updating the effective capacitance of each node in step 3-4 is as follows: wherein R is i→i+k C is the resistance between the ith node and the kth fan-out node of the ith node effi+k The effective capacitance of the kth fan-out node, C, for the ith node total i+k Is the total capacitance downstream of the kth fan-out node of the ith node.
As a still further optimization scheme of the line delay prediction method based on machine learning and node effective capacitance, the specific method for training the machine learning model according to the characteristic data and the line delay standard sample set in the step 4 is as follows: and constructing a data set according to the characteristic data obtained by RC network models of different SPEF windings, dividing the data set into a training set and a verification set, performing cross verification by utilizing the training set and the verification set, adjusting characteristic parameter values in each round of cross verification, predicting the line delay of a receiving end node and the conversion time of the receiving end node, taking the characteristic parameter value when the error of the predicted value of the line delay of the receiving end node and the measured value of the line delay SPICE simulation of the receiving end node is minimum as the characteristic parameter unified value of the machine learning model, and taking the average value of the line delay of the receiving end node and the average value of the conversion time of the receiving end node predicted by each round of cross verification as the evaluation index of the machine learning model.
An electronic device comprising a memory and a processor, the memory storing a computer program running on the processor, the processor executing the steps of the line delay prediction method described above when running the computer program.
A computer readable storage medium having stored thereon a computer program which, when run, performs the steps of the line delay prediction method described above.
The invention has the following beneficial effects for realizing the technical scheme:
(1) According to the invention, the influence of the input conversion time and the resistance shielding effect is fully considered, and the effective capacitance of all nodes of the RC network model of the SPEF file is obtained through an iterative calculation mode of back propagation of the effective capacitance after forward propagation of the conversion time.
(2) According to the invention, characteristic data are extracted by calculating the node line delay of the receiving end, the node switching time of the receiving end and the capacitance of all nodes of different SPEF file RC network models under different driving signals, the node line delay of the receiving end calculated by an iterative algorithm is associated with SPICE simulation data, a machine learning model is trained according to the characteristic data, the influence of input switching time and resistance shielding effect on the effective capacitance of the nodes can be considered, the topological structure characteristics of a circuit can be captured, the calculation precision of the line delay is further enhanced, and compared with the existing line delay prediction model, the line delay prediction method has the technical advantages of low modeling cost, lower complexity, high calculation speed and high calculation precision.
Drawings
FIG. 1 is a flow chart of the invention for predicting line delay.
FIG. 2 is a flow chart of the present invention processing a SPEF file.
FIG. 3 is a circuit topology of a SPEF wrap processed in an embodiment of the present invention.
FIG. 4 is a schematic diagram of a single pi-model slew propagation process.
Detailed Description
The technical scheme of the invention is described in detail below with reference to the accompanying drawings.
The disclosed machine learning and node effective capacitance based line delay prediction method of the present invention will be described in detail with reference to fig. 1.
Firstly, in step S1, a parasitic file, a netlist file, and a timing library file in a (Standard Parasitic Extraction Format, SPEF) parasitic parameter standard extraction format are read; the SPEF parasitic file information comprises a winding name, a network node name, a node coupling capacitance value, a winding total capacitance value and a node resistance value; the netlist file information includes pins, slew time, or slew.
In step S2, SPICE simulation is adopted to measure the node line delay of the sink end, and a line delay standard sample set is established; SPICE simulation measures sink end node line delay, which refers to delay from the RC network source to each receiving end, sink end node.
In step S3, the SPEF parasitic file and the netlist file are processed, the sink node line delay, the sink node slew and the effective capacitances of all nodes are calculated by combining the timing sequence library file, and the process of calculating the sink node line delay, the sink node slew and the effective capacitances of all nodes in this step will be described in detail by taking the SPEF winding shown in fig. 3 as an example with reference to the SPEF file processing flow shown in fig. 2, specifically including S3-1 to S3-5.
S3-1: judging whether the SPEF winding is a tree-type RC network or not, and if so, processing the SPEF winding into the tree-type RC network.
S3-2: initializing each Node i Is effective in terms of the effective capacitance Ceff of (2) i Node with source end Node 0 Is S of SLew 0 . Each Node i Initial effective capacitance Ceff of (c) i For the total capacitance Cto downstream of each nodetal i The method comprises the steps of carrying out a first treatment on the surface of the RC network source Node 0 Is S of SLew 0 Effective capacitance Ceff from source node 0 Input of slewS with driving unit in Determining, by looking up the source node effective capacitance Ceff in the driving unit timing table in the timing library file 0 And/or the drive unit inputs the switching time S in In the (a) way, a source Node of the RC network is obtained 0 Is of slewS of (1) 0 。
S3-3: as shown in fig. 3, the slew is propagated from the source node forward to the sink node, and the delay from the source node to each node of the tree RC network is calculated by equation (1):
T 0-i ＝∑ all node i R i-1→i C eff i (1)
in the formula (1), T 0-i From the source Node to the ith Node i R is the delay of (1) i-1→i For the i-1 Node i-1 Node with i Node i Resistance between C eff i For the ith Node i Is effective in capacitance.
Calculate each Node by equation (2) i S of (2) i ，S i By the last Node i-1 Propagation S i-1 Obtained. For each pi-model consisting of two nodes and a resistor between them, the propagation process taking the shielding effect of the resistor into account is shown in fig. 4, and the tree-shaped SPEF windings are equivalent to a combination of several pi-models.
In the formula (2), S i For the ith Node i Is S i-1 For the i-1 Node i-1 Is (1) slew, R i-1→i For Node i-1 And Node i Resistance between C i For the ith Node i Is connected to the ground.
S3-4: as shown in FIG. 3, back-propagating from sink end to source end Node, updating each Node i Is effective in terms of the effective capacitance Ceff of (2) i 。
In the formula (3), C i For the ith Node i Is the (i) th Node i Totally K fan-out nodes Node i+1 ～Node i+K ，R i→i+k For the ith Node i Kth fan-out Node with ith Node i+k Resistance between C effi+k The kth fan-out Node being the ith Node i+k Is effective in capacitance S i For the ith Node i Slow, C total i+k The kth fan-out Node being the ith Node i+k Downstream total capacitance of (c). Node for the ith Node i C of (2) effi In other words, considering the resistance mask coefficients of all the fan-out nodes of the ith node, the resistance mask coefficient of the kth fan-out node of the ith node, i.e., the (i+k) th node, depends on R i→i+k 、C effi+k 、S i Calculated ith Node i Effective capacitance C effi Mask fan-out Node i+k Downstream total capacitance C of (2) total i+k 。
S3-5, updating the source end node effective capacitance Ceff according to the step 3-4 0 Table look-up source Node 0 Is of the transition time S of (2) 0 . Judgment S 0 Whether or not to converge, if S 0 Returning to S3-3 to iteratively calculate sink end node line delay, sink end node slew and all node effective capacitances again if S 0 And (3) convergence, and ending S3.
In step S4, processing obtains feature data required for training the machine learning model XGBoost, where the feature data includes: the driving unit inputs the transition time slew S in The method comprises the steps of determining the number of nodes from a source end to a sink end of an RC network, effective capacitances of all nodes on a path from the source end to the sink end of the RC network, and calculating the delay of the node line of the sink end and the conversion time slew of the node line of the sink end by an iterative algorithm. In this embodiment, 100 ten thousand SP groups are processedAnd training the machine learning model by using the characteristic data obtained by EF winding as a data set and using a cross validation method, dividing the data set into 5 subsets, sequentially selecting one subset as a validation set, taking the rest subsets as training sets, repeating training and validation for 5 times, and finally calculating the average value of the delay of a sink end node line and the average value of the conversion time of the sink end node as evaluation indexes of the model performance. Because the number of nodes on paths from a source end to a sink end of different RC networks is different, the effective capacitance number of the RC networks is also different, and therefore, the characteristic parameters need to be repeatedly optimized and adjusted in the process of training a model to determine the number of characteristic data, and the method comprises the following steps: when the feature engineering is carried out, the size of the feature data is required to be unified, and the number of nodes on a path from a source end to a sink end of the RC network is selected as a feature parameter: for RC networks with the number of nodes larger than the unified value of the characteristic parameters, only the number of the required nodes from the source end is needed to be selected; for RC networks where the number of nodes is less than the unified value of the characteristic parameter, then a padding of 0 is required. In order to build a machine learning model of the predicted line delay, we gradually increase the number of nodes on the path from the source end to the sink end of the RC network, from the minimum number of nodes to the maximum number of nodes, in each round of cross verification, compare the errors between the predicted value of the line delay of the sink node in the verification set and the SPICE simulation measured value in the line delay standard sample set, and select the node number when the predicted line delay of the sink node in the verification set and the SPICE simulation measured delay error of the sink node in the verification set are minimum as the unified value of the special parameters.
In one embodiment of the present invention, there is also provided an electronic device including a memory and a processor, the memory storing a computer program running on the processor, the processor executing the steps of the line delay prediction method as described above when running the computer program.
In one embodiment of the present invention, there is also provided a computer readable storage medium having stored thereon a computer program which, when run, performs the steps of the line delay prediction method as described above.
The above specific embodiments and examples are specific support for the technical idea proposed by the present invention, and the scope of protection of the present invention is not limited thereby, and any equivalent changes or equivalent modifications made on the basis of the technical scheme according to the technical idea proposed by the present invention still belong to the scope of protection of the technical scheme of the present invention.
Claims (10)
1. The line delay prediction method based on machine learning and node effective capacitance is characterized by comprising the following steps of:
step 1, reading a SPEF parasitic file, a netlist file and a time sequence library file;
step 2, adopting SPICE simulation to measure the node line delay of the receiving end, and establishing a line delay standard sample set;
step 3, calculating the line delay of the receiving end node, the conversion time of the receiving end node and the effective capacitance of all nodes according to the SPEF parasitic file and the netlist file read in the step 1 and combining the time sequence library file;
and 4, inputting the conversion time of the driving unit, the number of nodes from the source end to the receiving end of the RC network, the effective capacitance of all the nodes on the path from the source end to the receiving end of the RC network, the line delay of the receiving end nodes calculated in the step 3 and the conversion time of the receiving end nodes as characteristic data, taking the number of the nodes on the path from the source end to the receiving end of the RC network as characteristic parameters, and training a machine learning model according to the characteristic data and the line delay standard sample set.
2. The machine learning and node effective capacitance based line delay prediction method of claim 1, wherein the SPEF parasitic file comprises: SPEF winding name, network node name, node coupling capacitance value, winding total capacitance value and node resistance value; the netlist file includes: pin information, transition time.
3. The method for predicting line delay based on machine learning and node effective capacitance according to claim 2, wherein the specific method for calculating the line delay of the receiving end node, the conversion time of the receiving end node and the node effective capacitance in step 3 is as follows:
step 3-1, when the SPEF wire winding is a tree-type RC network, turning to step 3-2; when the SPEF winding is a non-tree type RC network, converting the SPEF winding into a tree type RC network, and then converting into the step 3-2;
step 3-2, initializing the conversion time of the source end node and the effective capacitance of each node;
step 3-3, forward propagation conversion time from the source end node, calculating delay from the source end node to each node of the tree RC network, and obtaining conversion time of each node;
step 3-4, the fan-out node resistance shielding effect is considered, the effective capacitance is reversely propagated from the receiving end node to the source end node, and the effective capacitance of each node is updated;
and step 3-5, acquiring a source node conversion time update value according to the source node effective capacitor updated in the step 3-4, returning to the step 3-3 when the source node conversion time update value is not converged, and ending the step 3 when the source node conversion time update value is converged.
4. The method for predicting line delay based on machine learning and node effective capacitance according to claim 3, wherein in the step 3-2, the method for initializing the transition time of the source node is as follows: inquiring source node effective capacitance and/or source node conversion time corresponding to the driving unit input conversion time in the time sequence library file; the method for initializing the effective capacitance of each node comprises the following steps: the downstream total capacitance of each node is taken as the initial value of the effective capacitance of each node.
5. The method for predicting line delay based on machine learning and node effective capacitance of claim 4, wherein the expression of calculating the delay from the source node to each node of the tree RC network in step 3-3 is: t (T) 0-i ＝∑ allnodei R i-1→i C effi Wherein T is 0-i R is the delay from the source end node to the ith node i-1→i C is the resistance between the i-1 th node and the i-th node effi Is the effective capacitance of the i-th node.
6. The method for predicting line delay based on machine learning and node effective capacitance as claimed in claim 5, wherein the step 3-3 obtains the expression of the transition time of each node as follows:wherein S is i For the transition time of the ith node, S i-1 For the transition time of the i-1 th node, C i Is the ground capacitance of the i-th node.
7. The method for predicting line delay based on machine learning and node effective capacitance of claim 6, wherein the updating the expression of the effective capacitance of each node in step 3-4 is: wherein R is i→i+k C is the resistance between the ith node and the kth fan-out node of the ith node effi+k The effective capacitance of the kth fan-out node, C, for the ith node totali+k Is the total capacitance downstream of the kth fan-out node of the ith node.
8. The method for predicting line delay based on machine learning and node effective capacitance according to claim 7, wherein the specific method for training the machine learning model according to the feature data and the line delay standard sample set in step 4 is as follows: and constructing a data set according to the characteristic data obtained by RC network models of different SPEF windings, dividing the data set into a training set and a verification set, performing cross verification by utilizing the training set and the verification set, adjusting characteristic parameter values in each round of cross verification, predicting the line delay of a receiving end node and the conversion time of the receiving end node, taking the characteristic parameter value when the error of the predicted value of the line delay of the receiving end node and the measured value of the line delay SPICE simulation of the receiving end node is minimum as a characteristic parameter unified value of a machine learning model, and taking the average value of the line delay of the receiving end node and the average value of the conversion time of the receiving end node predicted by each round of cross verification as an evaluation index of the machine learning model.
9. An electronic device comprising a memory and a processor, the memory having stored thereon a computer program running on the processor, the processor executing the steps of the line delay prediction method of claim 1 when the computer program is run.
10. A computer readable storage medium having stored thereon a computer program which when run performs the steps of the line delay prediction method of claim 1.
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| CN1776698A (en) * | 2005-11-29 | 2006-05-24 | 知亿科技股份有限公司 | Circuit design assisting method |
| US20220391566A1 (en) * | 2021-06-07 | 2022-12-08 | Synopsys, Inc. | Machine learning models for predicting detailed routing topology and track usage for accurate resistance and capacitance estimation for electronic circuit designs |
| CN115130425A (en) * | 2022-05-31 | 2022-09-30 | 东南大学 | Time sequence modeling method for near-threshold clock tree |
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