CN114003450B - Test fixture, test method and computer equipment for automatically switching PCIE links - Google Patents
Test fixture, test method and computer equipment for automatically switching PCIE links Download PDFInfo
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- 238000012360 testing method Methods 0.000 title claims abstract description 158
- 238000010998 test method Methods 0.000 title claims abstract description 16
- 238000004891 communication Methods 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims description 11
- 238000004590 computer program Methods 0.000 claims description 9
- 230000003993 interaction Effects 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract 1
- 238000001816 cooling Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- NBLBCGUCPBXKOV-UHFFFAOYSA-N 8-(methoxymethyl)-1-methyl-3-(2-methylpropyl)-7H-purine-2,6-dione Chemical compound CC(C)CN1C(=O)N(C)C(=O)C2=C1N=C(COC)N2 NBLBCGUCPBXKOV-UHFFFAOYSA-N 0.000 description 3
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- 230000008054 signal transmission Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2247—Verification or detection of system hardware configuration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2289—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by configuration test
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application relates to a test fixture, a test method and computer equipment for automatically switching PCIE links. The test fixture comprises an FPGA logic controller and a dial switch, wherein the dial switch is connected with the FPGA logic controller in serial communication; the clock controller is connected with the FPGA logic controller in serial communication and is used for driving the PCIE link to finish rate switching and rate configuration; and the BMC management controller is in communication connection with the FPGA logic controller through real-time information interaction. Through above-mentioned scheme, this application has cost, easy and simple to handle, degree of automation is high beneficial effect.
Description
Technical Field
The present disclosure relates to the field of signal transmission technologies, and in particular, to a test fixture, a test method, and a computer device for automatically switching PCIE links.
Background
With the development of high-speed links, the development of artificial intelligence and other technologies in recent years also puts higher demands on computational power, and various xPU appears to put higher demands on the system interconnection technology. In particular, the development of PCIE signals has gradually progressed from PCIE1.0 to PCIE5.0, and pcie_tx consistency tests involving daughter cards have become more complex and stringent, where PCIE1.0 employs De-emphasis of-3.5 db, PCIE2.0 employs De-emphasis (De-phase) techniques of-3.5 db and-6 db, and the preset of PCIE3.0 has 11 configurations (preset 0-preset 10), while the preset of PCIE4.0 still has 11 configurations, and if preset7 of PCIE4.0 is to be tested, in a test fixture conventionally employing CBB, research and development testers need to manually switch for at least 21 times to enter preset7 of PCIE 4.0. Rate switching for PCIE5.0 is identical to PCIE4.0, and 11 preset are also involved.
In the prior art, an X8 daughter card link is taken as an example, if pcie_tx consistency is to be tested for full coverage, at least 32 differential connection ports and 2 clock connection ports are required for SMP/MMPX connectors, and the individual SMP/MMPX connectors are expensive, which leads to a drastic increase in the manufacturing cost of the test fixture. In addition, in the process of arbitrarily switching links, the service life of the SMP/MMPX connector is greatly shortened due to the fact that the connecting ports are required to be repeatedly plugged.
Therefore, a test fixture and a test method for solving the problems of high manufacturing cost and complex operation of TX consistency of PCIE links in the prior art are urgently needed.
Disclosure of Invention
Accordingly, it is desirable to provide a test fixture, a test method and a computer device for automatically switching PCIE links, which can reduce the manufacturing cost and simplify the operation.
In one aspect, a test fixture for automatically switching PCIE links is provided, including an FPGA logic controller; the test fixture further comprises: the dial switch is connected with the FPGA logic controller in serial communication; the clock controller is connected with the FPGA logic controller in serial communication and is used for driving the PCIE to finish rate switching and rate configuration; and the BMC management controller is in communication connection with the FPGA logic controller through real-time information interaction.
In one embodiment, the clock controller comprises a first clock controller and a second clock controller; the second clock controller is connected with the FPGA logic controller in serial communication so that the FPGA logic controller can perform rate switching; and the first clock controller is connected with the FPGA logic controller in serial communication, and is started when the second clock controller cannot perform rate switching.
In one embodiment, the dial switch is a ten-bit dial switch; wherein: the first three-bit coding value of the dial switch represents PCIE link information; the fourth bit to sixth bit coding value of the dial switch represents PCIE link test rate; and the seventh bit to tenth bit coding values of the dial switch represent PCIE link test rate configuration parameters.
In one embodiment, the test fixture further includes an LED ticker connected in serial communication with the FPGA logic controller for displaying PCIE link test status.
In one embodiment, the test fixture further comprises: temperature sensor: the temperature sensor is electrically connected with the BMC management controller and used for acquiring the test environment temperature and transmitting the environment temperature to the BMC management controller; cooling fan: the cooling fan is electrically connected with the BMC management controller, and when the ambient temperature is higher than a threshold value, the BMC management controller starts the cooling fan.
On the other hand, a test method for automatically switching PCIE links is provided, and a test fixture based on the automatically switching PCIE links is realized, wherein the test method specifically comprises the following steps: step S01, receiving PCIE link test parameters sent by the dial switch through the FPGA logic controller; step S02, the FPGA logic controller converts the acquired PCIE link test parameters into PCIE link test signals which can be identified by PCIE links; step S03, PCIE link test is performed based on the PCIE link test signal, a PCIE link test result is obtained, and whether the PCIE link test result meets the preset PCIE link test requirement is determined.
In one embodiment, the PCIE link test parameters include: and testing PCIE link information, PCIE link test rate and PCIE link test rate configuration information.
In one embodiment, the step S02 includes: the FPGA logic controller configures control pin parameters according to the test PCIE link information; sending out a pulse trigger signal through a preset second clock controller to obtain the PCIE link test rate; based on the PCIE link test rate, obtaining PCIE link test rate configuration information corresponding to the PCIE link test rate.
In one embodiment, the performing PCIE link test based on PCIE link test signals includes the following steps: step S031, firstly, determining PCIE links to be tested based on read test PCIE link information; step S032, judging whether PCIE link test rate configuration information needs to be read or not based on PCIE link test rate; step S033, if it is determined that the PCIE link test rate configuration information needs to be read, configuring, by a preset second clock controller, the PCIE link test rate based on the PCIE link test rate configuration information.
In yet another aspect, a computer device is provided, including a memory, a processor, and a computer program stored on the memory and capable of running on the processor, wherein the processor implements the steps of a test method for automatically switching PCIE links when the processor executes the computer program.
According to the test fixture, the test method and the computer equipment for automatically switching the PCIE link, the dial switch is connected with the FPGA logic controller in a serial communication mode, so that the PCIE link is tested by changing the code of the dial switch; the clock controller is connected with the FPGA logic controller in a serial communication manner so as to drive the PCIE to finish rate switching and rate configuration without using a large number of specific connectors to perform PCIE link tests, and in the test process, the connectors are not required to be repeatedly plugged and unplugged, so that automatic switching of PCIE test links can be realized, the manufacturing cost of the whole test fixture is reduced, the service life of the test fixture is prolonged, and excessive manpower resources are not required to be consumed; the BMC management controller and the FPGA logic controller are connected through real-time information interaction communication, so that the FPGA logic controller and the BMC management controller can be mutually supervised, faults of the test fixture in the PCIE link test process are prevented, and PCIE link test operation can be smoothly performed. In summary, the test fixture and the test method for automatically switching PCIE links have the advantages of being low in manufacturing cost, simple and convenient to operate and high in automation degree.
Drawings
Fig. 1 is a test environment diagram of a test method for automatically switching PCIE links in one embodiment;
fig. 2 is a test flow diagram of automatically switching PCIE links in one embodiment;
fig. 3 is a schematic diagram of a test fixture for automatically switching PCIE links in one embodiment;
fig. 4 is a flowchart of a test method for switching PCIE links in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
The application provides a test fixture for automatically switching PCIE links, as shown in FIG. 2, comprising an FPGA logic controller.
In a specific embodiment, the test fixture further comprises: the dial switch is connected with the FPGA logic controller in serial communication; the clock controller is connected with the FPGA logic controller in serial communication and is used for driving the PCIE link to finish rate switching and rate configuration; and the BMC management controller is in communication connection with the FPGA logic controller through real-time information interaction.
In a specific embodiment, the dial switch is a ten-bit dial switch; wherein: the first 3-bit coding value of the dial switch represents PCIE link information; the fourth bit to sixth bit coding value of the dial switch represents PCIE link test rate; the seventh to tenth coded values of the dial switch represent equalized signal quality, and in particular, the specific definition of the coded values of the coded bits of the ten-bit dial switch is shown in the following table. It should be understood that the number of coding bits of the dial switch is not limited, and those skilled in the art may select an appropriate dial switch according to actual situations, so as to implement testing of the PCIE link that is automatically switched.
TABLE 1
| Coded value K0K1K2 of dial switch | PCIE link information |
| 000 | PCIE_lane0 |
| 001 | PCIE_lane1 |
| 010 | PCIE_lane2 |
| 011 | PCIE_lane3 |
| 100 | PCIE_lane4 |
| 101 | PCIE_lane5 |
| 110 | PCIE_lane6 |
| 111 | PCIE_lane7 |
TABLE 2
| Coded value K3K4K5 of dial switch | PCIE protocol version |
| 000 | Gen1 |
| 001 | Gen2_3.5dB |
| 011 | Gen2_6dB |
| 100 | Gen3 |
| 101 | Gen4 |
| 110 | Gen5 |
| 111 | Automatic switching cannot be performed |
TABLE 3 Table 3
| Coded value K3K4K5 of dial switch | PCIE link rate configuration |
| 0000 | Preset0 |
| 0001 | Preset1 |
| 0011 | Preset2 |
| 0100 | Preset3 |
| 0101 | Preset4 |
| 0110 | Preset5 |
| 0111 | Preset6 |
| 1000 | Preset7 |
| 1001 | Preset8 |
| 1011 | Preset9 |
| 1100 | Preset10 |
| 1111 | Failure to automatically perform rate configuration |
TABLE 4 Table 4
| FPGA logic controller control pins G1-G14 | Signal trend |
| G1G2G4＝000 | lane0_TX0 |
| G1G2G5＝000 | lane1_TX1 |
| G1G3G6＝000 | lane2_TX2 |
| G1G3G7＝000 | lane3_TX3 |
| G8G9G11＝000 | lane4_TX4 |
| G8G9G12＝000 | lane5_TX5 |
| G8G10G13＝000 | lane6_TX6 |
| G8G10G14＝000 | lane7_TX7 |
In this embodiment, the clock controller includes a first clock controller and a second clock controller;
the second clock controller is connected with the FPGA logic controller in serial communication so that the FPGA logic controller can perform rate switching and rate configuration;
and the first clock controller is connected with the FPGA logic controller in serial communication, and when the second clock controller cannot automatically perform rate switching, the first clock controller is started. Wherein: the first clock controller may also be referred to as a 100M CLK clock controller a and the second clock controller may also be referred to as a 100M CLK clock controller B, particularly as shown in fig. 1.
In this embodiment, the test fixture further includes an LED ticker connected in serial communication with the FPGA logic controller, so as to display a test rate switching result. When the test rate of the PCIE link is successfully switched, the LED ticker flashes corresponding light to remind the test rate state of the PCIE link. Or, a person skilled in the art can set different LED ticker lights corresponding to different PCIE link test rates, so that the test rate of the current PCIE link can be more intuitively displayed to the user.
In this embodiment, the test fixture further includes: temperature sensor: the temperature sensor is electrically connected with the BMC management controller and used for acquiring the test environment temperature and transmitting the environment temperature to the BMC management controller; cooling fan: the cooling fan is electrically connected with the BMC management controller, and when the ambient temperature is higher than a threshold value, the BMC management controller starts the cooling fan. The test environment is not burnt out due to the fact that the temperature of the test environment is too high in the test process. It should be understood that the specific value of the threshold is not limited, and those skilled in the art can set the threshold according to the temperature requirement of the test environment and the temperature resistance of each component in the test environment.
Example two
As shown in fig. 2, the test method for automatically switching PCIE links is implemented based on a test tool for automatically switching PCIE links, and is applied to a test environment of the test method for automatically switching PCIE links shown in fig. 1. The testing method specifically comprises the following steps: step S01, receiving PCIE link test parameters sent by the dial switch through the FPGA logic controller; step S02, the FPGA logic controller converts the acquired PCIE link test parameters into PCIE link test signals which can be identified by PCIE links; step S03, PCIE link test is performed based on the PCIE link test signal, a PCIE link test result is obtained, and whether the PCIE link test result meets the preset PCIE link test requirement is determined.
In this embodiment, the PCIE link test parameters include: and testing PCIE link information, PCIE link test rate and PCIE link test rate configuration information. Wherein: the PCIE link test information indicates which PCIE link is specifically tested in the PCIE link test process; PCIE link test rate indicates the rate of test signals passing through PCIE links, i.e., the version of PCIE signaling protocol, as shown in table 1, including Gen1 (PCIE 1.0), gen2_3.5dB (PCIE 1.0), gen2_6dB (PCIE 2.0), gen3 (PCIE 3.0), gen4 (PCIE 4.0), gen5 (PCIE 5.0); the PCIE link test rate configuration information is only the PCIE link test rate configuration information corresponding to any PCIE signal protocol when the PCIE link test rate, that is, the PCIE signal protocol version is Gen3 (PCIE 3.0), gen4 (PCIE 4.0), and Gen5 (PCIE 5.0).
In a specific embodiment, the dial switch based on the present embodiment is a ten-bit dial switch, the first three-bit code value of the dial switch, that is, K0K1K2, represents the tested PCIE link information, the fourth to sixth bit code values of the dial switch, that is, K3K4K5, represent the PCIE link testing rate, and the seventh to tenth bit code values of the dial switch, that is, K6K7K8K9, represent the tested PCIE link quality adjustment parameter. It should be understood that, a person skilled in the art may select an appropriate dial switch according to the actual situation of testing the PCIE link, and the meaning of the code values of different code bits related to the dial switch may also be reasonably selected according to the actual situation.
Specifically, the 7 th PCIE link, i.e., lane7, is tested for illustration. According to the information comparison table shown in table 1, when the first three digits of the code bits of the read dial switch are all 1, namely, k0k1k2=111, the FPGA logic controller obtains that the PCIE link to be detected is PCIE link 7; at this time, the FPGA logic controller converts the PCIE link test parameters into PCIE link test signals, that is, the bit signals of the CPLD control pins of the FPGA logic controller correspond to the values of the coded bits of the dial switch, and according to the information comparison table shown in table 4, the G8, G10, and G14 of the CPLD control pins of the FPGA logic controller are pulled up to be set to 1, and the other CPLD control pins are pulled down to be set to 0, so that the tested PCIE link is switched to be Lane7.
In a specific embodiment, as shown in fig. 3, when K3K4K5 and K6K7K8K9 are all pulled high to be set to 1, that is, it means that the PCIE link can be tested by manual control, and the LED ticker sends out an indication signal. If the PCIE link test is converted from the manual control test to the automatic switching PCI E link test, the specific steps of the FPGA logic controller re-reading the PCIE link test parameters include: the first clock controller replaces the second clock controller to run for a plurality of seconds; after a few seconds, the second clock controller pulses the PCIE link test rate so that the PCIE link test rate completes switching. Wherein: it should be understood that the first clock controller and the second clock controller described in this embodiment are collectively referred to as a 100M clock controller, i.e. the 100M clock controller shown in fig. two.
Example III
A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the following steps when executing the computer program:
step S01, receiving PCIE link test parameters sent by the dial switch through the FPGA logic controller; step S02, the FPGA logic controller converts the acquired PCIE link test parameters into PCIE link test signals which can be identified by PCIE links; step S03, PCIE link test is performed based on the PCIE link test signal, a PCIE link test result is obtained, and whether the PCIE link test result meets the preset PCIE link test requirement is determined. Wherein: the PCIE link test parameters comprise test PCIE link information, PCIE link test rate and PCIE link test rate configuration information.
In one embodiment, the processor when executing the computer program further performs the steps of:
the FPGA logic controller configures control pin parameters according to the test PCIE link information; sending out a pulse trigger signal through a preset second clock controller to obtain the PCIE link test rate; based on the PCIE link test rate, obtaining PCIE link test rate configuration information corresponding to the PCIE link test rate.
In one embodiment, the processor when executing the computer program further performs the steps of:
step S031, firstly, determining PCIE links to be tested based on read test PCIE link information; step S032, judging whether PCIE link test rate configuration information needs to be read or not based on PCIE link test rate; step S033, if it is determined that the PCIE link test rate configuration information needs to be read, configuring, by a preset second clock controller, the PCIE link test rate based on the PCIE link test rate configuration information.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the various embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (4)
1. The test method for automatically switching PCIE links is characterized in that the test jig based on the automatically switching PCIE links comprises an FPGA logic controller, a dial switch and a clock controller, wherein the dial switch is in serial communication connection with the FPGA logic controller, and the clock controller is in serial communication connection with the FPGA logic controller so as to drive the PCIE links to finish rate switching and rate configuration;
the clock controller comprises a first clock controller and a second clock controller; the second clock controller is connected with the FPGA logic controller in serial communication so that the FPGA logic controller can perform rate switching; the first clock controller is connected with the FPGA logic controller in serial communication, and when the second clock controller cannot automatically perform rate switching, the first clock controller is started;
the testing method specifically comprises the following steps:
step S01, receiving PCIE link test parameters sent by the dial switch through the FPGA logic controller;
step S02, the FPGA logic controller converts the acquired PCIE link test parameters into PCIE link test signals which can be identified by PCIE links;
the PCIE link testing parameters include PCIE link testing information, and step S02 includes:
the FPGA logic controller configures control pin parameters according to the test PCIE link information;
sending out a pulse trigger signal through a preset second clock controller to obtain the PCIE link test rate;
based on the PCIE link test rate, acquiring PCIE link test rate configuration information corresponding to the PCIE link test rate;
step S03, PCIE link test is performed based on the PCIE link test signal, a PCIE link test result is obtained, and whether the PCIE link test result meets the preset PCIE link test requirement is determined.
2. The method for testing automatically switching PCIE links according to claim 1, wherein said PCIE link testing parameters include: PCIE link test rate and PCIE link test rate configuration information.
3. The method for automatically switching PCIE links according to claim 1, wherein said PCIE link test based on PCIE link test signals comprises the steps of:
step S031, firstly, determining PCIE links to be tested based on read test PCIE link information;
step S032, judging whether PCIE link test rate configuration information needs to be read or not based on PCIE link test rate;
step S033, if it is determined that the PCIE link test rate configuration information needs to be read, configuring, by a preset second clock controller, the PCIE link test rate based on the PCIE link test rate configuration information.
4. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any one of claims 1 to 3 when the computer program is executed by the processor.
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