CN114002785A - CMOS compatible structure for reducing thermal crosstalk of silicon optical chip - Google Patents
CMOS compatible structure for reducing thermal crosstalk of silicon optical chip Download PDFInfo
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- CN114002785A CN114002785A CN202111202514.1A CN202111202514A CN114002785A CN 114002785 A CN114002785 A CN 114002785A CN 202111202514 A CN202111202514 A CN 202111202514A CN 114002785 A CN114002785 A CN 114002785A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 32
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 32
- 239000010703 silicon Substances 0.000 title claims abstract description 32
- 230000003287 optical effect Effects 0.000 title abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims description 8
- 238000005253 cladding Methods 0.000 claims description 5
- 239000007769 metal material Substances 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims 1
- 229910045601 alloy Inorganic materials 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 10
- 230000010354 integration Effects 0.000 abstract description 2
- 230000007935 neutral effect Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 54
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 33
- 235000012239 silicon dioxide Nutrition 0.000 description 16
- 239000000377 silicon dioxide Substances 0.000 description 16
- 238000005530 etching Methods 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000001259 photo etching Methods 0.000 description 8
- 238000009616 inductively coupled plasma Methods 0.000 description 6
- 238000011161 development Methods 0.000 description 5
- 238000004377 microelectronic Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 230000005693 optoelectronics Effects 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 239000011162 core material Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4266—Thermal aspects, temperature control or temperature monitoring
- G02B6/4273—Thermal aspects, temperature control or temperature monitoring with heat insulation means to thermally decouple or restrain the heat from spreading
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Optical Integrated Circuits (AREA)
Abstract
The invention discloses a CMOS compatible structure for reducing thermal crosstalk of a silicon optical chip, which is a double-layer cylindrical ring layer designed based on a neutral inclusion idea and comprises a metal cylindrical ring layer arranged on an outer layer and an air cylindrical ring layer arranged on an inner layer. The invention adopts isotropic and CMOS compatible materials, can reduce the thermal crosstalk between silicon optical chips under the CMOS standard process, protects temperature sensitive devices and provides feasibility for on-chip integration of a system.
Description
Technical Field
The invention belongs to the field of silicon-based optoelectronic integrated systems, and particularly relates to a CMOS compatible structure for reducing thermal crosstalk of a silicon optical chip.
Background
Microelectronics has been the driving force for the development of modern information society in recent years. However, the micro-scale cycle of the microelectronic chip is gradually slowed down due to the limitations of physical, technical and economic aspects, and moore's law is faced with failure. However, the demand of modern society for high-speed information processing is not reduced by the delay of microelectronic technology, and the information congestion problem becomes the most prominent contradiction.
Photons are used as carriers of information transfer, and compared with electrons, the photons have stable and controllable modulation and multiplexing dimensions such as amplitude, phase, wavelength, polarization state, mode and the like, and have larger bandwidth, higher spectrum utilization rate and higher communication capacity. Its advantages come from the organic combination of mature microelectronic technique and broad-band photoelectronic technique in the micro-nano range. Its applications also extend from primary microelectronics to communications, computing, sensing, artificial intelligence, and even consumer areas. In the modern information society based on big data, silicon-based optoelectronics has become the most potential solution on chip with high efficiency and low cost.
On a silicon-based optoelectronic chip, various photonic, electronic and optoelectronic devices required by information throughput can be integrated, including optical waveguides, modulators, detectors, transistor integrated circuits and the like. However, the thermo-optic coefficient of silicon is 1 order of magnitude greater than that of passive materials such as silicon nitride and silicon oxide (about 1.85 × 10 at room temperature)-4K-1). Environmental temperature changes and chip heat accumulation have obvious influence on the performance of the silicon-based photoelectric device, and the energy consumption of the chip is increased by temperature control. Reducing thermal cross-talk between silicon photonics has become a significant challenge.
Disclosure of Invention
The invention aims to provide a CMOS compatible structure for reducing the thermal crosstalk of a silicon optical chip, which does not add extra temperature control on the basis of design to reduce the thermal crosstalk.
In order to achieve the above design objective, the technical solution of the present invention is as follows:
a CMOS compatible structure for reducing the thermal crosstalk of a silicon optical chip comprises a metal cylindrical ring layer arranged on an outer layer and an air cylindrical ring layer arranged on an inner layer;
the material of the metal cylindrical ring layer can be a metal material included in a CMOS (complementary metal oxide semiconductor) process line of copper, aluminum, tungsten and the like.
Ideally the depth of the metal collar layer and the air collar layer is from the top of the cladding layer (cladding) to the BOX layer and silicon substrate (Si substrate) interface. The depth and size of the metal cylindrical ring layer and the air cylindrical ring layer can be adjusted according to the actual technological level.
The CMOS compatible structure for reducing the thermal crosstalk of the silicon optical chip is prepared by adopting isotropic and CMOS compatible materials, and the preparation process comprises the following steps: for the standard process of the Institute of Microelectronics, singapore (IME), 245nm deep uv light source was used, the wafer radius was 8 inches, the top silicon thickness was 220nm, the underlying silicon dioxide layer was 2 μm, and the standard line width of the process was a minimum of 200 μm.
(1) Passive three-time etching: firstly, cleaning a wafer, growing 75nm silicon dioxide on the wafer by using Chemical Vapor Deposition (PECVD), then spin-coating Photoresist (PR) on the silicon dioxide, and transferring the pattern of a photomask onto the silicon dioxide by etching after photoetching development, wherein the part of the silicon dioxide is used as a hard mask (the photoresist is not removed after each etching) for subsequent silicon etching. After the photoresist is removed, an Inductively coupled Plasma etcher (ICP) is used to Etch the part of the grating downwards by 70nm, so as to complete the etching of the vertical coupling grating. And then spin-coating the photoresist again, selectively reserving a part of photoresist above the vertical coupling grating by photoetching and developing, and then etching downwards for 90nm by utilizing ICP (inductively coupled plasma), thus finishing the etching of the ridge waveguide. And finally, spin-coating a photoresist, selectively reserving a part of the photoresist above the vertical coupling grating and the ridge waveguide by photoetching and developing, and then etching downwards by 60nm by utilizing ICP (inductively coupled plasma), thus finishing the etching of the last step, namely the strip waveguide.
(2) Preparation of Heater layer and lead layer: removing the previous photoresist, growing a 600nm thick silicon dioxide layer on the surface, using Chemical Mechanical Planarization (CMP) to make the surface thickness consistent, carrying out photoetching development, forming a through hole (Via1 layer) from the surface to a silicon layer by etching the 600nm silicon dioxide, depositing 50nm thick TaN, 750nm thick Al, 50nm thick TaN and 50nm nitride respectively, carrying out photoetching development to generate a mask, and etching the metal layer on the surface to form a first layer of interconnection line (Matal 1 layer). And growing 1400nm silicon dioxide, 5nm titanium, 120nm titanium nitride and 60nm nitride by PECVD. Then, a mask is generated by photoetching and developing, and the metal layer on the surface is etched away, so that the heater of the titanium nitride can be obtained. Silicon dioxide with the thickness of 1 μm is grown again, then a mask is generated by photoetching and development, a through hole (Via2 layer) from the surface to a titanium nitride heater or a Matel 1 layer can be formed by etching, and TaN with the thickness of 25nm and Al with the thickness of 2000nm are grown by PECVD. Then developed and etched by photolithography to form Matel 2. Then growing a silicon dioxide layer, and then photoetching, developing and etching to Open a 'window' (Bond Open layer) so that a part of the Matel2 layer is exposed in the air to facilitate the lead.
The above is the etching process of the device, and the air cylinder ring layer of the structure of the present invention is formed by forming a deep trench (deep trench) after the above process is completed (the deep trench is located inside the metal cylinder ring layer, and needs to avoid the device, and the inside of the air cylinder ring layer is a structure that needs to reduce thermal crosstalk), and the metal cylinder ring layer is prepared according to the process conditions, for example, the metal cylinder ring layer can only be formed by splicing metal 1 and metal 2 in the IME. And most preferably directly to the silicon substrate layer (Si substrate) as the metal in the dashed box.
The invention has the beneficial effects that:
the CMOS compatible structure for reducing the thermal crosstalk of the silicon optical chip can effectively shield the thermal crosstalk generated by other active devices on the chip, and further ensure the working performance of the temperature-sensitive silicon optical device piece, such as a silicon optical filter. Rather than increasing the distance between the two in order to reduce the thermal crosstalk, the overall size is increased, which is not favorable for on-chip integration of the system; thermal crosstalk can be reduced under the condition of not adding temperature control, and energy consumption increase is effectively avoided. The structure of the invention, namely the thickness of the double-layer cylindrical ring layer can be very thin, and the structure is designed according to the size of the internal filter. In actual preparation, the thickness can be properly increased to meet the process level under the condition of keeping the working performance by considering the minimum size of the process.
Drawings
FIG. 1 is a CMOS compatible structure of the present invention for reducing thermal crosstalk in silicon photonics chips;
FIG. 2 is an SOI waveguide under standard processing;
FIG. 3 is a schematic IME process.
Detailed Description
Fig. 1 is a CMOS compatible structure of the present invention in xy view to reduce thermal crosstalk of a silicon optical chip: comprises a metal cylindrical ring layer arranged on an outer layer and an air cylindrical ring layer arranged on an inner layer;
FIG. 2 is a standard process SOI waveguide in xz view;
the material of the metal cylinder ring layer can be a metal material included in a CMOS process line such as copper, aluminum, tungsten and the like, and ideally, the depth of the metal cylinder ring layer and the air cylinder ring layer is from the top of a cladding layer (cladding) to the interface of a BOX layer and a silicon substrate (Si substrate). The depth and the size of the metal cylindrical ring layer and the air cylindrical ring layer can be adjusted according to the actual technological level;
the design of the structure based on the neutral inclusion thought:
the basic idea is as follows: when the equivalent parameter after inclusion is equal to the physical parameter of the background material, the physical field in the background material (the region outside the inclusion) is not disturbed.
Based on the above design concept, the volume fraction of the inclusion layer of the homogeneous isotropic material is:
wherein r is<r1The part of (a) is the cylindrical core layer, i.e. the region where the internal silicon optical chip is located, r2>r>r1Is a cylindrical ring layer of air, r3>r>r2Is a metal cylindrical ring layer. And the metal ring column layer and the air ring column layer are the inclusion layers. The equivalent thermal conductivity of the entire cylinder:
wherein, therein
Is the thermal conductivity, k, of the cylindrical core material (the region where the silicon optical filter is located)0Is the thermal conductivity, k, of the background material2Is the thermal conductivity of air, k3Is the thermal conductivity of the metal and L is the number of layers of inclusions. When there are two layers, L is 2, when
Get the target k0The designed structure is as follows:
and selecting appropriate materials under the CMOS standard process, and reasonably designing a structure by combining with the minimum size of the process. In a simple way, the thermal conductivity of air is only 0.0263W/mK, and the air cylindrical ring layer plays a good role in heat insulation. While the thermal conductivity of metals is relatively high, such as Cu having a thermal conductivity of about 400W/mK, which can direct heat into the underlying silicon substrate, silicon (Si) having a thermal conductivity of 148W/mK compared to silicon dioxide (SiO)2) The heat conductivity of the heat conducting pipe is 1.38W/mK, which is over a hundred times higher, and the heat can be well guided away. Conventional on-chip thermal isolation would use silicon dioxide (SiO) with a relatively low thermal conductivity2) To insulate, but this is a double-edged sword, silicon dioxide (SiO)2) The low thermal conductivity of (2) also limits the heat. The structure proposed by the present invention can compensate for this drawback.
Claims (2)
1. A CMOS compatible structure for reducing thermal crosstalk in silicon photonics chips, comprising: comprises a metal cylindrical ring layer (1) arranged on an outer layer and an air cylindrical ring layer (2) arranged on an inner layer;
the depth of the metal cylindrical ring layer (1) and the air cylindrical ring layer (2) is from the top of the cladding to the interface of the BOX layer and the silicon substrate.
2. The CMOS compatible structure for reducing thermal crosstalk in silicon photonics chips of claim 1 further comprising: the metal cylindrical ring layer (1) is made of metal materials or alloys contained in a CMOS process line.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111202514.1A CN114002785A (en) | 2021-10-15 | 2021-10-15 | CMOS compatible structure for reducing thermal crosstalk of silicon optical chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111202514.1A CN114002785A (en) | 2021-10-15 | 2021-10-15 | CMOS compatible structure for reducing thermal crosstalk of silicon optical chip |
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| CN114002785A true CN114002785A (en) | 2022-02-01 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110944501A (en) * | 2019-12-10 | 2020-03-31 | 哈尔滨工程大学 | Protection device applied to thermoelectric double fields |
| CN111263574A (en) * | 2020-03-19 | 2020-06-09 | 哈尔滨工程大学 | Thermoelectric protection device based on equivalent medium method and preparation method |
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- 2021-10-15 CN CN202111202514.1A patent/CN114002785A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110944501A (en) * | 2019-12-10 | 2020-03-31 | 哈尔滨工程大学 | Protection device applied to thermoelectric double fields |
| CN111263574A (en) * | 2020-03-19 | 2020-06-09 | 哈尔滨工程大学 | Thermoelectric protection device based on equivalent medium method and preparation method |
Non-Patent Citations (1)
| Title |
|---|
| 张兴伟: "《基于中性夹杂的热流传输路径调控》", 《中国优秀博硕士学位论文全文数据库(硕士)工程科技Ⅱ辑》 * |
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Application publication date: 20220201 |
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