CN113990936A - MOS (Metal oxide semiconductor) tube device based on different gate structures - Google Patents

MOS (Metal oxide semiconductor) tube device based on different gate structures Download PDF

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CN113990936A
CN113990936A CN202111587237.0A CN202111587237A CN113990936A CN 113990936 A CN113990936 A CN 113990936A CN 202111587237 A CN202111587237 A CN 202111587237A CN 113990936 A CN113990936 A CN 113990936A
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gate
dielectric layer
doped
gate dielectric
doping
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CN113990936B (en
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盛况
任娜
徐弘毅
王珩宇
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Hangzhou Xinzhu Semiconductor Co ltd
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ZJU Hangzhou Global Scientific and Technological Innovation Center
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Abstract

The application discloses MOS tube device based on different grid structures relates to semiconductor technology field, includes: a first doped substrate; the first doping structure is connected with the first doping substrate; the second doping structure is connected with the first doping structure; the trench gate structure is respectively connected with the first doping structure and the second doping structure; the trench gate structure comprises a gate and a gate dielectric layer, the gate dielectric layer is arranged at the bottom and the side wall of the gate, the gate dielectric layer is respectively connected with the first doping structure and the second doping structure, the gate is provided with a symmetrical or asymmetrical periodic arrangement structure, the trench gate structure has the advantages that on the premise that the cell size and the cell density are not changed, the area of a channel is obviously increased, the channel resistance of a device is effectively reduced, the phenomenon of channel non-uniform flow is avoided through different gate structures, and the FinFET effect can occur when the trench gate structure is reduced to be below 40nm, so that the resistance of the channel is further reduced.

Description

MOS (Metal oxide semiconductor) tube device based on different gate structures
Technical Field
The application belongs to the technical field of semiconductors, and more specifically relates to a MOS (metal oxide semiconductor) transistor device based on different gate structures.
Background
The performance of conventional silicon-based semiconductor devices has gradually approached the physical limit of materials, and third generation power semiconductor devices using silicon carbide materials have strong attraction in high power density and high efficiency devices due to their excellent characteristics of high frequency, high voltage, strong heat conductivity, etc. Silicon carbide MOS devices are used in applications such as electric vehicles and photovoltaic inverters due to their characteristics of easy driving and high switching frequency.
Silicon carbide MOS device mainly includes silicon carbide planar gate MOSFET and silicon carbide trench gate MOSFET. Compared with a planar gate MOSFET, the trench gate MOSFET eliminates the resistance of a JFET area, and has higher channel density, so that the on-state characteristic resistance of the device is remarkably reduced, and the side wall of the trench has excellent channel electron mobility due to the crystal orientation of the material. However, the silicon carbide trench gate MOSFET still has the following drawbacks:
first, in the development of power electronics, it is crucial to pursue operating efficiency and power density, since SiO is at the gate dielectric interface of silicon carbide trench gate MOSFETs2The interface state density of SiC is unavoidable, so that the silicon carbide trench gate MOSFET has larger on-resistance, the working efficiency and the power density are seriously influenced, and the channel resistance occupies most of the on-resistance of the silicon carbide trench gate MOSFET.
Secondly, grid trench electrode and grid trench oxide layer are the bar and arrange in traditional carborundum trench gate MOSFET cell, have the inhomogeneous and the inhomogeneous phenomenon of channel of resistance of slot both sides, and the phenomenon of aggravating the inhomogeneous flow of extreme condition such as short circuit simultaneously to lead to the irreversible damage of device.
Disclosure of Invention
The application aims to provide a MOS (metal oxide semiconductor) device based on different gate structures so as to solve the technical problems of overhigh channel resistance and nonuniform current of the device in the prior art.
In order to achieve the technical purpose, the technical scheme adopted by the application is as follows:
a MOS device based on different gate structures, comprising:
a first doped substrate;
a first doped structure connected to the first doped substrate;
a second doped structure connected with the first doped structure;
the trench gate structure is respectively connected with the first doping structure and the second doping structure;
the trench gate structure comprises a gate and a gate dielectric layer, the gate dielectric layer is arranged at the bottom and the side wall of the gate, the gate dielectric layer is respectively connected with the first doping structure and the second doping structure, and the gate is provided with a symmetrical or asymmetrical periodic arrangement structure.
Preferably, the first doping structure includes a first doping silicon carbide region and a first doping source region, the first doping silicon carbide region is arranged on the top layer of the first doping substrate, and the first doping source region and the second doping structure are connected.
Preferably, the second doping structure includes a second doping source region, a second doping well region and a second doping shielding region, the second doping source region is disposed on one side of the second doping well region, the trench gate structure is disposed on the other side of the second doping well region, and the second doping shielding region is disposed at the bottom layer of the trench gate structure.
Preferably, the grid electrode is in at least one of a gear shape, a wave shape, a triangular shape, a dumbbell shape and a sub-shape, and the grid dielectric layer and the grid electrode have the same shape.
Preferably, the fractal grid at least comprises a first-order fractal, and the first-order fractal is in at least one of a gear shape, a wave shape, a triangular shape, a dumbbell shape and a fractal shape.
Preferably, a first interval is arranged on one side of the gate dielectric layer, a second interval is arranged on the other side of the gate dielectric layer, and the difference between the first interval and the second interval is twice the thickness of the gate dielectric layer.
Preferably, the gate includes a first gate and a second gate, the gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer is disposed at the bottom and the sidewall of the first gate, and the second gate dielectric layer is disposed at the bottom and the sidewall of the second gate.
Preferably, the first gate electrode and the second gate electrode have the same shape and period, and the first gate dielectric layer and the second gate dielectric layer have the same shape and period.
Preferably, the first gate electrode and the second gate electrode have different shapes and periods, and the first gate dielectric layer and the second gate dielectric layer have different shapes and periods.
Preferably, the first gate electrode and the second gate electrode have the same shape and period, and the first gate dielectric layer and the second gate dielectric layer have different shapes and periods.
Preferably, the first gate and the second gate have the same shape, the first gate and the second gate have different periods, the first gate dielectric layer and the second gate dielectric layer have the same shape, and the first gate dielectric layer and the second gate dielectric layer have different periods.
A MOS device based on different gate structures, comprising:
a first doped substrate;
a first doped structure connected to the first doped substrate;
a second doped structure connected with the first doped structure;
the trench gate structure is respectively connected with the first doping structure and the second doping structure;
the trench gate structure comprises a gate and a gate dielectric layer, the gate dielectric layer is arranged at the bottom and on the side wall of the gate, and the gate dielectric layer surrounds the island-shaped first doped source region.
A MOS device based on different gate structures, comprising:
a first doped substrate;
a first doped structure connected to the first doped substrate;
a second doped structure connected with the first doped structure;
the trench gate structure is respectively connected with the first doping structure and the second doping structure;
the trench gate structure comprises a gate and a gate dielectric layer, the gate dielectric layer is arranged at the bottom and the side wall of the gate, the gate dielectric layer is respectively connected with the first doping structure and the second doping structure, the gate is provided with an island-shaped periodic arrangement structure, and the island-shaped periodic arrangement structures are mutually independent and have sealing performance.
The application provides beneficial effect lies in:
1. the trench gate structure comprises a gate and a gate dielectric layer, the gate is provided with a symmetrical or asymmetrical periodic arrangement structure, the area of a channel is remarkably increased on the premise of keeping the size and density of cells unchanged, the channel resistance of a device is effectively reduced, and the overall resistance of the device is reduced.
2. The utility model provides a gate dielectric layer one side is provided with first interval, gate dielectric layer opposite side is provided with the second interval, the difference of first interval and second interval is the thickness of twice gate dielectric layer, the grid includes first grid and second grid, the gate dielectric layer includes first gate dielectric layer and second gate dielectric layer, through different gate structures, avoid the phenomenon of channel current sharing, effectively reduce the channel resistance according to the demand of reality simultaneously, and can appear the FinFET effect when the trench gate structure reduces to below 40nm, help increasing the cross-sectional area of conducting channel, thereby further reduce the resistance of channel.
3. The first doping structure comprises an island-shaped first doping source region, the island-shaped first doping source regions are mutually independent and have sealing performance, the gate dielectric layer surrounds the island-shaped first doping source region, the channel length is further expanded, the current density is improved, when the width of the first doping source region is smaller than 50nm, the FinFET effect can occur, meanwhile, the gate dielectric layer surrounding the island-shaped first doping source region can increase the FinFET effect and the current concentration of a channel, and the channel mobility is improved.
4. The utility model provides a trench gate structure includes grid and gate dielectric layer, and the grid is provided with and is island-like periodic arrangement structure, is island-like periodic arrangement structure mutual independence and has the closure, and the grid produces the FinFET effect and forms the FinFET effect district to connect the first doping source region of the left and right sides, be favorable to the first doping source region of both sides to form ohmic contact under the state of broad, reduce the degree of difficulty that the MOS tube device formed ohmic contact.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a schematic diagram of a MOS device with a gear-shaped gate;
FIG. 2 is a top view of a MOS device with a gear-shaped gate;
FIG. 3 is a cross-sectional view of FIG. 2 at AA';
FIG. 4 is a cross-sectional view of FIG. 2 at BB';
FIG. 5 is a schematic structural diagram of a MOS device with a second doped source region in a gear shape;
FIG. 6 is a cross-sectional view of FIG. 5 at AA';
FIG. 7 is a cross-sectional view of FIG. 5 at BB';
FIG. 8 is a schematic diagram of a MOS device with a corrugated gate;
FIG. 9 is a schematic diagram of a gate triangular MOS device structure;
FIG. 10 is a schematic diagram of a MOS device with a gate having a split shape;
FIG. 11 is a schematic diagram of a MOS device with a gate electrode having a cogwheel shape and a FinFET effect;
FIG. 12 is a cross-sectional view of FIG. 11 at DD';
FIG. 13 is a schematic diagram of channel electron concentration;
fig. 14 is a schematic diagram of a MOS device with a dumbbell-shaped gate;
fig. 15 is a schematic diagram of a plurality of MOS device structures with alternating gate shapes;
fig. 16 is a schematic diagram of a symmetrical gate MOS device structure;
fig. 17 is a top view of a symmetrical gate MOS device structure;
FIG. 18 is a schematic diagram of a MOS device with a gate having a different period;
fig. 19 is a schematic diagram of a MOS device structure with gates having different shapes and periods;
fig. 20 is a schematic diagram of a MOS device structure including multiple gate dielectric layers;
fig. 21 is a schematic diagram of a MOS device structure including multiple gates;
the main element symbols are as follows:
1. a gate electrode; 2. a gate dielectric layer; 3. a first doped source region; 4. a second doped source region; 5. a second doped well region; 6. a second doped screening region; 7. a neck portion of the first doped source region; 8. a first gate electrode; 9. a second gate electrode; 10. a first gate dielectric layer; 11. and a second gate dielectric layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Example 1:
the present embodiment includes a MOS device based on different gate structures, including: a first doped substrate; the first doping structure is connected with the first doping substrate; the second doping structure is connected with the first doping structure; the trench gate structure is respectively connected with the first doping structure and the second doping structure; the trench gate structure comprises a gate 1 and a gate dielectric layer 2, the gate dielectric layer 2 is arranged at the bottom and the side wall of the gate 1, the gate dielectric layer 2 is respectively connected with the first doping structure and the second doping structure, and the gate 1 is provided with a symmetrical or asymmetrical periodic arrangement structure.
The first doping structure comprises a first doped silicon carbide region and a first doped source region 3, the first doped silicon carbide region is arranged on the top layer of the first doped substrate, and the first doped source region 3 is connected with the second doping structure.
The second doping structure comprises a second doping source region 4, a second doping well region 5 and a second doping shielding region 6, wherein the second doping source region 4 is arranged on one side of the second doping well region 5, a trench gate structure is arranged on the other side of the second doping well region 5, and the second doping shielding region 6 is arranged on the bottom layer of the trench gate structure.
Specifically, the semiconductor device further comprises a drain electrode and a source electrode, wherein the drain electrode is arranged on the bottom layer of the first doped substrate, ohmic contact is formed between the drain electrode and the bottom layer surface of the first doped substrate, the source electrode is arranged on the top layer of the first doped source region 3, and ohmic contact is formed between the source electrode and the top layer surface of the first doped source region 3.
A first interval is arranged on one side of the gate dielectric layer 2, a second interval is arranged on the other side of the gate dielectric layer 2, and the difference value between the first interval and the second interval is twice the thickness of the gate dielectric layer 2. The grid electrode 1 is in at least one of a gear shape, a wave shape, a triangular shape, a dumbbell shape and a sub-shape, and the grid dielectric layer 2 and the grid electrode 1 have the same shape.
As shown in fig. 1 and fig. 2, in this embodiment, a MOS device of the present application is sequentially provided with a first doped substrate and a first doped silicon carbide region from a bottom layer to a top layer, wherein a second doped source region 4, a second doped well region 5, and a second doped shielding region 6 are all disposed on a top surface of the first doped silicon carbide region, a first doped source region 3 is disposed on a top surface of the second doped well region 5, a trench gate structure is disposed on a top surface of the second doped shielding region 6, a second doped source region 4 is disposed on a left side of the first doped source region 3, and a trench gate structure and a second doped shielding region 6 are disposed on a right side of the first doped source region 3. The first doped source region 3 and the second doped well region 5 have the same shape structure, and the second doped shielding region 6 completely covers the bottom surface of the gate dielectric layer 2.
In the above embodiment, the gate 1 is in a gear shape, the gate dielectric layer 2 is disposed at the bottom and the sidewall of the gate 1, and the gate dielectric layer 2 and the gear-shaped gate 1 have the same shape. Specifically, the second doped well region 5 connected to the trench gate structure is a channel, and the channel density of the MOS device in this embodiment is (W1 + W1/(a + b) × c)/L1, where W1 denotes the length of the second doped well region 5, L1 denotes the width of the first doped silicon carbide region, a denotes the first pitch, b denotes the second pitch, and c denotes the width of the gear-shaped gate dielectric layer 2. From the above formula, the channel density of the MOS device can be adjusted according to the actual requirement.
As shown in fig. 3 and 4, fig. 3 is a cross-sectional view at AA 'of fig. 2, and fig. 4 is a cross-sectional view at BB' of fig. 2. In the above embodiment, the two sides of the gear-shaped gate 1 are asymmetric in structure, so the area of the gate 1 at AA 'is larger than the area of the gate 1 at BB', the area of the second doped shielding region 6 at AA 'is larger than the area of the second doped shielding region 6 at BB', the area of the second doped well region 5 at AA 'is smaller than the area of the second doped well region 5 at BB', the area of the first doped source region 3 at AA 'is smaller than the area of the first doped source region 3 at BB', and the area of the second doped source region 4 at AA 'is equal to the area of the second doped source region 4 at BB'. Wherein, the gear-shaped trench gate structure increases the contact area with the second doped well region 5, thereby reducing the resistance of the MOS device, and when the first pitch is smaller than 40nm, the FinFET effect gradually occurs, the thickness of the channel increases, thereby further reducing the resistance.
As shown in fig. 5, in this embodiment, the gate 1 is in a gear shape, the gate dielectric layer 2 is disposed at the bottom and the side wall of the gate 1, the gate dielectric layer 2 and the gear-shaped gate 1 have the same shape, further, the second doping source region 4 is also in a gear shape, and the gear convex portion of the second doping source region 4 is matched with the gear concave portion of the gate dielectric layer 2.
As shown in fig. 6 and 7, fig. 6 is a cross-sectional view of fig. 5 at AA ', fig. 7 is a cross-sectional view of fig. 5 at BB', in the above embodiment, the area of the gate 1 at AA 'is larger than that of the gate 1 at BB', the area of the second doped shielding region 6 at AA 'is larger than that of the second doped shielding region 6 at BB', the area of the second doped well region 5 at AA 'is equal to that of the second doped well region 5 at BB', the area of the first doped source region 3 at AA 'is equal to that of the first doped source region 3 at BB', and the area of the second doped source region 4 at AA 'is smaller than that of the second doped source region 4 at BB'. The gear-shaped second doping source region 4 further contacts the second doping shielding region 6, so that the bottom electric field of the second doping shielding region 6 is better protected.
As shown in fig. 8, in the present embodiment, a gate 1, a gate dielectric layer 2, a first doped source region 3, and a second doped source region 4 are sequentially arranged from left to right, the gate 1 is in a wavy shape, the gate dielectric layer 2 is disposed at the bottom and the sidewall of the gate 1, and the gate dielectric layer 2 and the wavy gate 1 have the same shape. The wavy grid electrode 1 and the wavy grid medium layer 2 can avoid the phenomena of uneven trench grid structure at the channel corner and polycrystal gap filling.
As shown in fig. 9, in the present embodiment, a gate 1, a gate dielectric layer 2, a first doped source region 3, and a second doped source region 4 are sequentially arranged from left to right, the gate 1 is in a triangular shape, the gate dielectric layer 2 is disposed at the bottom and the sidewall of the gate 1, and the gate dielectric layer 2 and the triangular gate 1 have the same shape. The triangular grid electrode 1 and the grid dielectric layer 2 can further increase the contact area with the second doped well region 5, and therefore the conduction performance is improved.
As shown in fig. 10, in this embodiment, a gate 1, a gate dielectric layer 2, a first doped source region 3, and a second doped source region 4 are sequentially arranged from left to right, the gate 1 is in a fractal shape, the fractal-shaped gate 1 includes at least one stage of fractal, and the stage of fractal is in at least one of a gear shape, a wave shape, a triangle shape, and a dumbbell shape.
The gate dielectric layer 2 is arranged at the bottom and the side wall of the grid electrode 1, and the gate dielectric layer 2 and the fractal grid electrode 1 have the same shape. The contact area between the shaped gate 1 and the gate dielectric layer 2 and the second doped well region 5 can be further increased, so that the conduction performance is improved. When the fractal antenna width is gradually reduced, the FinFET effect gradually occurs, the thickness of a channel is increased, and therefore resistance is further reduced. While the same technical effect can be achieved, the shape of the gate 1 of the present application includes, but is not limited to, the above types.
As shown in fig. 11 and 12, fig. 12 is a cross-sectional view of fig. 11 at DD', in this embodiment, the first doped source region 3 is disposed on the top surface of the second doped well region 5, both sides of the first doped source region 3 and the second doped well region 5 are trench gate structures, and the bottom of the trench gate structures at both sides are provided with the second doped shielding region 6, which can expand the depth of the channel, increase the electron concentration of the channel, and thereby improve the conduction performance. As shown in fig. 13, when the width of the second doped well region 5 is less than 40nm, the electron concentration of the channel is significantly increased, a FinFET effect occurs, and the channel mobility is improved, and meanwhile, because the area of the first doped source region 3 is smaller, the ohmic contact between the source and the top surface of the first doped source region 3 is more favorably formed.
As shown in fig. 14, in the present embodiment, a gate 1, a gate dielectric layer 2, a first doped source region 3, and a second doped source region 4 are sequentially arranged from left to right, the gate 1 is dumbbell-shaped, the gate dielectric layer 2 is disposed at the bottom and the sidewall of the gate 1, and the gate dielectric layer 2 and the dumbbell-shaped gate 1 have the same shape. The structure enables FinFET effect to be generated on the right side of the first doping source region 3, the dumbbell-shaped grid 1 and the grid dielectric layer 2 further increase the width of the second doping well region 5, and channel resistance is reduced. The risk that channel resistance has a short circuit is reduced, the neck of the first doping source region 3 can play a role of a ballast resistor, and meanwhile, the neck can play a role of flow equalization and large current limitation, so that the short circuit robustness of the MOS transistor device is improved.
Example 2:
the difference from example 1 is that: the grid 1 comprises a first grid 8 and a second grid 9, the grid dielectric layer 2 comprises a first grid dielectric layer 10 and a second grid dielectric layer 11, the first grid dielectric layer 10 is arranged at the bottom and on the side wall of the first grid 8, and the second grid dielectric layer 11 is arranged at the bottom and on the side wall of the second grid 9.
The first gate electrode 8 and the second gate electrode 9 have the same shape and period, and the first gate dielectric layer 10 and the second gate dielectric layer 11 have different shapes and periods. The first gate electrode 8 and the second gate electrode 9 have different shapes and periods, and the first gate dielectric layer 10 and the second gate dielectric layer 11 have different shapes and periods.
As shown in fig. 15, in this embodiment, the first gate dielectric layer 10 and the second gate dielectric layer 11 are disposed on the same side and connected to each other, the first gate 8 and the second gate 9 have different shapes and different periods, the first gate 8 is in a gear shape, the second gate 9 is in a wave shape, the first gate dielectric layer 10 and the second gate dielectric layer 11 have different shapes and different periods, the first gate dielectric layer 10 is disposed at the bottom and the sidewall of the first gate 8, the first gate dielectric layer 10 is in a gear shape, the second gate dielectric layer 11 is disposed at the bottom and the sidewall of the second gate 9, and the second gate dielectric layer 11 is in a wave shape.
The first gate electrode 8 and the second gate electrode 9 have the same shape and period, and the first gate dielectric layer 10 and the second gate dielectric layer 11 have the same shape and period.
As shown in fig. 16 and 17, fig. 17 is a top view of fig. 16, in this embodiment, the gate 1 includes a first gate 8 and a second gate 9, the first gate 8 and the second gate 9 have the same shape and period, and the first gate 8 is connected to the second gate 9, a first gate dielectric layer 10 is disposed on the bottom and the sidewall of the first gate 8, a second gate dielectric layer 11 is disposed on the bottom and the sidewall of the second gate 9, the first gate dielectric layer 10 and the second gate dielectric layer 11 have the same shape and period, and the first gate dielectric layer 10 is connected to the second gate dielectric layer 11. The left side of the first gate dielectric layer 10 is provided with a first doped source region 3 and a second doped well region 5, and the right side of the second gate dielectric layer 11 is provided with a first doped source region 3 and a second doped well region 5.
The first gate electrode 8 and the second gate electrode 9 have the same shape, the first gate electrode 8 and the second gate electrode 9 have different periods, the first gate dielectric layer 10 and the second gate dielectric layer 11 have the same shape, and the first gate dielectric layer 10 and the second gate dielectric layer 11 have different periods.
As shown in fig. 18, in this embodiment, the gate 1 includes a first gate 8 and a second gate 9, the first gate 8 and the second gate 9 are both in a gear shape, but the first gate 8 and the second gate 9 have different periods, the first gate 8 is connected to the second gate 9, the first gate dielectric layer 10 and the second gate dielectric layer 11 are both in a gear shape, but the first gate dielectric layer 10 and the second gate dielectric layer 11 have different periods, the first gate dielectric layer 10 is disposed at the bottom and the sidewall of the first gate 8, and the second gate dielectric layer 11 is disposed at the bottom and the sidewall of the second gate 9.
As shown in fig. 19, in this embodiment, the gate 1 includes a first gate 8 and a second gate 9, the first gate dielectric layer 10 and the second gate dielectric layer 11 are disposed on two sides and are not connected, the first gate 8 and the second gate 9 have different shapes and different periods, the first gate 8 is in a gear shape, the second gate 9 is in a wave shape, the first gate 8 and the second gate 9 are connected, the first gate dielectric layer 10 and the second gate dielectric layer 11 have different shapes and periods, the first gate dielectric layer 10 is disposed on the bottom and the sidewall of the first gate 8, the first gate dielectric layer 10 is in a gear shape, the second gate dielectric layer 11 is disposed on the bottom and the sidewall of the second gate 9, the second gate dielectric layer 11 is in a wave shape, and the first gate dielectric layer 10 and the second gate dielectric layer 11 are not connected.
Example 3:
the present embodiment includes a MOS device based on different gate structures, including: a first doped substrate; the first doping structure is connected with the first doping substrate; the second doping structure is connected with the first doping structure; and the groove gate structure is respectively connected with the first doping structure and the second doping structure.
The first doping structure comprises an island-shaped first doping source region 3, the island-shaped first doping source regions 3 are mutually independent and have sealing performance, the trench gate structure comprises a gate 1 and a gate dielectric layer 2, the gate dielectric layer 2 is arranged at the bottom and on the side wall of the gate 1, and the gate dielectric layer 2 surrounds the island-shaped first doping source region 3.
The first doping structure further comprises a first doped silicon carbide region and a first doped source region 3 in the shape of a gear. The second doping structure comprises a second doped source region 4, a second doped well region 5 and a second doped screening region 6. Specifically, the semiconductor device further comprises a drain electrode and a source electrode, wherein the drain electrode is arranged on the bottom layer of the first doped substrate, ohmic contact is formed between the drain electrode and the bottom layer surface of the first doped substrate, the source electrode is arranged on the top layer of the first doped source region 3, and ohmic contact is formed between the source electrode and the top layer surface of the first doped source region 3.
As shown in fig. 20, in this embodiment, the gate 1 includes a first gate 8 and a second gate 9, the first gate 8 and the second gate 9 have the same shape and period, the first gate 8 and the second gate 9 are connected, the first gate dielectric layer 10 and the second gate dielectric layer 11 have different shapes and periods, the first gate dielectric layer 10 is disposed at the bottom and the sidewall of the first gate 8, the first gate dielectric layer 10 is in a gear shape, the second gate dielectric layer 11 is disposed at the bottom and the sidewall of the second gate 9, the second gate dielectric layer 11 is in a rectangular shape, and the first gate dielectric layer 10 and the second gate dielectric layer 11 are not connected.
Wherein, one side of the first doping source region 3 in the shape of a gear is provided with a second doping source region 4, and the gate dielectric layer 2 surrounds the first doping source region 3 in the shape of an island. In this embodiment, the structure of the MOS device further extends the channel length, so as to increase the current density, when the width of the first doped source region 3 is less than 50nm, the FinFET effect will also occur, and the gate dielectric layer 2 surrounding the island-shaped first doped source region 3 can increase the FinFET effect and the current concentration of the channel, thereby improving the channel mobility.
Example 4:
the present embodiment includes a MOS device based on different gate structures, including: a first doped substrate; the first doping structure is connected with the first doping substrate; the second doping structure is connected with the first doping structure; and the groove gate structure is respectively connected with the first doping structure and the second doping structure.
The trench gate structure comprises a gate 1 and a gate dielectric layer 2, the gate dielectric layer 2 is arranged at the bottom and the side wall of the gate 1, the gate dielectric layer 2 is respectively connected with the first doping structure and the second doping structure, the gate 1 is provided with an island-shaped periodic arrangement structure, and the island-shaped periodic arrangement structures are mutually independent and have sealing performance.
Specifically, the semiconductor device further comprises a drain electrode and a source electrode, wherein the drain electrode is arranged on the bottom layer of the first doped substrate, ohmic contact is formed between the drain electrode and the bottom layer surface of the first doped substrate, the source electrode is arranged on the top layer of the first doped source region 3, and ohmic contact is formed between the source electrode and the top layer surface of the first doped source region 3.
As shown in fig. 21, the trench gate structure is disposed in the middle of the first doped source region 3, the trench gate structure includes a plurality of gates 1, an island-shaped periodic arrangement structure is formed between the plurality of gates 1, each gate 1 is independent and has a sealing property, the gate dielectric layer 2 covers the bottom of the gate 1 and the sidewall above the bottom of the gate 1, and both sides of the first doped source region 3 are the second doped source regions 4.
It should be noted that:
reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, the appearances of the phrase "one embodiment" or "an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
In addition, it should be noted that the specific embodiments described in the present specification may differ in the shape of the components, the names of the components, and the like. All equivalent or simple changes in the structure, characteristics and principles as described in the patent idea are included in the protection scope of the patent. Various modifications, additions and substitutions for the specific embodiments described herein may occur to those skilled in the art without departing from the scope and spirit of the invention as defined by the accompanying claims.

Claims (13)

1. A MOS device based on different gate structures, comprising:
a first doped substrate;
a first doped structure connected to the first doped substrate;
a second doped structure connected with the first doped structure;
the trench gate structure is respectively connected with the first doping structure and the second doping structure;
the trench gate structure comprises a gate and a gate dielectric layer, the gate dielectric layer is arranged at the bottom and the side wall of the gate, the gate dielectric layer is respectively connected with the first doping structure and the second doping structure, and the gate is provided with a symmetrical or asymmetrical periodic arrangement structure.
2. The different gate structure-based MOS device of claim 1, wherein the first doped structure comprises a first doped silicon carbide region disposed on a top layer of the first doped substrate and a first doped source region, the first doped source region being connected to the second doped structure.
3. The MOS device of claim 1, wherein the second doped structure comprises a second doped source region, a second doped well region and a second doped shielding region, the second doped source region is disposed on one side of the second doped well region, the trench gate structure is disposed on the other side of the second doped well region, and the second doped shielding region is disposed on the bottom layer of the trench gate structure.
4. The MOS device of any of claims 1-3, wherein the gate electrode is at least one of cogged, wavy, triangular, dumbbell-shaped, and profiled, and wherein the gate dielectric layer and the gate electrode have the same shape.
5. The MOS device of claim 4, wherein the profiled gate comprises at least one stage, the stage being at least one of cogwheel, wave, triangle, dumbbell, and profiled.
6. The MOS device of claim 1, wherein one side of the gate dielectric layer is provided with a first pitch and the other side of the gate dielectric layer is provided with a second pitch, and the difference between the first pitch and the second pitch is twice the thickness of the gate dielectric layer.
7. The MOS device of any of claims 1-3, wherein the gate comprises a first gate and a second gate, and the gate dielectric layer comprises a first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer is disposed on the bottom and the sidewall of the first gate, and the second gate dielectric layer is disposed on the bottom and the sidewall of the second gate.
8. The MOS device of claim 7, wherein the first gate electrode and the second gate electrode have the same shape and period, and wherein the first gate dielectric layer and the second gate dielectric layer have the same shape and period.
9. The MOS device of claim 7, wherein the first gate electrode and the second gate electrode have different shapes and periods, and wherein the first gate dielectric layer and the second gate dielectric layer have different shapes and periods.
10. The MOS device of claim 7, wherein the first gate electrode and the second gate electrode have the same shape and period, and wherein the first gate dielectric layer and the second gate dielectric layer have different shapes and periods.
11. The MOS device of claim 7, wherein the first gate and the second gate have the same shape and have different periods, the first gate dielectric layer and the second gate dielectric layer have the same shape and have different periods.
12. A MOS device based on different gate structures, comprising:
a first doped substrate;
a first doped structure connected to the first doped substrate;
a second doped structure connected with the first doped structure;
the trench gate structure is respectively connected with the first doping structure and the second doping structure;
the trench gate structure comprises a gate and a gate dielectric layer, the gate dielectric layer is arranged at the bottom and on the side wall of the gate, and the gate dielectric layer surrounds the island-shaped first doped source region.
13. A MOS device based on different gate structures, comprising:
a first doped substrate;
a first doped structure connected to the first doped substrate;
a second doped structure connected with the first doped structure;
the trench gate structure is respectively connected with the first doping structure and the second doping structure;
the trench gate structure comprises a gate and a gate dielectric layer, the gate dielectric layer is arranged at the bottom and the side wall of the gate, the gate dielectric layer is respectively connected with the first doping structure and the second doping structure, the gate is provided with an island-shaped periodic arrangement structure, and the island-shaped periodic arrangement structures are mutually independent and have sealing performance.
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08330601A (en) * 1995-03-30 1996-12-13 Toshiba Corp Semiconductor device and manufacture thereof
US6060747A (en) * 1997-09-30 2000-05-09 Kabushiki Kaisha Toshiba Semiconductor device
US20030141514A1 (en) * 1999-10-19 2003-07-31 Hitoshi Yamaguchi Method of manufacturing semiconductor device having trench filled up with gate electrode
US20090078994A1 (en) * 2007-09-21 2009-03-26 Yoshinori Takami Semiconductor device and method for fabricating the same
CN111916498A (en) * 2019-05-07 2020-11-10 格芯公司 Field effect transistor with laterally meandering gate
US11152503B1 (en) * 2019-11-05 2021-10-19 Semiq Incorporated Silicon carbide MOSFET with wave-shaped channel regions
US20210351296A1 (en) * 2020-05-09 2021-11-11 Joulwatt Technology Co., Ltd. Semiconductor device and manufacturing method thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08330601A (en) * 1995-03-30 1996-12-13 Toshiba Corp Semiconductor device and manufacture thereof
US6060747A (en) * 1997-09-30 2000-05-09 Kabushiki Kaisha Toshiba Semiconductor device
US20030141514A1 (en) * 1999-10-19 2003-07-31 Hitoshi Yamaguchi Method of manufacturing semiconductor device having trench filled up with gate electrode
US20090078994A1 (en) * 2007-09-21 2009-03-26 Yoshinori Takami Semiconductor device and method for fabricating the same
CN111916498A (en) * 2019-05-07 2020-11-10 格芯公司 Field effect transistor with laterally meandering gate
US11152503B1 (en) * 2019-11-05 2021-10-19 Semiq Incorporated Silicon carbide MOSFET with wave-shaped channel regions
US20210351296A1 (en) * 2020-05-09 2021-11-11 Joulwatt Technology Co., Ltd. Semiconductor device and manufacturing method thereof

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