CN113990928B - Trench MOSFET device with low breakdown voltage temperature coefficient and preparation method thereof - Google Patents
Trench MOSFET device with low breakdown voltage temperature coefficient and preparation method thereof Download PDFInfo
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Abstract
The invention provides a Trench MOSFET device with low breakdown voltage temperature coefficient and a preparation method thereof, wherein the Trench MOSFET device comprises a P+ substrate, a metalized drain electrode, a P-drift region, a metalized source electrode, an oxide layer, a gate electrode, an N-doped region, a P+ heavily doped region, an N+ heavily doped region and a metalized source electrode; the invention effectively solves the reliability problem caused by the increase of the punch-through breakdown voltage of the Trench MOSFET along with the temperature rise. Obviously, all the P-type regions and all the N-type regions can be exchanged, and the exchanged P-type regions and the N-type regions become a device with opposite conductivity types. The structure can also provide a key technology for realizing low breakdown voltage temperature coefficient for other similar devices.
Description
Technical Field
The invention relates to a field effect transistor device structure, and belongs to the technical field of power semiconductors.
Background
With the improvement of the power control capability, the fields of traffic, medical treatment, consumer electronics, power transmission and the like are greatly developed, and the dependence of people on electronic products is rapidly improved. Power MOSFETs play an extremely important role in power technology, and scientific technology can develop so rapidly as to benefit from the development of power MOSFET devices. The conventional double diffusion MOSFET adopts the double diffusion technology to form the body region, so that the cell width is large, and meanwhile, the on-resistance is large due to the existence of the JFET region inside the cell. The grid groove of the Trench MOSFET is positioned in the body region and goes deep into the drift region, and the conducting channel is a longitudinal channel, so that the cell density can be improved, the resistance of the JFET region can be eliminated, the on-resistance is closer to an ideal value, the working frequency of the power MOSFET is improved to the range of 1MHz by optimizing the structure, and the structure is widely applied to the field of low-voltage high-frequency products.
The temperature coefficient of the breakdown voltage is one of the more important operating parameters of MOSFET devices. The punch-through breakdown voltage of the device increases with increasing temperature, resulting in instability problems of the device caused by temperature changes, which can seriously affect the reliability of the MOSFET device. The structure provided by the invention can improve the instability problem caused by temperature change on the basis of the Trench MOSFET structure, and enhance the reliability of the MOSFET device in application.
Disclosure of Invention
The invention aims to provide a Trench MOSFET structure with a low breakdown voltage temperature coefficient. Taking a P channel as an example, introducing a p+ heavily doped region 7 and an n+ heavily doped region 8 into the Trench MOSFET, namely introducing a PN junction, and utilizing the fact that the width of the depletion region of the PN junction becomes smaller along with the temperature rise, further reducing the resistance of the p+ heavily doped region 7, and reducing the voltage drop of the p+ heavily doped region to compensate the characteristic that the punch-through breakdown voltage of the Trench MOSFET increases along with the temperature rise.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
a low-breakdown-voltage temperature-coefficient Trench MOSFET device comprises a P+ substrate 2, a metallized drain electrode 1 positioned on the back surface of the P+ substrate, a P-drift region 3 positioned on the P+ substrate, a metallized source electrode 9 positioned on the top layer of the whole Trench MOSFET structure, and a gate electrode 4 wrapped by an oxide layer 5; an N-doped region 6 and a P+ heavily doped region 7 are arranged on two sides of the oxide layer 5, the P+ heavily doped region 7 is positioned on the upper side of the N-doped region 6, and the vertical depth of the bottom of the N-doped region 6 is not more than the vertical depth of the bottom of the gate electrode 4; the top of the gate electrode 4 is higher than the top of the P+ heavily doped region 7 on the left and right sides; the side above the inside of the P+ heavily doped region 7 and far from the oxide layer 5 is an N+ heavily doped region 8, and the top of the N+ heavily doped region 8 is flush with the top of the P+ heavily doped region 7; the metalized source electrode 9 covers the surface layer of the device and is contacted with the N+ heavily doped region 8 and the P+ heavily doped region 7, and the metalized source electrode 9 is isolated from the gate electrode 4;
when the device is conducted in the forward direction, the gate electrode 4 is connected with negative potential, the metalized drain electrode 1 is connected with negative potential, and the metalized source electrode 9 is connected with zero potential; when the device is blocked in the reverse direction, the gate electrode 4 and the metalized source electrode 9 are short-circuited and connected with zero potential, and the metalized drain electrode 1 is connected with negative potential.
Preferably, the oxide layer 5 is silicon dioxide or a composite of silicon dioxide and silicon nitride.
Preferably, the gate electrode 4 is made of polysilicon.
Preferably, the material of the entire device is bulk silicon, or silicon carbide, or gallium arsenide or silicon germanium.
Preferably, all N-type regions are swapped with all P-type regions to form a device of opposite conductivity type.
Preferably, the P+ heavily doped region 7 has a doping concentration of greater than 1e17/cm 3 The doping concentration of the N+ heavily doped region 8 is greater than 1e19/cm 3 。
The invention also provides a preparation method of the Trench MOSFET device with the low breakdown voltage temperature coefficient, which comprises the following steps:
(1) Preparing monocrystalline silicon and epitaxially growing; a heavily doped monocrystalline silicon P+ substrate 2 is adopted, the crystal direction is <100>, and a vapor phase epitaxy VPE method is adopted to grow a P-drift region 3;
(2) Grooving; depositing a hard mask; as a barrier layer for subsequent grooving, carrying out groove etching by using a photoetching plate to etch a groove gate region, wherein the specific etching process is reactive ion etching or plasma etching;
(3) Thermal growth of silicon dioxide; removing the hard mask, and growing a silicon dioxide layer in the groove to form an oxide layer 5;
(4) Depositing and etching polysilicon; depositing polysilicon to form a gate electrode 4; ensuring that the thickness of the polysilicon can fill the groove-shaped region; etching the top of the polysilicon and the silicon dioxide by using a photoetching plate;
(5) Depositing an oxide layer; depositing an oxide layer on the top of the gate electrode 4 and etching away the redundant oxide layer;
(6) Ion implantation; phosphorus implantation to form an N-doped region 6, wherein the vertical depth of the N-doped region 6 does not exceed the depth of the gate electrode 4;
(7) Ion implantation; boron is injected to form a P+ heavily doped region 7, and then arsenic is injected to form an N+ heavily doped region 8;
(8) Metallizing; front side metallization, metal etching, back side metallization and passivation.
The working principle of the invention is explained in two ways:
(1) Forward conduction of a device
The electrode connection mode of the low-breakdown-voltage temperature coefficient Trench MOSFET structure provided by the invention in forward conduction is as follows: the gate electrode 4 is connected with negative potential, the metalized drain electrode 1 is connected with negative potential, and the metalized source electrode 9 is connected with zero potential. When the negative bias voltage applied by the gate electrode 4 reaches the threshold voltage, an inversion layer channel is formed on one side, close to the oxide layer 5, of the N-doped region 6, a multi-sub hole accumulation layer is formed on one side, close to the oxide layer 5, of the P+ heavily doped region 7, and under the reverse bias voltage of the metalized drain 1, holes are injected into the P-drift region 3 as carriers from the P+ heavily doped region 7 through the inversion layer channel in the N-doped region 6, reach the metalized drain 1 to form forward current, and the device is turned on. Wherein the top of the gate electrode 4 is higher than the top of the p+ heavily doped region 7, which ensures that a hole accumulation layer can be formed on the side of the p+ heavily doped region 7 near the oxide layer 5, so as to reduce the on-resistance when the device is turned on.
(2) Reverse blocking of devices
The invention provides a low breakdown voltage temperature coefficient Trench MOSFET structure, which is characterized in that the electrode connection mode during reverse blocking is as follows: the gate electrode 4 is connected with zero potential, the metalized source electrode 9 is connected with zero potential, and the metalized drain electrode 1 is connected with negative potential. The conduction path of the multi-sub holes is pinched off because there is no inversion layer channel in the N-doped region 6 when the gate electrode 4 is zero biased. Upon increasing the reverse voltage, the N-doped region 6 is fully depleted, i.e. punch-through. Due to the introduction of the N+ heavily doped region 8 and the P+ heavily doped region 7, a JFET region is formed between the N+ heavily doped region 8 and the groove, and as the temperature rises, the width of a PN junction depletion region between the N+ heavily doped region 8 and the P+ heavily doped region 7 is reduced, and the resistance of the JFET region is reduced. Compared with the traditional Trench MOSFET device, the temperature-dependent resistor with the negative temperature coefficient is connected in series on one side of the device, namely the JFET region, and the voltage drop on the temperature-dependent resistor is reduced along with the temperature rise, so that the breakdown voltage with the positive temperature coefficient can be compensated, and the temperature coefficient of the breakdown voltage is reduced.
The beneficial effects of the invention are as follows: the Trench MOSFET structure with the low breakdown voltage temperature coefficient effectively solves the problem of reliability caused by the fact that the punch-through breakdown voltage of the Trench MOSFET is increased along with the temperature rise. Obviously, all the P-type regions and all the N-type regions can be exchanged, and the exchanged P-type regions and the N-type regions become a device with opposite conductivity types. The structure can also provide a key technology for realizing low breakdown voltage temperature coefficient for other similar devices.
Drawings
Fig. 1 is a schematic diagram of a cross-sectional structure of a device of a low breakdown voltage temperature coefficient Trench MOSFET structure provided by the present invention.
Fig. 2-1 is a graph of avalanche breakdown voltage versus temperature for a conventional Trench MOSFET device at temperatures of 300K, 350K, 400K;
fig. 2-2 are graphs of punch-through breakdown voltage as a function of temperature for conventional Trench MOSFET devices at temperatures of 300K, 350K, 400K.
Fig. 2-3 are simulated graphs of breakdown voltage as a function of temperature for devices of the present invention at temperatures of 300K, 350K, 400K.
Fig. 3-1 to 3-8 are schematic flow diagrams of a method for manufacturing a low breakdown voltage temperature coefficient Trench MOSFET device according to the present invention.
1 is a metalized drain electrode, 2 is a P+ substrate, 3 is a P-drift region, 4 is a gate electrode, 5 is an oxide layer, 6 is an N-doped region, 7 is a P+ heavily doped region, 8 is an N+ heavily doped region, and 9 is a metalized source electrode.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
A low-breakdown-voltage temperature-coefficient Trench MOSFET device comprises a P+ substrate 2, a metallized drain electrode 1 positioned on the back surface of the P+ substrate, a P-drift region 3 positioned on the P+ substrate, a metallized source electrode 9 positioned on the top layer of the whole Trench MOSFET structure, and a gate electrode 4 wrapped by an oxide layer 5; an N-doped region 6 and a P+ heavily doped region 7 are arranged on two sides of the oxide layer 5, the P+ heavily doped region 7 is positioned on the upper side of the N-doped region 6, and the vertical depth of the bottom of the N-doped region 6 is not more than the vertical depth of the bottom of the gate electrode 4; the top of the gate electrode 4 is higher than the top of the P+ heavily doped region 7 on the left and right sides; the side above the inside of the P+ heavily doped region 7 and far from the oxide layer 5 is an N+ heavily doped region 8, and the top of the N+ heavily doped region 8 is flush with the top of the P+ heavily doped region 7; the metalized source electrode 9 covers the surface layer of the device and is contacted with the N+ heavily doped region 8 and the P+ heavily doped region 7, and the metalized source electrode 9 is isolated from the gate electrode 4;
when the device is conducted in the forward direction, the gate electrode 4 is connected with negative potential, the metalized drain electrode 1 is connected with negative potential, and the metalized source electrode 9 is connected with zero potential; when the device is blocked in the reverse direction, the gate electrode 4 and the metalized source electrode 9 are short-circuited and connected with zero potential, and the metalized drain electrode 1 is connected with negative potential.
The oxide layer 5 is silicon dioxide or a composite material of silicon dioxide and silicon nitride.
The gate electrode 4 is made of polysilicon.
Preferably, the material of the entire device is bulk silicon, or silicon carbide, or gallium arsenide or silicon germanium.
Preferably, all N-type regions are swapped with all P-type regions to form a device of opposite conductivity type.
Preferably, the P+ heavily doped region 7 has a doping concentration of greater than 1e17/cm 3 The doping concentration of the N+ heavily doped region 8 is greater than 1e19/cm 3 。
The embodiment also provides a preparation method of the Trench MOSFET device with the low breakdown voltage temperature coefficient, which comprises the following steps:
(1) Preparing monocrystalline silicon and epitaxially growing; as shown in fig. 3-1, a heavily doped monocrystalline silicon p+ substrate 2 is adopted, the crystal direction is <100>, and a vapor phase epitaxy VPE method is adopted to grow a P-drift region 3;
(2) Grooving; as shown in fig. 3-2, a hard mask (such as silicon nitride) is deposited as a barrier layer for subsequent grooving, and a photoetching plate is used for carrying out groove etching to etch a groove gate region, wherein the specific etching process is reactive ion etching or plasma etching;
(3) Thermal growth of silicon dioxide; as shown in fig. 3-3, removing the hard mask, and growing a silicon dioxide layer in the groove to form an oxide layer 5;
(4) Depositing and etching polysilicon; as shown in fig. 3-4, polysilicon is deposited to form a gate electrode 4; ensuring that the thickness of the polysilicon can fill the groove-shaped region; etching the top of the polysilicon and the silicon dioxide by using a photoetching plate;
(5) Depositing an oxide layer; as shown in fig. 3-5, an oxide layer is deposited on top of the gate electrode 4 and the excess oxide layer is etched away;
(6) Ion implantation; as shown in fig. 3-6, phosphorus is implanted to form N-doped region 6, wherein the vertical depth of N-doped region 6 does not exceed the depth of gate electrode 4;
(7) Ion implantation; as shown in fig. 3-7, boron is implanted to form p+ heavily doped region 7, and then arsenic is implanted to form n+ heavily doped region 8;
(8) Metallizing; as in fig. 3-8, front side metallization, metal etching, back side metallization, passivation.
In the above description, in the embodiments of the present invention, when manufacturing a device, semiconductor materials such as silicon carbide, gallium arsenide, or silicon germanium may be used instead of bulk silicon.
Under the pressure resistance of about 40V, the temperature coefficient of avalanche breakdown of the traditional device is about 40mV/K, the temperature coefficient of punch-through breakdown is about 20mV/K, temperatures of 300K, 350K and 400K are respectively selected, and the curves of breakdown voltages of the two with the change of temperature are respectively shown in figures 2-1 and 2-2. The invention is based on Trench MOSFET device optimization, with cell width of 2.8 μm, drift region thickness of 8 μm, trench depth of 1.6 μm, trench width of 0.67 μm, gate oxide thickness of 0.05 μm, the following parameters are finally determined by parameter bias to meet the requirements of the invention: the resistivity of the P-drift region 3 is 2, the doping amount, the implantation energy and the junction pushing time of the N-doped region 6 are 6.6e12/cm respectively 2 And 150Kev for 60 min, the doping amount, the implantation energy and the junction pushing time of the P+ heavily doped region 7 are respectively 3e13/cm 2 And 60Kev for 20 minutes, the twice doping amount and implantation energy of the N+ heavily doped region 8 are 5e14/cm respectively 2 And 25Kev,5e13 and 35Kev. The breakdown voltage temperature change curve of the invention is shown in figures 2-3, and the temperature coefficient is 3mV/K, so that the invention can effectively reduce the temperature coefficient of the breakdown voltage of the Trench MOSFET.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims of this invention, which are within the skill of those skilled in the art, can be made without departing from the spirit and scope of the invention disclosed herein.
Claims (7)
1. A low breakdown voltage temperature coefficient Trench MOSFET device, characterized in that: the structure comprises a P+ substrate (2), a metalized drain electrode (1) positioned on the back surface of the P+ substrate, a P-drift region (3) positioned on the P+ substrate, a metalized source electrode (9) positioned on the top layer of the whole Trench MOSFET structure, and a gate electrode (4) wrapped by an oxide layer (5); the two sides of the oxide layer (5) are respectively provided with an N-doped region (6) and a P+ heavily doped region (7), the P+ heavily doped region (7) is positioned on the upper side of the N-doped region (6), and the vertical depth of the bottom of the N-doped region (6) is not more than the vertical depth of the bottom of the gate electrode (4); the top of the gate electrode (4) is higher than the tops of the P+ heavily doped regions (7) on the left side and the right side; an N+ heavily doped region (8) is arranged on one side, which is above the inner part of the P+ heavily doped region (7) and is far away from the oxide layer (5), and the top of the N+ heavily doped region (8) is level with the top of the P+ heavily doped region (7); the metalized source electrode (9) covers the surface layer of the device and is contacted with the N+ heavy doping region (8) and the P+ heavy doping region (7), and the metalized source electrode (9) is isolated from the gate electrode (4);
when the device is conducted in the forward direction, the gate electrode (4) is connected with negative potential, the metalized drain electrode (1) is connected with negative potential, and the metalized source electrode (9) is connected with zero potential; when the device is blocked in the reverse direction, the gate electrode (4) and the metalized source electrode (9) are short-circuited and connected with zero potential in parallel, and the metalized drain electrode (1) is connected with negative potential.
2. A low breakdown voltage temperature coefficient Trench MOSFET device according to claim 1, wherein: the oxide layer (5) is silicon dioxide or a composite material of silicon dioxide and silicon nitride.
3. A low breakdown voltage temperature coefficient Trench MOSFET device according to claim 1, wherein: the gate electrode (4) is made of polysilicon.
4. A low breakdown voltage temperature coefficient Trench MOSFET device according to claim 1, wherein: the material of the whole device is bulk silicon, or silicon carbide, or gallium arsenide or silicon germanium.
5. A low breakdown voltage temperature coefficient Trench MOSFET device according to claim 1, wherein: all the N-type regions are exchanged with all the P-type regions, and the exchanged N-type regions become a device with opposite conductivity type.
6. A low breakdown voltage temperature coefficient Trench MOSFET device according to claim 1, wherein: the doping concentration of the P+ heavily doped region (7) is more than 1e17/cm 3 The doping concentration of the N+ heavily doped region (8) is greater than 1e19/cm 3 。
7. A method of fabricating a low breakdown voltage temperature coefficient Trench MOSFET device according to claim 1, wherein: the method comprises the following steps:
(1) Preparing monocrystalline silicon and epitaxially growing: a heavily doped monocrystalline silicon P+ substrate (2) is adopted, the crystal direction is <100>, and a vapor phase epitaxy VPE method is adopted to grow a P-drift region (3);
(2) Grooving; and (3) depositing a hard mask: as a barrier layer for subsequent grooving, carrying out groove etching by using a photoetching plate to etch a groove gate region, wherein the specific etching process is reactive ion etching or plasma etching;
(3) Thermal growth of silica: removing the hard mask, and growing a silicon dioxide layer in the groove to form an oxide layer (5);
(4) Deposition and etching of polysilicon: depositing polysilicon to form a gate electrode (4); ensuring that the thickness of the polysilicon can fill the groove-shaped region; etching the top of the polysilicon and the silicon dioxide by using a photoetching plate;
(5) And (3) oxide layer deposition: depositing an oxide layer on the top of the gate electrode (4), and etching away the redundant oxide layer;
(6) Ion implantation: phosphorus implantation to form an N-doped region (6), wherein the vertical depth of the N-doped region (6) does not exceed the depth of the gate electrode (4);
(7) Ion implantation: boron is injected to form a P+ heavily doped region (7), and then arsenic is injected to form an N+ heavily doped region (8);
(8) And (3) metallization: front side metallization, metal etching, back side metallization and passivation.
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