CN113986625A - Detection method and device for PCS sublayer logic function, electronic equipment and storage medium - Google Patents
Detection method and device for PCS sublayer logic function, electronic equipment and storage medium Download PDFInfo
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Abstract
The invention discloses a method and a device for detecting the logic function of a PCS sublayer, electronic equipment and a storage medium, wherein the method comprises the following steps: generating a first test stimulus, the first test stimulus comprising a data block and/or a control block; the PCS sublayer transmitting end receives and codes the first test excitation, and obtains a plurality of distribution data which are correspondingly distributed to a plurality of transmitting channels according to the coded data; delaying and/or scrambling the order of at least part of the distributed data to obtain scrambled data; the PCS sublayer receiving end receives and restores the disturbed data to obtain restored data; the restored data is compared to a second test stimulus, which is the first test stimulus or is the same as the first test stimulus. The invention delays and/or disturbs the sequence of at least part of the distributed data to achieve the effect of delaying and/or disordering when the analog data passes through the PMA sublayer, thereby preventing the data from directly passing through the PMA sublayer and being beneficial to quickly and accurately detecting the logic function of the PCS sublayer.
Description
Technical Field
The invention relates to the field of electronic communication Ethernet, in particular to a method and a device for detecting a logical function of a PCS sublayer, electronic equipment and a storage medium.
Background
In 2017, the IEEE802.3 Ethernet working group formally approved the 200Gb/s Ethernet standard IEEE802.3 bs. The standard defines the medium access control parameters, physical layer specifications and management parameters required for ethernet networks that transmit at 200Gb/s speed. The IEEE802.3bs standard covers various interconnection applications, the ultra-high bandwidth can completely meet the requirements of various bandwidth-intensive applications such as cloud expansion data centers, internet switching, host hosting services, service provider networks and the like, and the port cost is greatly reduced, so that the 200Gb/s ethernet network will be widely applied in the future.
The core part of the ethernet technology is the physical layer, which is the basis of the whole system and is responsible for ensuring that the original data can be transmitted on various physical media, and providing a reliable environment for data communication. The Physical Coding Sublayer (PCS) is the key of the physical layer, and the physical coding sublayer includes a sending layer, a PMA sublayer and a receiving layer, and data needs to pass through in sequence to complete transmission. Therefore, the normal transmission of data is ensured, the PCS sublayer needs to be detected urgently, and how to quickly and accurately detect the logic function of the PCS sublayer circuit of the 200Gb/s Ethernet is a problem which needs to be mainly solved in the popularization process of the 200Gb/s Ethernet.
Disclosure of Invention
The present invention is directed to provide a method, an apparatus, an electronic device and a storage medium for detecting a PCS sublayer logic function, which can detect the PCS sublayer logic function quickly and accurately.
In order to achieve the purpose, the invention discloses a method for detecting the logic function of a PCS sublayer, which comprises the following steps:
generating a first test stimulus, the first test stimulus comprising a data block and/or a control block;
the PCS sublayer sending end receives the first test excitation and encodes the first test excitation to obtain encoded data, and a plurality of distribution data which are correspondingly distributed to a plurality of sending channels are obtained according to the encoded data;
delaying and/or scrambling the order of at least part of the distribution data to obtain scrambled data;
the PCS sublayer receiving end receives and restores the disturbed data to obtain restored data;
comparing the restored data with a second test stimulus, the second test stimulus being the first test stimulus or the same as the first test stimulus.
Optionally, the method for detecting a logic function of the PCS sublayer further includes:
the second test stimulus and the restored data are generated synchronously.
Optionally, the PCS sublayer receiving end includes a plurality of receiving channels, and each receiving channel is preset to correspond to each transmitting channel one to one;
said "delaying and/or scrambling at least part of said distribution data to obtain scrambled data" comprises:
and transmitting at least part of the distribution data output by the sending channel to the receiving channel different from the receiving channel preset to correspond to the sending channel outputting the distribution data.
Optionally, the receiving end of the "PCS sublayer receives and restores the scrambled data to obtain restored data" includes:
and adjusting the corresponding relation of the receiving channels so that the receiving channel for receiving the distribution data corresponds to the sending channel for sending the distribution data.
Optionally, the distribution data comprises channel data and control signals.
In order to achieve the above object, the present invention further discloses a device for detecting the logic function of the PCS sublayer, comprising:
an excitation module for generating a first test excitation, the first test excitation comprising a data block and/or a control block;
a sending module, configured to receive the first test stimulus and encode the first test stimulus by a PCS sublayer sending end to obtain encoded data, and obtain, according to the encoded data, multiple pieces of distribution data that are correspondingly allocated to multiple sending channels;
a scrambling module for delaying and/or scrambling an order of at least part of the distribution data to obtain scrambled data;
the recovery module is used for receiving and recovering the disturbed data by the PCS sublayer receiving end to obtain recovered data;
an analysis module to compare the restored data to a second test stimulus, the second test stimulus being the first test stimulus or the same as the first test stimulus.
Optionally, the detecting device for the PCS sublayer logic function further includes:
the second test stimulus and the restored data are generated synchronously.
Optionally, the PCS sublayer receiving end includes a plurality of receiving channels, and each receiving channel is preset to correspond to each transmitting channel one to one;
said "delaying and/or scrambling at least part of said distribution data to obtain scrambled data" comprises:
and transmitting at least part of the distribution data output by the sending channel to the receiving channel different from the receiving channel preset to correspond to the sending channel outputting the distribution data.
In order to achieve the above object, the present invention also discloses an electronic device, comprising:
a processor;
a memory having stored therein executable instructions of the processor;
wherein the processor is configured to perform the detection method of PCS sublayer logic functions as described above via execution of the executable instructions.
In order to achieve the above object, the present invention also discloses a computer readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the method for detecting the logic function of the PCS sublayer as described above.
The method for detecting the logic function of the PCS sublayer comprises the steps of firstly generating a first test excitation, coding the first test excitation by the transmitting end of the PCS sublayer to obtain a plurality of distribution data correspondingly distributed to a plurality of transmitting channels, then delaying and/or scrambling at least part of the distribution data, restoring the scrambled data by the receiving end of the PCS sublayer, and finally comparing the restored data with a second test excitation, wherein the second test excitation is the first test excitation or is the same as the first test excitation. The invention delays and/or disturbs the sequence of at least part of the distributed data to achieve the effect of delaying and/or disordering when the analog data passes through the PMA sublayer, thereby preventing the data from directly passing through the PMA sublayer and being beneficial to quickly and accurately detecting the logic function of the PCS sublayer.
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Fig. 1 is a flowchart illustrating a method for detecting a logic function of a PCS sublayer according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a detection apparatus for detecting the logic function of the PCS sublayer according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of an electronic device according to an embodiment of the invention.
Detailed Description
In order to explain technical contents, structural features, implementation principles, and objects and effects of the present invention in detail, the following detailed description is given with reference to the accompanying drawings in combination with the embodiments.
Referring to fig. 1, the present invention discloses a method for detecting a logic function of a PCS sublayer, comprising:
101. a first test stimulus is generated, the first test stimulus comprising a data block and/or a control block.
Specifically, the first test stimulus may be composed of a data block, or may be composed of a control block, or may be composed of a data block and a control block. The data block comprises pseudo random codes, and the control block comprises an error control block, an idle control block, a continuous set control block, a termination control block and a starting control block.
Further, the first test stimulus is generated by a stimulus transmitter comprising a first counter, a pseudo-random code generator and a stimulus selector. When the excitation transmitter is started, the first counter starts to count, and the counting range of the first counter can be set according to the number of test excitations required to be generated. The pseudo-random code generator is embodied as a PRBS15 pseudo-random code generator consisting of 15 shift registers, which generates pseudo-random codes, which are treated as data blocks. The excitation selector selects a corresponding control block, data block or corresponding control signal according to the corresponding first counter count value, wherein the control signal comprises a clock signal, a reset signal, a data signal, a start signal, an end signal and an effective signal.
When the excitation transmitter is started, the reset signal and the clock signal are both set to be 0, meanwhile, the data signal and the valid signal are also both set to be 0, the PRBS15 pseudo random code generator is started, and the excitation transmitter enters normal operation. For example, to test 200Gb/s Ethernet PCS sub-layer circuitry, the stimulus selector selects 8 control blocks, which may be randomly selected among an error control block, an idle control block, a superset control block, a termination control block, and an enable control block, when the count of the first counter is 0 and 1, but typically the last control block should be the enable control block to ensure that the test stimulus enters the enabled state. When the count value of the first counter is greater than 3, the excitation selector selects 256-bit data (consisting of 4 pieces of 64-bit data) randomly generated by the PRBS15 pseudo random code generator. When the count value of the first counter is 100, a termination control block, an idle control block and a start control block are inserted again to detect whether the interrupted data transmission process is recovered to the normal transmission state.
102. The PCS sublayer transmitting end receives the first test excitation and encodes the first test excitation to obtain encoded data, and a plurality of distribution data which are correspondingly distributed to a plurality of transmitting channels are obtained according to the encoded data.
Specifically, the first test stimulus is encoded using a 64B/66B encoding scheme.
Because the excitation selector generates 4 first test excitations of 64 bits, a 64B/66B coding mode is adopted for coding, and the 4 first test excitations of 64 bits are coded into 4 data of 66 bits.
Because different state machines are output when the 64B/66B coding is adopted, and different state machines are corresponding to different data blocks and/or control blocks when the data blocks and/or the control blocks are received, for example, the data blocks and the control blocks are in a transmission state when the data blocks are received, and different control blocks are also corresponding to different states, such as a starting state, an ending state and the like, the control blocks are introduced in the test excitation transmission process to judge whether the coding is in a normal operation state or not.
Further, 4 pieces of 66-bit data are coded into 257-bit data through 256/257B transcoding, so that the process of linear coding is reduced.
Further, 257bit parallel scrambling is performed on 257bit data to maintain direct current balance.
Furthermore, an alignment mark is inserted into 257bit data, so that the data is conveniently positioned, and subsequent processing is facilitated. Wherein, the alignment mark can be composed of 4 257bit blocks, and one alignment mark is inserted every 81920 257bit data.
Then, 257bit data after inserting the alignment mark is correspondingly distributed to a plurality of sending channels.
For example, to detect a 200Gb/s ethernet PCS sublayer circuit, a transmitting end of a PCS sublayer is provided with 8 transmitting channels, and first, the transmitting end of the PCS sublayer receives a first test stimulus a, then performs 64B/66B encoding, 256/257B transcoding, parallel scrambling, insertion of an alignment mark, and the like on the first test stimulus a to obtain distribution data a1, a2, A3, a4, a5, A6, a7, and A8, and then respectively transmits the distribution data a1, a2, A3, a4, a5, A6, a7, and A8 to the corresponding transmitting channels B1, B2, B3, B4, B5, B6, B7, and B8.
103. Delaying and/or scrambling the order of at least part of the distributed data to obtain scrambled data.
In the actual PCS sublayer, after the data is processed by the PCS sublayer sending layer, the data needs to be transmitted to the next layer, and the data needs to be processed by other layers and then received and restored by the PCS sublayer receiving layer. In the data transmission between layers, the data may have deviation, asynchronism and disorder, so that at least part of distributed data is delayed and/or scrambled to obtain scrambled data, so as to simulate the transmission of data between different layers, avoid the data from directly passing through a plurality of physical layers and improve the test efficiency.
At least part of the distributed data may be delayed, or the scrambling order may be performed, or the delay and the scrambling order may be performed simultaneously. Specifically, the delay time for distributing data is set according to the requirement, such as one clock cycle, two clock cycles, and the like.
In some embodiments, the PCS sublayer receiving end includes a plurality of receiving channels, and each receiving channel is preset to correspond to each transmitting channel one by one.
The above "delaying and/or scrambling at least part of the distribution data to obtain scrambled data" includes:
and transmitting at least part of the distribution data output by the sending channel to a receiving channel different from a receiving channel preset to correspond to the sending channel outputting the distribution data.
Because the receiving channels are preset to be in one-to-one correspondence with the sending channels, the distributed data output by at least part of the sending channels are transmitted to the receiving channels different from the receiving channels preset to be corresponding to the sending channels outputting the distributed data, so that the distributed data are disturbed in sequence, the disorder phenomenon of the data during transmission among different layers is well simulated, the data are prevented from directly passing through a plurality of physical layers, and the test efficiency and the test reliability are improved.
Specifically, the distribution data includes channel data and control signals. The control signals include a start signal, an end signal, a valid signal, etc., and the channel data and the control signals may be delayed and/or scrambled in sequence, respectively.
For example, referring to the PCS sublayer circuit, the PCS sublayer receiving end is also provided with 8 receiving channels, and the 8 receiving channels are preset to correspond to the transmitting channels one by one, for example, the receiving channel C1 corresponds to the transmitting channel B1, the receiving channel C2 corresponds to the transmitting channel B2, the receiving channel C3 corresponds to the transmitting channel B3, and the like. And then at least part of the distribution data is transmitted to a receiving channel different from the receiving channel corresponding to the preset. For example, the distribution data a1 in the sending channel B1 is transmitted to the receiving channel C3, the distribution data A3 in the sending channel B3 is transmitted to the receiving channel C1, and the like, and further the distribution data is scrambled, and in addition, the distribution data output by a part of the sending channels may still be transmitted to the receiving channels corresponding to the preset, for example, the distribution data a2 in the sending channel B2 may still be transmitted to the receiving channel C2 corresponding to the preset, and the like. Of course, the specific transmission form of the sending channel and the receiving channel is not limited herein, and only the distribution data output by at least part of the sending channel needs to be transmitted to the receiving channel different from the receiving channel preset to correspond to the sending channel outputting the distribution data.
104. And the PCS sublayer receiving end receives and restores the scrambled data to obtain restored data.
In some embodiments, the receiving end of the PCS sublayer receives and restores the scrambled data to obtain restored data, including:
the correspondence relationship of the receiving channels is adjusted so that the receiving channel that receives the distribution data corresponds to the transmitting channel that transmits the distribution data.
By adjusting the corresponding relation of the receiving channels, the disturbed data can be better restored, and the efficiency of restoring the data is improved.
Continuing with the example with reference to the PCS sublayer circuitry, the distribution data a1 in the transmit channel B1 is transmitted to the receive channel C3, and the distribution data A3 in the transmit channel B3 is transmitted to the receive channel C1. Next, the correspondence relationship between the reception channels is adjusted, and at this time, the reception channel C3 that has received the distribution data a1 is adjusted to correspond to the transmission channel B1 that has transmitted the distribution data a1, and the reception channel C1 that has received the distribution data A3 is adjusted to correspond to the transmission channel B3 that has transmitted the distribution data A3, thereby restoring the scrambled data well. Of course, the specific transmission modes of the sending channel and the receiving channel are not limited herein.
Further, 256/257B inversion codes and 64B/66B decoding are adopted to decode the restored data. 256/257B inversion code converts the output restored data (257bit data) into 4 66bit data after adjusting the corresponding relationship of the receiving channel, and the 4 66bit data are decoded into 4 64bit data according to the 64B/66B decoding mode, which is convenient for the comparison between the following data.
105. The restored data is compared to a second test stimulus, which is the first test stimulus or is the same as the first test stimulus.
Specifically, the detection result includes a functional correctness and a functional error. If the reduction data is the same as the second test excitation, the detection result is correct in function; and if the restored data is inconsistent with the second test excitation, the detection result is a functional error.
The second test stimulus may be the first test stimulus, or may be the same stimulus as the first test stimulus.
In some embodiments, the method for detecting the logic function of the PCS sublayer further comprises:
the second test stimulus and the recovery data are generated synchronously.
The second test excitation is synchronously generated when the reduction data is output, so that the test excitation is output accurately, the loss of the test excitation or the reduction data is avoided, the detection efficiency is improved, and meanwhile, the second test excitation and the reduction data are conveniently and directly compared to obtain a detection result quickly.
Specifically, when the sending end of the PCS sublayer receives a first test stimulus, the stimulus transmitter is started at a preset time interval to generate a second test stimulus identical to the first test stimulus, and the preset time interval is set according to a time period of the PCS sublayer for test stimulus processing. And when the PCS sublayer finishes the data processing of the first test excitation and outputs the restored data, the excitation transmitter is started again to synchronously generate a second test excitation which is the same as the first test excitation, and the restored data and the second test excitation are directly compared to quickly obtain a detection result.
Continuing to refer to the above PCS sublayer circuit for example, the excitation transmitter further includes a second counter, assuming that the time period of the test excitation processing performed by the PCS sublayer is specifically 135 clock periods, after the excitation transmitter is initialized, the first counter and the second counter start counting at the same time, the excitation selector generates the first test excitation according to the corresponding first counter count value, the PCS sublayer performs data processing on the first test excitation, and when the second counter counts to 135, the excitation transmitter is reused to generate the second test excitation identical to the first test excitation. The second test stimulus generated here is 135 clock cycles later than the first test stimulus, and is output in synchronization with the recovered data output by the PCS sublayer after processing the first test stimulus.
The method for detecting the logic function of the PCS sublayer comprises the steps of firstly generating a first test excitation, coding the first test excitation by the transmitting end of the PCS sublayer to obtain a plurality of distribution data correspondingly distributed to a plurality of transmitting channels, then delaying and/or scrambling at least part of the distribution data, restoring the scrambled data by the receiving end of the PCS sublayer, and finally comparing the restored data with a second test excitation, wherein the second test excitation is the first test excitation or is the same as the first test excitation. The invention delays and/or disturbs the sequence of at least part of the distributed data to achieve the effect of delaying and/or disordering when the analog data passes through the PMA sublayer, thereby preventing the data from directly passing through the PMA sublayer and being beneficial to quickly and accurately detecting the logic function of the PCS sublayer.
Referring to fig. 2, the present invention further discloses a detection apparatus for detecting the logic function of the PCS sublayer, which includes an excitation module 10, a sending module 11, a scrambling module 12, a restoring module 13, and an analysis module 14.
The stimulus module 10 is configured to generate a first test stimulus, which comprises a data block and/or a control block.
The sending module 11 is configured to receive the first test stimulus and encode the first test stimulus by the PCS sublayer sending end to obtain encoded data, and obtain, according to the encoded data, a plurality of distribution data that are correspondingly allocated to the plurality of sending channels.
Scrambling module 12 is configured to delay and/or scramble the order of at least a portion of the distributed data to obtain scrambled data.
The restoring module 13 is used by the PCS sublayer receiving end to receive and restore the scrambled data to obtain restored data.
The analysis module 14 is configured to compare the recovered data with a second test stimulus, the second test stimulus being the first test stimulus or being the same as the first test stimulus.
Further, the detection apparatus for the PCS sublayer logic function further includes:
the second test stimulus and the recovery data are generated synchronously.
Further, the PCS sublayer receiving end includes a plurality of receiving channels, and each receiving channel is preset to correspond to each transmitting channel one to one.
The above "delaying and/or scrambling at least part of the distribution data to obtain scrambled data" includes:
and transmitting at least part of the distribution data output by the sending channel to a receiving channel different from a receiving channel preset to correspond to the sending channel outputting the distribution data.
For a detailed description of the detecting device for the PCS sublayer logic function, the above detecting method for the PCS sublayer logic function is described in detail, and is not repeated herein.
Referring to fig. 3, an embodiment of the present invention further discloses an electronic device, which includes:
a processor 21;
a memory 20 having stored therein executable instructions of the processor 21;
the processor 21 is configured to execute the detection method of the PCS sublayer logic function through executing the executable instructions.
The embodiment of the invention also discloses a computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, and the computer program is executed by a processor to realize the detection method of the PCS sublayer logic function.
The embodiment of the invention also discloses a computer program product or a computer program, which comprises computer instructions, and the computer instructions are stored in a computer readable storage medium. The processor of the electronic device reads the computer instructions from the computer-readable storage medium, and executes the computer instructions, so that the electronic device executes the detection method of the logic function of the PCS sublayer.
It should be understood that in the embodiments of the present invention, the Processor may be a Central Processing Unit (CPU), and the Processor may also be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware associated with computer program instructions, and the programs can be stored in a computer readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above disclosure is only a preferred embodiment of the present invention, and should not be taken as limiting the scope of the invention, so that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.
Claims (10)
1. A method for detecting the logic function of a PCS sublayer is characterized by comprising the following steps:
generating a first test stimulus, the first test stimulus comprising a data block and/or a control block;
the PCS sublayer sending end receives the first test excitation and encodes the first test excitation to obtain encoded data, and a plurality of distribution data which are correspondingly distributed to a plurality of sending channels are obtained according to the encoded data;
delaying and/or scrambling the order of at least part of the distribution data to obtain scrambled data;
the PCS sublayer receiving end receives and restores the disturbed data to obtain restored data;
comparing the restored data with a second test stimulus, the second test stimulus being the first test stimulus or the same as the first test stimulus.
2. The method for detecting the logic function of the PCS sublayer of claim 1 further comprising:
the second test stimulus and the restored data are generated synchronously.
3. The method of testing the logic function of the PCS sub-layer of claim 1,
the PCS sublayer receiving end comprises a plurality of receiving channels, and each receiving channel is preset to be in one-to-one correspondence with each sending channel;
said "delaying and/or scrambling at least part of said distribution data to obtain scrambled data" comprises:
and transmitting at least part of the distribution data output by the sending channel to the receiving channel different from the receiving channel preset to correspond to the sending channel outputting the distribution data.
4. The method of testing the logic functions of the PCS sub-layer of claim 3,
the receiving end of the PCS sublayer receives and restores the scrambled data to obtain restored data includes:
and adjusting the corresponding relation of the receiving channels so that the receiving channel for receiving the distribution data corresponds to the sending channel for sending the distribution data.
5. The method of testing the logic function of the PCS sub-layer of claim 1,
the distribution data includes channel data and control signals.
6. An apparatus for detecting logic functions of a PCS sub-layer, comprising:
an excitation module for generating a first test excitation, the first test excitation comprising a data block and/or a control block;
a sending module, configured to receive the first test stimulus and encode the first test stimulus by a PCS sublayer sending end to obtain encoded data, and obtain, according to the encoded data, multiple pieces of distribution data that are correspondingly allocated to multiple sending channels;
a scrambling module for delaying and/or scrambling an order of at least part of the distribution data to obtain scrambled data;
the recovery module is used for receiving and recovering the disturbed data by the PCS sublayer receiving end to obtain recovered data;
an analysis module to compare the restored data to a second test stimulus, the second test stimulus being the first test stimulus or the same as the first test stimulus.
7. The apparatus for detecting the logic function of the PCS sublayer of claim 6 further comprising:
the second test stimulus and the restored data are generated synchronously.
8. The apparatus for detecting the logic function of the PCS sub-layer according to claim 6,
the PCS sublayer receiving end comprises a plurality of receiving channels, and each receiving channel is preset to be in one-to-one correspondence with each sending channel;
said "delaying and/or scrambling at least part of said distribution data to obtain scrambled data" comprises:
and transmitting at least part of the distribution data output by the sending channel to the receiving channel different from the receiving channel preset to correspond to the sending channel outputting the distribution data.
9. An electronic device, comprising:
one or more processors;
a memory;
and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs comprising instructions for performing a method of detection of PCS sublayer logic functions as in any of claims 1 to 5.
10. A computer-readable storage medium comprising a test computer program executable by a processor to perform a method for detecting a logical function of the PCS sublayer of any one of the claims 1 to 5.
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| CN214067321U (en) * | 2020-10-10 | 2021-08-27 | 北京国科天迅科技有限公司 | Detection circuit for verifying logic function of PCS sublayer |
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