CN113972266A - HEMT device with tunneling enhanced vertical structure - Google Patents

HEMT device with tunneling enhanced vertical structure Download PDF

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Publication number
CN113972266A
CN113972266A CN202010714612.2A CN202010714612A CN113972266A CN 113972266 A CN113972266 A CN 113972266A CN 202010714612 A CN202010714612 A CN 202010714612A CN 113972266 A CN113972266 A CN 113972266A
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layer
substrate
hemt device
barrier layer
gallium nitride
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钟敏
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Wuhu Qidi Semiconductor Co ltd
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Wuhu Qidi Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7788—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H01L29/475—Schottky barrier electrodes on AIII-BV compounds

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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention provides a HEMT device with a tunneling enhanced vertical structure. The HEMT device includes: a substrate; a buffer layer disposed on one surface of the substrate; the current blocking layer is arranged on the surface of the buffer layer, which is far away from the substrate; a channel layer covering the diffusion preventing layer, the current blocking layer and a portion of the buffer layer; the barrier layer is arranged on the surface of the channel layer far away from the substrate; the anti-diffusion layer is arranged between the current blocking layer and the barrier layer; the source electrode is arranged on the surface, far away from the current blocking layer, of the channel layer and is provided with a first extending portion, and the first extending portion covers part of the surface of the barrier layer and forms Schottky contact with the barrier layer; the insulating medium layer covers a part of the barrier layer and the other part of the buffer layer; the grid electrode is arranged on the surface of the insulating medium layer, which is far away from the buffer layer, and is arranged on two sides of the source electrode; and the drain electrode is arranged on the surface of the substrate far away from the buffer layer. According to the HEMT device with the vertical structure, the contact area of the source electrode and the barrier layer in the horizontal direction is prolonged, and the extended part of metal and the barrier layer form Schottky contact so as to improve the reverse blocking property of the device.

Description

HEMT device with tunneling enhanced vertical structure
Technical Field
The invention relates to the technical field of semiconductor device design, in particular to a HEMT device with a tunneling enhanced vertical structure.
Background
Compared with the traditional gallium nitride (GaN) High Electron Mobility Transistor (HEMT) device with a transverse structure, the withstand voltage of the GaN HEMT device with a vertical structure is not limited by the transverse size any more, and the withstand voltage of the device is mainly borne by the longitudinal distance between the grid and the drain, so the transverse size of the device can be designed to be very small, and the chip area is effectively saved. Meanwhile, the drain electrode with high voltage is manufactured below the device, so that the whole surface of the device can be in a low electric field state, and the concentration of an electric field on the edge of the grid electrode is effectively avoided.
Disclosure of Invention
The present invention has been completed based on the following findings of the inventors:
the inventor of the invention finds that when the HEMT device is applied to a high-power switching circuit, the HEMT device with an enhanced vertical structure can be realized through a tunneling mechanism for the design simplicity and safety of the circuit. However, when the current tunneling method is adopted to realize the enhancement type device, the forward conduction performance and the reverse blocking performance of the device are in contradiction. Therefore, the inventor designs a tunneling enhancement type HEMT device with a vertical structure, which improves reverse blocking performance, and the source electrode is made to be L-shaped or T-shaped, so that the source electrode metal is contacted with the barrier layer in the horizontal direction to form a metal-AlGaN junction.
In a first aspect of the invention, a tunneling-enhanced vertical HEMT device is presented.
According to an embodiment of the present invention, the HEMT device includes: a substrate; a buffer layer disposed on one surface of the substrate; the current blocking layer is arranged on the surface of the buffer layer far away from the substrate; a diffusion prevention layer disposed between the current blocking layer and the barrier layer; a channel layer covering the diffusion preventing layer, the current blocking layer and a portion of the buffer layer; a barrier layer disposed on a surface of the channel layer remote from the substrate; a source disposed on a surface of the channel layer distal from the current blocking layer, the source having a first extension that covers a portion of a surface of the barrier layer and forms a Schottky contact with the barrier layer; an insulating dielectric layer covering a portion of the barrier layer and another portion of the buffer layer; the grid electrodes are arranged on the surface, far away from the buffer layer, of the insulating medium layer and are arranged on two sides of the source electrode; the drain electrode is arranged on the surface of the substrate far away from the buffer layer.
According to the HEMT device with the vertical structure, the grid electrodes are designed on two sides close to the source electrode, the current blocking layer is designed below the source electrode, the drain electrode is designed on the back surface of the substrate, the tunneling mechanism is utilized to realize the enhancement type device, the contact area of the source electrode and the barrier layer in the horizontal direction is also prolonged, and the prolonged part of metal and the barrier layer form Schottky contact, so that the reverse blocking performance of the device is improved, and the forward conduction performance and the reverse blocking performance of the device are taken into consideration.
In addition, the vertical HEMT device according to the above embodiment of the present invention may further have the following additional technical features:
according to the embodiment of the invention, the gate electrode is provided with the second extension part, and the orthographic projection of the second extension part on the substrate is partially overlapped with the orthographic projection of the first extension part on the substrate.
According to an embodiment of the invention, the material forming the substrate comprises at least one of n-type or intrinsic gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium and silicon.
According to an embodiment of the present invention, a material forming the buffer layer includes at least one of n-type or unintentionally doped gallium nitride and indium gallium nitride.
According to the embodiment of the invention, the material for forming the current blocking layer comprises at least one of p-type gallium nitride, p-type indium gallium nitride and silicon dioxide, and the thickness of the current blocking layer is 50-1000 nm.
According to an embodiment of the present invention, a material forming the diffusion preventing layer includes aluminum nitride, and a thickness of the diffusion preventing layer is not more than 5 nm.
According to an embodiment of the present invention, a material forming the channel layer includes at least one of unintentionally doped gallium nitride and indium gallium nitride.
According to an embodiment of the present invention, a material forming the barrier layer includes InmAlnGa(1-m-n) N, wherein N is more than or equal to 0.15 and less than or equal to 0.80, m is more than or equal to 0 and less than or equal to 0.45, and the thickness of the barrier layer is not less than 20 nm.
According to the embodiment of the invention, the material for forming the insulating medium layer comprises at least one of aluminum oxide, hafnium oxide, titanium dioxide and gallium oxide.
According to an embodiment of the present invention, the drain electrode is an ohmic contact, and a material forming the drain electrode includes at least one of titanium, aluminum, nickel, gold, and tantalum; the source electrode is a Schottky contact, and the material forming the source electrode comprises at least one of titanium, aluminum, nickel and tantalum; the material forming the gate electrode includes at least one of nickel, gold, palladium, and platinum.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing aspects of the invention are explained in the description of the embodiments with reference to the following drawings, in which:
FIG. 1 is a schematic cross-sectional view of a typical vertical HEMT device;
fig. 2 is a schematic cross-sectional view of a HEMT device of the tunneling-enhanced vertical structure in accordance with one embodiment of the present invention;
fig. 3 is a schematic cross-sectional view of a HEMT device of a tunneling-enhanced vertical structure according to another embodiment of the present invention;
fig. 4 is a schematic cross-sectional view of a HEMT device of a tunneling-enhancement vertical structure according to another embodiment of the present invention.
Reference numerals
100 substrate
200 buffer layer
300 Current Barrier layer
310 diffusion barrier layer
400 channel layer
500 source electrode
510 first extension part
600 barrier layer
700 insulating dielectric layer
800 grid electrode
801 first grid
802 second gate
8021 second extension
810 gate insulating layer
900 drain electrode
Detailed Description
The following examples of the present invention are described in detail, and it will be understood by those skilled in the art that the following examples are intended to illustrate the present invention, but should not be construed as limiting the present invention. Unless otherwise indicated, specific techniques or conditions are not explicitly described in the following examples, and those skilled in the art may follow techniques or conditions commonly employed in the art or in accordance with the product specifications.
In one aspect of the invention, a tunneling-enhanced vertical HEMT device is presented.
In the course of research, the inventors of the present invention found that, in the structure of a classical vertical HEMT device reported by Masakazu Kanechika in 2007, referring to fig. 1, a source electrode 500 is located on the left and right sides of the surface of the device, a gate electrode 800 is located in the middle, and a drain electrode 900 is located below a substrate 100. When the device is operated, electrons enter the channel layer 400 from the source 500, and under the action of the Current Blocking Layers (CBLs) 300 of the two p-type GaN layers, electron current a (shown by a solid arrow in fig. 1) passes through the aperture in the middle and then enters the drain 900 through the buffer layer 200. Since the high-voltage drain 900 is formed under the device, the entire surface of the device can be in a low electric field state, thereby effectively avoiding the concentration of an electric field at the edge of the gate 800. However, the structure is still a depletion-mode GaN HEMT device, so that the technical difficulty of turning off is existed.
According to an embodiment of the present invention, the inventors have devised a HEMT device of the tunneling-enhancement type vertical structure, with reference to fig. 2, which includes: a substrate 100, a buffer layer 200, a Current Blocking Layer (CBL)300, a diffusion preventing layer 310, a channel layer 400, a source electrode 500, a barrier layer 600, an insulating dielectric layer 700, a gate electrode 800, and a drain electrode 900; wherein the buffer layer 200 is disposed on one surface of the substrate 100; the current blocking layer 300 is disposed on the surface of the buffer layer 200 away from the substrate 100; the channel layer 400 covers the current blocking layer 300 and a portion of the buffer layer 200; the barrier layer 600 is disposed on a surface of the channel layer 400 away from the substrate 100; the diffusion preventing layer 310 is disposed between the current blocking layer 300 and the barrier layer 600; the source electrode 500 is disposed on a surface of the channel layer 400 away from the current blocking layer 300, the source electrode 500 has a first extension portion 510, and the first extension portion 510 covers a portion of a surface of the barrier layer 600, the first extension portion 510 forming a schottky contact with the barrier layer 600; an insulating dielectric layer 700 covers the barrier layer 600 and another part of the buffer layer 200; the gate 800 is arranged on the surface of the insulating medium layer 700 far away from the buffer layer 200, and the gate 800 is arranged on two sides of the source 500; and the drain 900 is disposed on the surface of the substrate 100 away from the buffer layer 200.
The gate 800 is designed near both sides of the source 500, the current blocking layer 300 is designed under the source 500, and the drain 900 is designed at the back of the substrate 100. The contact surface of the barrier layer 600 and the channel layer 400 generates a two-dimensional electron gas (2DEG), when the source electrode 500 contacts the 2DEG, a schottky contact is formed, electrons in the 2DEG enter the source electrode 500, a space charge region is formed on the 2DEG side of the metal-2 DEG junction, and the device is in a normally-off state. When a positive bias is applied to the grid electrode close to one side of the metal-2 DEG junction, the 2DEG side of the metal-2 DEG junction is modulated to be heavily doped, so that the width of a depletion region of the junction is reduced, and when the width of the depletion region is reduced to a certain degree, more electrons participate in tunneling to form tunneling current. As such, a tunneling current b (shown by a solid arrow in fig. 2) generated by the tunneling mechanism flows into the buffer layer 200 from both sides of the current blocking layer 300, and passes through the buffer layer 200 and the substrate 100 to reach the drain 900.
Although the enhanced characteristics of the device can be achieved by using the current tunneling method, there is a contradiction between the forward-direction conducting performance and the reverse-direction blocking performance of the device. Specifically, the forward conduction of the device is completed by a gate voltage modulated tunneling transport mechanism, and in order to increase the tunneling probability, a source metal with a lower metal work function is preferably selected to form a schottky contact, so as to reduce the turn-on voltage. However, this approach would significantly reduce the reverse blocking capability of the device, resulting in a problem of large off-state leakage current. Therefore, the inventor also makes the source electrode 500 into a lying "L" shape or a lying "T" shape, so that the source electrode 500 and the barrier layer 600 are in contact in the horizontal direction to form a metal-AlGaN junction, and since the forbidden bandwidth of AlGaN is large, the newly added metal-AlGaN junction can be regarded as a capacitor when being reversely blocked, thereby improving the reverse blocking performance of the device.
According to an embodiment of the present invention, the material forming the substrate 100 may include at least one of n-type or intrinsic gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon, so that the performance of the HEMT device fabricated on the substrate 100 may be better. In some embodiments of the present invention, the material of the substrate 100 may be n-type gan, so that the substrate 100 has a better self-supporting function.
According to an embodiment of the present invention, the material forming the buffer layer 200 may include at least one of n-type or unintentionally doped gallium nitride (GaN) and indium gallium nitride (InGaN), so that the buffer layer 200 of the above material may be directly grown on the substrate 100, thereby better providing a flow path for the carrier conduction of the HEMT device.
According to an embodiment of the present invention, the material forming the current blocking layer 300 may include one of p-type gallium nitride (p-GaN), p-type indium gallium nitride (p-InGaN), and silicon dioxide, and the thickness of the current blocking layer may be 50 to 1000nm, so that a layer of the current blocking layer 300 may be continuously grown on the buffer layer 200 by using the in-situ Mg and Zn doping technology, and a specific growth method may adopt MOCVD, MBE, ALD, etc., so that the tunneling current of the HEMT device may flow into the buffer layer 200 from both sides of the current blocking layer 300.
According to an embodiment of the present invention, a material forming the channel layer 400 may include at least one of unintentionally doped gallium nitride (GaN) and indium gallium nitride (InGaN), and thus, the channel layer 400 may be grown on the current blocking layer 300 using a double epitaxy technique.
According to an embodiment of the invention, the material forming barrier layer 600 may include InmAlnGa(1-m-n)N, wherein N is greater than or equal to 0.15 and less than or equal to 0.80, m is greater than or equal to 0 and less than or equal to 0.45, and the thickness of the barrier layer 600 can be not less than 20nm, so that the barrier layer 600 grows on the channel layer 400 and can form a heterojunction with the channel layer 400 made of GaN or InGaN materials, and the forbidden bandwidth of the barrier layer 600 is greater than that of the channel layer.
According to an embodiment of the present invention, a material forming the insulating dielectric layer 700 may include aluminum oxide (Al)2O3) Hafnium oxide (HfO)2) Titanium dioxide (TiO)2) And gallium oxide (Ga)2O3) And thus, the source electrode 500 may be better blocked from the gate electrode 800 by the insulating dielectric layer 700 using the above-described insulating material.
According to an embodiment of the present invention, the source electrode 500 is a schottky contact, and the material forming the source electrode 500 includes at least one of titanium, aluminum, nickel, and tantalum. Therefore, the metal-2 DEG junction with a lower potential barrier can not be subjected to reverse breakdown through the protection of the metal-AlGaN junction capacitor. Specifically, silicon dioxide or silicon nitride can be used as a hard mask, dry etching (ICP, RIE, ECR, IBE, etc.) is performed on the insulating dielectric layer 700 and the barrier layer 600 in the source window, and the etching is performed in two steps, the etching width of the insulating dielectric layer 700 is not less than the etching width of the barrier layer 600, the depth of the etching insulating dielectric layer 700 is not less than the thickness of the insulating dielectric layer 700, so that the insulating dielectric layer 700 is properly and completely etched, and the depth of the etching barrier layer 600 is not less than the thickness of the barrier layer 600, so that the barrier layer 600 is properly and completely etched; the source electrode 500 is obtained by depositing metal by electron beam evaporation, magnetron sputtering or a combination thereof, and then forming schottky contact by annealing.
According to an embodiment of the present invention, a material forming the gate electrode 800 may include at least one of nickel, gold, palladium, and platinum. Therefore, the metal material with higher work function is selected to manufacture the grid electrode, so that the Schottky contact is formed better. In some embodiments of the present invention, the gate electrode 800 may have a second extension portion 8021, and an orthographic projection of the second extension portion 8021 on the substrate 100 is overlapped with an orthographic projection of the first extension portion 510 on the substrate 100, and the insulating medium layer 700 extends between the second extension portion 8021 and the first extension portion 510. Thus, the region where the second gate 802 partially overlaps the source electrode 500 forms a field plate like structure that can effectively clamp when the drain electrode 900 has a high voltage. Specifically, the gate 800 may be formed in the gate electrode window by using an electron beam evaporation technique or a magnetron sputtering technique. In some embodiments, referring to fig. 3, the plurality of gates may include a first gate 801 and a second gate 802, and the second gate 802 has a second extension 8021, and an orthogonal projection of the second extension 8021 on the substrate 100 coincides with an orthogonal projection of the first extension 510 on the substrate 100, and the insulating dielectric layer 700 extends between the second extension 8021 and the first extension 510. In other embodiments, referring to fig. 4, not only the second gate 802 has the second extension 8021, but also the first gate 801 may have the second extension 8021.
According to an embodiment of the present invention, the drain electrode 900 may be an ohmic contact, and a material forming the drain electrode 900 may include at least one of titanium, aluminum, nickel, gold, and tantalum. In this way, the drain electrode 900 may be obtained by depositing metal by electron beam evaporation, magnetron sputtering, or a combination thereof, and then annealing to form an ohmic contact.
In addition, the tunneling structure described above has the benefits of: 1. compared with the traditional vertical structure, only a layer of p-GaN grows in situ on the basis of preparing the substrate and the buffer layer and then the CBL below the source electrode is obtained by utilizing the etching technology, so that the lattice damage and the memory effect caused by the formation of the CBL by ion implantation can be avoided, and the side wall of the conductive aperture has a gap in the secondary epitaxial growth process to form a leakage channel; 2. compared with other common enhancement-mode realization technical means, the tunneling mechanism is utilized to realize the normally-off characteristic of the device, the doping activation process can be avoided, the channel layer of the 2DEG can be completely blocked, and the threshold voltage can be improved; in addition, the requirement on etching precision is not high, and the process difficulty is reduced; an ion implantation process is not available, so that damage to the barrier layer caused by ion implantation is avoided; 3. the special source electrode structure and/or the special grid electrode structure can improve the reverse blocking characteristic of the device on the premise of ensuring the forward conduction performance, so that the metal-2 DEG junction can be prevented from being subjected to reverse breakdown.
In summary, according to the embodiments of the present invention, the present invention provides a HEMT device with a vertical structure, wherein gates of the HEMT device are designed on two sides close to a source, a current blocking layer is designed below the source, and a drain is designed on a back surface of a substrate, so that a normally-off characteristic of the HEMT device is realized through a tunneling mechanism, a contact area between the source and a barrier layer in a horizontal direction is further extended, and an extended portion of metal forms a schottky contact with the barrier layer, so that a reverse blocking property of the HEMT device is improved, and a forward conduction property and a reverse blocking property of the HEMT device are considered at the same time.
In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims (10)

1. A HEMT device of a tunneling-enhanced vertical structure, comprising:
a substrate;
a buffer layer disposed on one surface of the substrate;
the current blocking layer is arranged on the surface of the buffer layer far away from the substrate;
a channel layer covering the diffusion preventing layer, the current blocking layer and a portion of the buffer layer;
a barrier layer disposed on a surface of the channel layer remote from the substrate;
a diffusion prevention layer disposed between the current blocking layer and the barrier layer;
a source disposed on a surface of the channel layer distal from the current blocking layer, the source having a first extension that covers a portion of a surface of the barrier layer and forms a Schottky contact with the barrier layer;
an insulating dielectric layer covering a portion of the barrier layer and another portion of the buffer layer;
the grid electrode is arranged on the surface, far away from the buffer layer, of the insulating medium layer and is arranged on two sides of the source electrode;
the drain electrode is arranged on the surface of the substrate far away from the buffer layer.
2. The HEMT device of claim 1, wherein said gate has a second extension, an orthographic projection of said second extension on said substrate coinciding with an orthographic projection of said first extension on said substrate.
3. The HEMT device of claim 1, wherein the material forming said substrate comprises at least one of n-type or intrinsic gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium and silicon.
4. The HEMT device of claim 1, wherein the material forming said buffer layer comprises at least one of n-type or unintentionally doped gallium nitride and indium gallium nitride.
5. The HEMT device according to claim 1, wherein a material forming the current blocking layer comprises at least one of p-type gallium nitride, p-type indium gallium nitride and silicon dioxide, and the thickness of the current blocking layer is 50-1000 nm.
6. The HEMT device of claim 2, wherein the material forming said diffusion barrier layer comprises aluminum nitride and the thickness of said diffusion barrier layer is no greater than 5 nm.
7. The HEMT device of claim 1, wherein the material forming said channel layer comprises at least one of unintentionally doped gallium nitride and indium gallium nitride.
8. The HEMT device of claim 1, wherein the material forming the barrier layer comprises InmAlnGa(1-m-n) N, wherein N is more than or equal to 0.15 and less than or equal to 0.80, m is more than or equal to 0 and less than or equal to 0.45, and the thickness of the barrier layer is not less than 20 nm.
9. The HEMT device of claim 1, wherein the material forming said insulating dielectric layer comprises at least one of aluminum oxide, hafnium oxide, titanium dioxide and gallium oxide.
10. The HEMT device of claim 1, wherein said drain is an ohmic contact and the material forming said drain comprises at least one of titanium, aluminum, nickel, gold and tantalum; the source electrode is a Schottky contact, and the material forming the source electrode comprises at least one of titanium, aluminum, nickel and tantalum; the material forming the gate electrode includes at least one of nickel, gold, palladium, and platinum.
CN202010714612.2A 2020-07-23 2020-07-23 HEMT device with tunneling enhanced vertical structure Pending CN113972266A (en)

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WO2012049892A1 (en) * 2010-10-13 2012-04-19 住友電気工業株式会社 Semiconductor device and method for producing same
US20130313561A1 (en) * 2012-05-25 2013-11-28 Triquint Semiconductor, Inc. Group iii-nitride transistor with charge-inducing layer
CN104992971A (en) * 2015-06-29 2015-10-21 电子科技大学 GaN vertical heterojunction field-effect transistor with composite low-K current barrier layer

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