CN113970877A - Photoetching process method for wafer number-carving area - Google Patents
Photoetching process method for wafer number-carving area Download PDFInfo
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- CN113970877A CN113970877A CN202111204293.1A CN202111204293A CN113970877A CN 113970877 A CN113970877 A CN 113970877A CN 202111204293 A CN202111204293 A CN 202111204293A CN 113970877 A CN113970877 A CN 113970877A
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- G—PHYSICS
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- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/16—Coating processes; Apparatus therefor
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/30—Imagewise removal using liquid means
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/38—Treatment before imagewise removal, e.g. prebaking
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
The invention discloses a photoetching process method for a wafer marking area, which comprises the steps of pretreating a wafer after light-tight media are deposited each time, coating photoresist on the pretreated wafer, and exposing the wafer marking area after the photoresist is coated; developing the wafer in the step S1, and removing the photoresist in the wafer marking area; and etching the wafer in the step S2 to obtain the wafer with clear carved number. The method carries out special exposure treatment on the surface of the wafer at the position of the mark, so that the position of the mark always keeps a certain depth-to-width ratio in the subsequent process, the effect of resolving the unclear mark by utilizing the light reflection law is far superior to that of the existing method, the feasibility of manually identifying the wafer mark is enhanced, the abnormal rate is reduced to the greatest extent, and the production efficiency is improved.
Description
Technical Field
The invention belongs to the technical field of chip manufacturing, and particularly belongs to a photoetching process method for a wafer number-carving area.
Background
In the production and processing process of semiconductor integrated circuit chips, in order to conveniently and manually identify wafers, marks and scale marks are marked on the front flat edge of the wafers during wafer throwing, the depth of the scale marks is about 3 microns, the width of the scale marks is about 40 microns, and the depth-to-width ratio is about 1: 13. the cross-section at the inscription is schematically shown in FIG. 1 below.
In a multi-layer metal wiring CMOS process, a chemical mechanical polishing process (CMP) is introduced for planarizing an oxide layer of a local interconnect. In practical production, before the contact hole is formed (i.e. the process in the dashed line frame at the top of fig. 2), the mark is subjected to CMP 1 time, and the aspect ratio is about 1: 13 to about 1: and 9.3, since the light-transmitting media such as silicon dioxide and silicon nitride are deposited at the carved positions, the manual identification is not influenced.
In the post-stage process (i.e., the process within the dashed line frame in the lower part of fig. 2) when the wafer enters the contact hole, the mark etching part undergoes multiple times of CMP, the aspect ratio of the mark etching part gradually becomes smaller and even zero, and the mark etching part is sputtered with opaque media such as titanium, titanium nitride, tungsten, aluminum, silicon, copper and the like in the subsequent metal interconnection process, so that the mark etching part is more difficult to identify manually and can not be identified in serious cases.
The traditional technology adopts a method of adding a pressure ring in a sputtering process, namely the pressure ring is used for blocking opaque media such as titanium, titanium nitride, tungsten, aluminum-silicon-copper and the like from being sputtered to a mark carving position, the method does not need to modify a sputtering machine table to generate high modification cost, and meanwhile, due to the fact that the pressure ring area and a non-pressure ring area have obvious steps, photoetching focusing failure is easily generated in the pressure ring area, and edge aggregation abnormal frequency of a subsequent photoetching exposure process is caused.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a photoetching process method for a wafer number-carving area, which increases the exposure of the number-carving area after the step of depositing opaque medium layers of titanium, titanium nitride, tungsten, aluminum, silicon, copper and the like on a wafer, solves the problem of difficulty in manually identifying the number-carving, saves the high equipment press ring modification cost caused by the fact that the number-carving of a multilayer metal wiring CMOS process product is not clear by a press ring method, and solves the technical problems of poor photoetching focus and the like caused by the press ring method. In order to achieve the purpose, the invention provides the following technical scheme: a photoetching process method for a wafer number-carving area comprises the following specific steps:
s1, preprocessing the wafer after the light-tight medium is deposited each time, coating photoresist on the preprocessed wafer, and exposing the wafer marking area after the photoresist is coated;
s2, developing the wafer in the step S1, and removing the photoresist in the wafer marking area;
s3, etching the wafer in the step S2 to obtain the wafer with clear carved number.
Further, in step S1, exposure is performed using a full-transmission reticle.
Further, in step S1, the front and the back of the fully transmissive reticle are made of common glass, and the back of the fully transmissive reticle is not sputtered with a chromium dioxide opaque coating.
Further, in step S1, exposure is performed only on the flat side of the wafer from left to right in accordance with the lithography view field.
Further, in step S1, the opaque medium includes titanium, titanium nitride, tungsten, or aluminum, silicon, and copper.
Further, in step S1, the pre-treatment is to sequentially perform hot plate treatment, HMDS treatment and cold plate treatment on the wafer.
Further, in step S2, before the development, PEB processing and cold plate processing are performed on the exposed wafer, and after the cold plate processing, the development is performed.
Further, in step S2, the developing step is to spray a developing solution on the wafer, the soaking time is 58S, and the developing is completed by spin-drying and flushing.
Compared with the prior art, the invention has at least the following beneficial effects:
the invention provides a photoetching process method for a wafer mark etching area, which solves the problem that the mark etching can not be manually identified after deposition of opaque media such as titanium nitride, aluminum silicon copper and the like by adopting the exposure method of the invention at the wafer flat edge mark etching position of a specific level in the production process of a multilayer metal wiring CMOS.
After the scheme provided by the invention is adopted by an online product, the problem of unclear mark etching identification does not occur, 3000 pieces of calculation are produced according to the month, once the mark etching is unclear, the edge is required to be independently exposed, developed and etched, the single piece reworking cost is calculated by 20 yuan, 6 ten thousand yuan is saved by monthly accumulation, and the invention has wide application range;
the invention adopts a full-transmission photoetching plate to expose the flat edge of the wafer which is not exposed after being coated with glue, the photoresist at the developed flat edge is removed by a developer, and then the lightproof media such as titanium, titanium nitride, tungsten, aluminum silicon copper and the like at the flat edge are also removed by etching due to the loss of the protection of the photoresist by an etching process, so that the technology of replacing a sputtering process to increase a pressure ring and blocking the lightproof media such as titanium, titanium nitride, tungsten, aluminum silicon copper and the like from sputtering to a mark position is adopted.
Drawings
FIG. 1 is a schematic cross-sectional view of a notch;
FIG. 2 is a flow diagram of a typical dual poly-tri-aluminum CMOS process;
FIG. 3 is a prior art wafer flat edge etching blur profile analysis diagram;
FIG. 4 is a schematic view of a prior art wafer flat edge with blurred engraved marks under an optical microscope;
FIG. 5 is a schematic diagram of a reticle exposure method of the present invention;
FIG. 6 is a schematic diagram illustrating the variation of the step aspect ratio of the wafer marking region with the process;
FIG. 7 is a clear cross-sectional view of a notch at the flat edge of a wafer according to the present invention;
FIG. 8 is a schematic view of a wafer flat edge under an optical microscope for clarity of marking in accordance with the present invention;
FIG. 9 is a 5 inch film-free full transmission lithographic master sample (suitable for all Nikon 5 inch lithography machines).
Detailed Description
The invention is further described with reference to the following figures and detailed description.
The invention provides a photoetching process method for a wafer number carving area, according to a light reflection law, if the number carving position has no step difference and is not a light-transmitting substance, according to the reflection law, reflected light at the number carving position is captured by eyes and processed to obtain information which is a step-free plane, and the number carving cannot be identified.
According to the law of reflection, the mark position must have step difference or the step is a light-transmitting medium, so that the reflection photoetching at the mark position can enter eyes, and the reflection photoetching is focused on retina after being refracted by an eyeball optical system, and the step difference is formed after being integrated by the brain due to the optical path difference, so that the mark can be identified;
the invention uses a full-transparent photoetching plate to expose the flat edge marking position of the flat edge of the wafer, which relates to the deposition of titanium, titanium nitride, tungsten, aluminum silicon copper and other opaque media layers (comprising contact hole photoetching, through hole 1 photoetching and through hole 2 photoetching), the photoresist at the flat edge is developed and removed after exposure, the subsequent etching process removes the media at the marking position, and the step height difference at the marking position is always kept, so that the marking can still be manually identified after the deposition of titanium nitride, aluminum silicon copper and other opaque media.
Referring to fig. 1-7, the photolithography process for etching the wafer mark area of the present invention specifically includes the following steps: step one, respectively carrying out hot plate treatment (the process temperature is 100 ℃, the process time is 60 seconds, and the distance from the hot plate is about 0.3 mm) on the surface of a wafer (including contact hole photoetching, through hole 1 photoetching and through hole 2) related to depositing titanium, titanium nitride, tungsten, aluminum silicon copper and other opaque medium layers, so that water molecules on the surface of the wafer are evaporated, and the surface of the wafer is in a dry state.
And step two, carrying out HMDS (atomizing hexamethyldisilazane in a vacuum cavity for 60 seconds at the process temperature of 100 ℃) on the wafer with the surface in the dry state, and then carrying out cold plate treatment (the process time is 60 seconds at the process temperature of 23 ℃).
And step three, gluing the wafer in a gluing cavity, spraying glue at the center of the wafer, uniformly coating photoresist on the wafer through a rotating centrifugal force, and performing EBR trimming (the width is 1-3 mm), wherein only the edge position of the round edge of the wafer can be removed by trimming, the flat edge cannot be removed, and the notch is positioned at the flat edge of the wafer.
Step four, using a full-transmission photoetching plate at the flat edge of the wafer which is not exposed after the glue coating is finished, carrying out full-transmission photoetching plate alignment and wafer alignment, then carrying out exposure on the flat edge marking area of the wafer from left to right according to the photoetching field, and carrying out exposure energy during exposure: 450-; focal length: 0 micron.
Preferably, the plate making requirements of the full-light-transmission photoetching plate are as follows:
| grade of Grade | Material of | Protective film 2(5 inch photoetching plate) | Protective film 1(6 inch photoetching plate) |
| Glass | Common glass plate | Double-sided protective film (optional option) | Single-side protective film (optional) |
Remarking: and (4) executing the size of the photoetching plate and the alignment Mark design rule according to the plate making requirement of the corresponding photoetching machine.
As shown in fig. 9, the front and the back of the full-transparent reticle of the present invention are made of common glass, and it is noted that: the reverse side of the full-transmission photoetching plate does not need to be sputtered with a chromium dioxide light-tight coating.
And fifthly, developing the exposed wafer by using a developing machine, firstly carrying out PEB treatment (the process time is 60 seconds and the process temperature is 100 ℃), then carrying out cold plate treatment (the process time is 60 seconds and the process temperature is 23 ℃), next entering a developing chamber for developing, spraying a developing solution on the wafer, soaking for 58s, carrying out spin-drying and flushing for completing developing, and removing the photoresist in the marking area after developing.
And sixthly, etching and removing the photoresist on the wafer by using an etching machine, and etching and removing the silicon dioxide medium in the marking area.
And after the sixth step, the silicon dioxide medium in the mark carving area is etched, a step is formed, and the mark carving can still be identified after the deposition of opaque mediums such as titanium nitride, aluminum silicon copper and the like.
As shown in fig. 5, for the 0.5 micron and following dual poly-tri-aluminum CMOS process products, respectively: each wafer coated with photoresist is exposed in a marking area at the flat edge of the wafer when the contact hole lithography (serial number 3) is carried out after ILD medium CMP, the through hole 1 lithography (serial number 8) is carried out after IMD1 medium CMP and the through hole 2 lithography (serial number 13) is carried out after IMD2 medium CMP, the photoresist in the marking area is removed by developer after exposure, and the specific flow is shown in table 1 and figure 6.
TABLE 10.5 micrometer double polycrystal three-aluminum back-end flow chart
FIG. 6 is a schematic view showing the change of the depth-to-width ratio of the step at the mark according to the present invention, as shown in the figure, the change of the depth-to-width ratio of the step at the mark is as follows:
(1) after the 1 st dielectric (ILD) is performed, silicon dioxide with the same thickness is added at the height and the height steps of the notch, and the depth-to-width ratio of the notch is changed from the initial 3: the 40 becomes shallow to be 3: 37.2;
(2) after the 1 st CMP, the silicon dioxide at the high step is ground off in the CMP process
The depth-to-width ratio of the notch is from the first 3: 37.2 lightening to 2: 37.2.
(3) and etching the contact hole, exposing, developing and etching the mark etching position by using contact hole photoetching, etching and removing silicon dioxide at the mark etching position, recovering the step at the mark etching position again, wherein the depth-to-width ratio of the mark etching position is from the initial 2: 37.2 deepening to 3: 40;
(4) deposition of
After the metal 1 medium is processed, the depth-to-width ratio of the notch is from 3: 40 deepening is 3: 38;
(5) after the 2 nd dielectric (IMD1), silicon dioxide with the same thickness is added at the positions of the high and low steps of the mark, and the thickness of the silicon dioxide is
The depth-to-width ratio of the notch is 3: 38 deepening to 3: 34.9 of the total weight of the powder;
(6) the 2 nd growth silicon dioxide medium at the high step after the 2 nd CMP is ground off in the 2 nd CMP process
The depth-to-width ratio of the notch is 3: 34.9 deepening to 2: 34.9 of the total weight of the powder;
(7) after photoetching the through hole 1, exposing, developing and etching the mark, etching and removing silicon dioxide at the mark, recovering the step height of the mark to 3 mu m, and enabling the depth-to-width ratio of the mark to be 2: 34.9 deepening to 3: 38;
(8) depositing metal 2 medium, growing totally
The metal 2 dielectric of (2), the depth-to-width ratio of the notch is from 3: 38 deepening to 3: 35;
(9) after 3 rd dielectric (IMD2), silicon dioxide with the same thickness is added at the positions of the high and low steps of the mark, and the thickness of the silicon dioxide is
The depth-to-width ratio of the notch is 3: 35 deepening to 3: 31.9 of the total weight of the mixture;
(10) after the 3 rd CMP, the 3 rd growth silicon dioxide medium at the high step is ground in the 3 rd CMP processTo get rid of
(11) Photoetching the through hole 2, exposing, developing and etching the mark position, etching and removing silicon dioxide at the mark position, and recovering the step height of the mark position to 3 mu m;
(12) growing a total of one or more wafers on the wafer processed in step (11)
The metal 2 medium of (2), the carved number can still be normally identified.
The invention is applied to a 6-inch 0.5-micron DPTM CMOS product, and relates to an exposure step of depositing titanium, titanium nitride, tungsten, aluminum, silicon, copper and other lighttight medium layers (including contact hole photoetching, through hole 1 photoetching and through hole 2 photoetching) photoetching in a process flow.
The invention is applied to the back-end process of 6-inch 0.18 micron/0.13 micron products, and relates to the exposure steps of depositing titanium, titanium nitride, tungsten, aluminum silicon copper and other opaque medium layers (including contact hole photoetching, through hole 1 photoetching, through hole 2 photoetching, through hole 3 photoetching, through hole 4 photoetching and through hole 5) photoetching in the process flow.
The invention can also be applied to the top metal photoetching level of a product with higher reliability requirement, the edge full exposure is increased through the exposure step of the top metal photoetching of the process flow, and then the development and the etching are carried out, so that the tube core in the 5mm area of the edge has no metal connecting wire and is directly removed in the device function test link due to the poor reliability of the tube core in the 5mm area of the edge, and the tube core with normal function test but poor reliability is prevented from being applied and used. The tape-out exceeds 2000 pieces, so that the problem that the die in the edge area is applied due to poor reliability is avoided, and the reliability of the whole piece is improved.
The invention provides a photoetching process method of a wafer marking area, which comprises the steps of pretreating a wafer after light-tight media are deposited each time, coating photoresist on the pretreated wafer, and exposing the wafer marking area after the photoresist is coated; developing the wafer in the step S1, and removing the photoresist in the wafer marking area; and etching the wafer in the step S2 to obtain the wafer with clear carved number. The method carries out special exposure treatment on the surface of the wafer at the position of the mark, so that the position of the mark always keeps a certain depth-to-width ratio in the subsequent process, the effect of resolving the unclear mark by utilizing the light reflection law is far superior to that of the existing method, the feasibility of manually identifying the wafer mark is enhanced, the abnormal rate is reduced to the greatest extent, and the production efficiency is improved.
Claims (8)
1. A photoetching process method for a wafer number-carving area is characterized by comprising the following specific steps:
s1, preprocessing the wafer after the light-tight medium is deposited each time, coating photoresist on the preprocessed wafer, and exposing the wafer marking area after the photoresist is coated;
s2, developing the wafer in the step S1, and removing the photoresist in the wafer marking area;
s3, etching the wafer in the step S2 to obtain the wafer with clear carved number.
2. The method of claim 1, wherein the exposing step S1 is performed using a full-transmission reticle.
3. The method according to claim 1, wherein in step S1, the front and back surfaces of the opaque reticle are made of common glass, and the back surface of the opaque reticle is not sputtered with a opaque coating of chromium dioxide.
4. The method as claimed in claim 1, wherein in step S1, only the wafer mark area is exposed from left to right according to the lithography view field.
5. The method as claimed in claim 1, wherein in step S1, the opaque medium comprises ti, tin, w, or al-si-cu.
6. The method as claimed in claim 1, wherein the pretreatment comprises hot plate treatment, HMDS and cold plate treatment of the wafer in sequence in step S1.
7. The method as claimed in claim 1, wherein in step S2, the wafer after exposure is subjected to PEB processing and cold plate processing before development, and development is performed after cold plate processing.
8. The method as claimed in claim 1, wherein in step S2, the developing step is performed by spraying a developing solution on the wafer for a soaking time of 58S, and the developing step is performed by spin-drying and flushing.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117832066A (en) * | 2024-03-06 | 2024-04-05 | 赛莱克斯微系统科技（北京）有限公司 | Patterning method |
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| US20050158966A1 (en) * | 2004-01-20 | 2005-07-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to avoid a laser marked area step height |
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