CN113965309A - Optimal frame header locking method in frame synchronizer - Google Patents
Optimal frame header locking method in frame synchronizer Download PDFInfo
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- CN113965309A CN113965309A CN202111185385.XA CN202111185385A CN113965309A CN 113965309 A CN113965309 A CN 113965309A CN 202111185385 A CN202111185385 A CN 202111185385A CN 113965309 A CN113965309 A CN 113965309A
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- 238000012795 verification Methods 0.000 claims abstract description 23
- 238000000605 extraction Methods 0.000 claims description 4
- 238000009432 framing Methods 0.000 claims description 2
- 238000004891 communication Methods 0.000 description 6
- 230000004048 modification Effects 0.000 description 3
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- 238000006243 chemical reaction Methods 0.000 description 2
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- 230000001360 synchronised effect Effects 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
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Abstract
The application provides an optimal frame header locking method in a frame synchronizer, which comprises a searching state, a checking state and a locking state. When the frame synchronizer is in a searching state, the frame synchronizer searches the input code element signals bit by bit until a suspected frame header is found; continuously checking the suspected frame header under the checking state until a real frame header is found; and when in the locking state, continuously performing locking verification on the position of the real frame header. The strategy can effectively reduce the probability of frame head error locking of the frame synchronizer.
Description
Technical Field
The present invention relates to the field of wireless communication, and in particular, to a method for locking an optimal frame header in a frame synchronizer.
Background
The wireless communication system generally includes modules at a receiving end, such as digital down-conversion, digital filtering, carrier acquisition and tracking, demodulation and decoding, wherein the demodulation and decoding module generally includes a code synchronizer, a frame synchronizer, and a decoder.
The frame synchronizer has the main functions of receiving the PCM serial signal and the synchronous clock from the code synchronizer, carrying out frame extraction on the input signal according to a determined frame format and a locking strategy, and generating a frame synchronization pulse and a frame locking state indication. An important link in the frame extraction process is to find the real frame header of the PCM serial signal, however, in actual communication, the occurrence of channel noise and suspected frame header will increase the probability of frame synchronizer false lock, and further affect the performance of the wireless communication receiving end.
The invention provides an optimal frame head locking mechanism in frame synchronization mainly aiming at the problem of frame synchronizer mislocking.
Disclosure of Invention
Aiming at the defects in the prior art, the embodiment of the application provides an optimal frame header locking method in a frame synchronizer. The technical scheme is as follows:
the application discloses an optimal frame header locking method in a frame synchronizer, which comprises a searching state, a checking state and a locking state;
s1, searching state, namely receiving an input signal, searching the input signal bit by bit, determining an initial frame header, marking the position of the initial frame header as an initial position, calculating the bit number which is inconsistent with a standard frame header and recording the bit number as an initial error;
s2, searching state, continuously receiving input signals, determining a checking frame head, marking the position of the checking frame head as a checking position, calculating the bit number which is inconsistent with the standard frame head, and recording the bit number as a checking error;
s3, checking state, calculating the difference value between the checking position and the initial position, and if the position difference is equal to the content M and the length N of the standard frame header, switching the frame synchronizer from the checking state to the locking state;
s4, checking state, extracting M bit code elements at positions (M + N) bit away from the checking frame head, comparing each verification frame head with a standard frame head, and if the verification frame head is a suspected frame head, locking verification is successful; if the verification frame header is not the suspected frame header, the locking verification fails, and the searching state is returned again;
s5, in the locking state, the authenticity of the suspected frame header is circularly checked by calculating the position difference and comparing the error magnitude until the real frame header is found, and then the frame synchronizer is switched into the locking state and gives a frame locking state indication.
In a possible implementation manner, if the position difference is greater than M + N, the frame synchronizer abandons the initial frame header, takes the check frame header as the initial position, and returns to the searching state again to continue to search for a second suspected frame header;
if the position difference is less than M + N, the frame synchronizer compares the initial error with the checking error, if the initial error is greater than the checking error, the frame synchronizer abandons the initial frame header, takes the checking frame header as the initial position, and returns to the searching state again to continuously search for a second suspected frame header;
if the initial error is less than or equal to the checking error, the frame synchronizer abandons the checking frame head, still takes the initial frame head as the initial position, and returns to the searching state again to continuously search for a second suspected frame head.
In one possible implementation, the frame synchronizer performs frame extraction on the input symbol signal according to a determined frame format and a locking strategy to generate a frame synchronization pulse and a frame locking state indication.
In one possible implementation, in the search state, the frame synchronizer searches bit by bit, and marks the respective positions and errors when two suspected frame headers are found.
In one possible implementation, during the check state, the frame synchronizer checks the authenticity of the suspected frame header by calculating the position difference and comparing the error magnitude.
In one possible implementation, in the locked state, the frame synchronizer performs lock verification at the frame header position according to the lock policy.
In one possible implementation, the frame format defines a framing manner of the frame synchronizer input symbol signal, and includes: any frame signal consists of a standard frame header and a data area, the content and the length of the standard frame header are fixed, the length of the data area is fixed, and a plurality of continuous frames form an input signal.
In one possible implementation, the locking policy includes: and comparing the frame head position with the standard frame head, and judging that the lock is lost if the error code number of the continuous 3-frame heads is more than 4.
In one possible implementation manner, the suspected frame header is: compared with the standard frame header, the length is the same, and the number of error codes is less than or equal to 3 code element sequences.
The beneficial effects brought by the technical scheme provided by the embodiment of the application at least comprise:
the method comprises a searching state, a checking state and a locking state, and carries out bit-by-bit screening and checking on the received signals respectively, so that the probability of frame header error locking of a receiving end in a wireless communication system can be reduced, and the performance of the wireless communication receiving end is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a diagram illustrating a frame synchronizer structure according to an exemplary embodiment of the present application;
FIG. 2 is a diagram of a frame format provided by an exemplary embodiment of the present application;
fig. 3 is a flowchart of an optimal frame header locking method according to an exemplary embodiment of the present application.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
The frame synchronizer operates in three states, as shown in fig. 1, which are a search state, a check state and a lock state.
The frame format is composed of a standard frame header followed by a data area, the content and length of the standard frame header are fixed and are M bits, the length of the data area are fixed and are N bits, and the frame format structure is shown in figure 2.
The suspected frame header refers to a code element sequence with the same length and the number of error codes less than or equal to S compared with the standard frame header, wherein the number of error codes can be freely set according to the actual situation, and exemplarily, the number of error codes S in this embodiment is 3.
Referring to fig. 3, fig. 3 is a flowchart of an optimal frame header locking method according to an exemplary embodiment of the present invention. The strategy relies on the tri-state conversion of the frame synchronizer to identify the optimal frame header. The following is specifically explained with reference to fig. three:
after the input signal enters the frame synchronizer, it is first in the search state. In the searching state, the frame synchronizer searches the input code element signals bit by bit according to the frame format until two suspected frame headers are found. Defining the first suspected frame head found first as an initial frame head, marking the position as an initial position, calculating the bit number which is inconsistent with the standard frame head and marking as an initial error; and marking the position of the second suspected frame head which is found after the definition as a checking frame head, and calculating the bit number which is inconsistent with the standard frame head and recording the bit number as a checking error. The frame synchronizer is switched from the search state to the check state.
In the checking state, the frame synchronizer calculates the difference value between the checking position and the initial position, and if the position difference is equal to M + N, the frame synchronizer is switched from the checking state to the locking state.
After entering the locked state, the frame synchronizer does not perform bit-by-bit comparison on the input code element signals any more, extracts the code element of M bit only at the position of every (M + N) bit away from the verification frame header, respectively defines the verification frame header 1 and the verification frame header 2 … … verification frame header N, and compares each verification frame header with the standard frame header. If the verification frame header is a suspected frame header, the locking verification is successful; if the verification frame header is not the suspected frame header, the locking verification fails. When the verification fails or the carrier is unlocked, the frame synchronizer returns to the searching state again.
If the position difference is larger than M + N, the frame synchronizer abandons the initial frame head, takes the checking frame head as the initial position, and returns to the searching state again to continuously search for a second suspected frame head. If the position difference is less than M + N, the frame synchronizer compares the initial error with the checking error, if the initial error is greater than the checking error, the frame synchronizer abandons the initial frame header, takes the checking frame header as the initial position, and returns to the searching state again to continuously search for a second suspected frame header; if the initial error is less than or equal to the checking error, the frame synchronizer abandons the checking frame head, still takes the initial frame head as the initial position, and returns to the searching state again to continuously search for a second suspected frame head.
And circularly checking the authenticity of the suspected frame header by calculating the position difference and comparing the error magnitude until the real frame header is found. The frame synchronizer then transitions to the lock state and gives an indication of the frame lock state.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.
It should be understood that reference to "a plurality" herein means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (9)
1. A method for locking an optimal frame header in a frame synchronizer is characterized in that the method comprises a searching state, a checking state and a locking state;
s1, searching state, namely receiving an input signal, searching the input signal bit by bit, determining an initial frame header, marking the position of the initial frame header as an initial position, calculating the bit number which is inconsistent with a standard frame header and recording the bit number as an initial error;
s2, searching state, continuously receiving input signals, determining a checking frame head, marking the position of the checking frame head as a checking position, calculating the bit number which is inconsistent with the standard frame head, and recording the bit number as a checking error;
s3, checking state, calculating the difference value between the checking position and the initial position, and if the position difference is equal to the content M and the length N of the standard frame header, switching the frame synchronizer from the checking state to the locking state;
s4, checking state, extracting M bit code elements at positions (M + N) bit away from the checking frame head, comparing each verification frame head with a standard frame head, and if the verification frame head is a suspected frame head, locking verification is successful; if the verification frame header is not the suspected frame header, the locking verification fails, and the searching state is returned again;
s5, in the locking state, the authenticity of the suspected frame header is circularly checked by calculating the position difference and comparing the error magnitude until the real frame header is found, and then the frame synchronizer is switched into the locking state and gives a frame locking state indication.
2. The method according to claim 1, wherein the step S4 includes:
if the position difference is larger than M + N, the frame synchronizer abandons the initial frame head, takes the checking frame head as the initial position, and returns to the searching state again to continuously search for a second suspected frame head;
if the position difference is less than M + N, the frame synchronizer compares the initial error with the checking error, if the initial error is greater than the checking error, the frame synchronizer abandons the initial frame header, takes the checking frame header as the initial position, and returns to the searching state again to continuously search for a second suspected frame header;
if the initial error is less than or equal to the checking error, the frame synchronizer abandons the checking frame head, still takes the initial frame head as the initial position, and returns to the searching state again to continuously search for a second suspected frame head.
3. The method of claim 1 wherein the frame synchronizer performs frame extraction on the input symbol signal in accordance with a predetermined frame format and lock strategy to generate a frame synchronization pulse and a frame lock status indication.
4. The method of claim 1, wherein in the search state, the frame synchronizer searches bit by bit, and marks the respective positions and errors when two suspected frame headers are found.
5. The method of claim 1, wherein the frame synchronizer checks the authenticity of the suspected frame header by calculating a position difference and comparing the error magnitudes during the check state.
6. The method of claim 1, wherein in the locked state, the frame synchronizer performs lock verification at the frame header position according to the lock policy.
7. The method of claim 3, wherein the frame format defines a framing pattern of the frame synchronizer input symbol signal, comprising: any frame signal consists of a standard frame header and a data area, the content and the length of the standard frame header are fixed, the length of the data area is fixed, and a plurality of continuous frames form an input signal.
8. The method of claim 6, wherein the locking policy comprises: and comparing the frame head position with the standard frame head, and judging that the lock is lost if the error code number of the continuous 3-frame heads is more than 4.
9. The method of claim 1, wherein the suspected frame header is: compared with the standard frame header, the length is the same, and the number of error codes is less than or equal to 3 code element sequences.
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