CN114339985A - Optimal frame header locking strategy in frame synchronization - Google Patents
Optimal frame header locking strategy in frame synchronization Download PDFInfo
- Publication number
- CN114339985A CN114339985A CN202210003988.1A CN202210003988A CN114339985A CN 114339985 A CN114339985 A CN 114339985A CN 202210003988 A CN202210003988 A CN 202210003988A CN 114339985 A CN114339985 A CN 114339985A
- Authority
- CN
- China
- Prior art keywords
- frame
- state
- checking
- synchronizer
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Images
Landscapes
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention provides an optimal frame header locking method in a frame synchronizer, which comprises the following steps: a search state, a check state and a lock state. When the frame synchronizer is in a searching state, the frame synchronizer searches input code element signals bit by bit until a suspected frame header is found; continuously checking the suspected frame header under the checking state until a real frame header is found; and when in the locking state, continuously performing locking verification on the position of the real frame header. The method can effectively reduce the probability of frame head false lock of the frame synchronizer.
Description
Technical Field
The invention relates to the field of wireless communication, in particular to the field of frame synchronization of a wireless communication receiving end.
Background
The wireless communication system generally includes modules at a receiving end, such as digital down-conversion, digital filtering, carrier acquisition and tracking, demodulation and decoding, wherein the demodulation and decoding module generally includes a code synchronizer, a frame synchronizer, and a decoder.
The frame synchronizer has the main functions of receiving the PCM serial signal and the synchronous clock from the code synchronizer, carrying out frame extraction on the input signal according to a determined frame format and a locking strategy, and generating a frame synchronization pulse and a frame locking state indication. An important link in the frame extraction process is to find the real frame header of the PCM serial signal, however, in actual communication, the occurrence of channel noise and suspected frame header will increase the probability of frame synchronizer false lock, and further affect the performance of the wireless communication receiving end.
Disclosure of Invention
The invention aims to provide an optimal frame header locking method in a frame synchronizer, which can reduce the probability of frame header error locking of a receiving end in a wireless communication system.
The purpose of the invention is realized by the following technical scheme: the frame synchronizer always works in a search state, a check state and a locking state.
In the searching state, the frame synchronizer searches the frame headers bit by bit, and marks the respective positions and errors after finding two suspected frame headers meeting the standard, so that the frame synchronizer is switched into the checking state.
Under the checking state, the frame synchronizer circularly checks the authenticity of the suspected frame header by calculating the position difference and comparing the error magnitude until finding the real frame header. The frame synchronizer then transitions to the lock state and gives an indication of the frame lock state.
After entering the locking state, the method does not search bit by bit, and only carries out locking verification on the position of the frame header. And when the verification fails or the carrier is unlocked, the searching state is returned again.
Further, in the method for locking an optimal frame header in a frame synchronizer, in the search state, the frame synchronizer searches for the frame headers bit by bit, and after finding two suspected frame headers meeting the standard, marks the respective positions and errors, and the frame synchronizer is then switched to the check state, including:
after the input signal enters the frame synchronizer, the input signal is firstly in a searching state, and in the searching state, the frame synchronizer searches the input code element signal bit by bit according to a frame format until two suspected frame headers are found. Defining the first suspected frame head found first as an initial frame head, marking the position as an initial position, calculating the bit number which is inconsistent with the standard frame head and marking as an initial error; and marking the position of the second suspected frame head which is found after the definition as a checking frame head, and calculating the bit number which is inconsistent with the standard frame head and recording the bit number as a checking error. The frame synchronizer is switched from the search state to the check state.
Further, in the method for locking an optimal frame header in a frame synchronizer, in a check state, the frame synchronizer checks the authenticity of a suspected frame header in a circulating manner by calculating a position difference and comparing error magnitudes until a real frame header is found, and then the frame synchronizer shifts to a locking state and gives a frame locking state indication, including:
in the checking state, the frame synchronizer calculates the difference value between the checking position and the initial position, and if the position difference is equal to M + N, the frame synchronizer is switched from the checking state to the locking state.
Further, in the method for locking an optimal frame header in a frame synchronizer, after entering a locking state, the method does not search bit by bit, performs locking verification only at the position of the frame header, and returns to the searching state again when the verification fails or the carrier loses lock, and includes:
after entering the locked state, the frame synchronizer does not perform bit-by-bit comparison on the input code element signals any more, extracts the code elements of M bit only at the positions (M + N) bit away from the checking frame head, respectively defines the positions as a checking frame head 1, a checking frame head 2, … … and a checking frame head N, compares each checking frame head with a standard frame head, and if the checking frame head is a suspected frame head, the locking verification is successful; if the verification frame header is not the suspected frame header, the locking verification fails; when the verification fails or the carrier is unlocked, the frame synchronizer returns to the searching state again;
if the position difference is larger than M + N, the frame synchronizer abandons the initial frame head, takes the checking frame head as the initial position, and returns to the searching state again to continuously search for a second suspected frame head. If the position difference is less than M + N, the frame synchronizer compares the initial error with the checking error, if the initial error is greater than the checking error, the frame synchronizer abandons the initial frame header, takes the checking frame header as the initial position, and returns to the searching state again to continuously search for a second suspected frame header; if the initial error is less than or equal to the checking error, the frame synchronizer abandons the checking frame head, still takes the initial frame head as the initial position, and returns to the searching state again to continuously search for a second suspected frame head.
Further, in the method for locking an optimal frame header in the frame synchronizer, the frame synchronizer performs frame extraction on the input code element signal according to a determined frame format and a locking strategy to generate a frame synchronization pulse and a frame locking state indication.
Further, in the method for locking an optimal frame header in a frame synchronizer, the frame format defines a framing mode of an input symbol signal of the frame synchronizer, and includes: any frame signal consists of a standard frame head and a data area, the content and the length of the standard frame head are fixed, the length of the data area is fixed, and a plurality of continuous frames form an input signal.
Further, in the method for locking an optimal frame header in the frame synchronizer, after the frame header enters the locking state, the frame header position is compared with the standard frame header, and if the number of error codes of the continuous 3-frame headers is greater than 4, the carrier is judged to be unlocked.
Further, in the method for locking an optimal frame header in the frame synchronizer, the suspected frame header is a symbol sequence with the same length and the number of error codes less than or equal to 3 compared with the standard frame header.
Drawings
FIG. 1 is a diagram of a frame synchronizer structure;
FIG. 2 is a diagram of a frame format;
fig. 3 is a flowchart of an optimal frame header locking strategy.
Detailed Description
The following describes an embodiment of the present invention with reference to the accompanying drawings by taking an example of an application of an optimal frame header locking policy in a frame synchronizer.
The frame synchronizer works in three states, namely a search state, a check state and a locking state. The overall structure of the frame synchronizer is shown in fig. 1.
The frame format is composed of a standard frame header followed by a data area, the content and length (assumed to be M bit) of the standard frame header are fixed, the length (assumed to be N bit) of the data area is fixed, and the frame format structure is shown in FIG. 2.
The suspected frame header refers to a code element sequence which has the same length and the number of error codes less than or equal to 3 compared with the standard frame header.
Fig. 3 is a schematic flow chart of an optimal frame header locking strategy designed by the present invention. The strategy relies on the tri-state conversion of the frame synchronizer to identify the optimal frame header. The following is specifically explained with reference to fig. three:
after the input signal enters the frame synchronizer, it is first in the search state. In the searching state, the frame synchronizer searches the input code element signals bit by bit according to the frame format until two suspected frame headers are found. Defining the first suspected frame head found first as an initial frame head, marking the position as an initial position, calculating the bit number which is inconsistent with the standard frame head and marking as an initial error; and marking the position of the second suspected frame head which is found after the definition as a checking frame head, and calculating the bit number which is inconsistent with the standard frame head and recording the bit number as a checking error. The frame synchronizer is switched from the search state to the check state.
In the checking state, the frame synchronizer calculates the difference value between the checking position and the initial position, and if the position difference is equal to M + N, the frame synchronizer is switched from the checking state to the locking state.
After entering the locked state, the frame synchronizer does not perform bit-by-bit comparison on the input code element signals any longer, extracts the code elements of M bit only at the positions (M + N) bit away from the checking frame head, respectively defines the checking frame head 1, the checking frame head 2, … … and the checking frame head N, and compares each checking frame head with the standard frame head. If the verification frame header is a suspected frame header, the locking verification is successful; if the verification frame header is not the suspected frame header, the locking verification fails; when the verification fails or the carrier is unlocked, the frame synchronizer returns to the searching state again.
If the position difference is larger than M + N, the frame synchronizer abandons the initial frame head, takes the checking frame head as the initial position, and returns to the searching state again to continuously search for a second suspected frame head. If the position difference is less than M + N, the frame synchronizer compares the initial error with the checking error, if the initial error is greater than the checking error, the frame synchronizer abandons the initial frame header, takes the checking frame header as the initial position, and returns to the searching state again to continuously search for a second suspected frame header; if the initial error is less than or equal to the checking error, the frame synchronizer abandons the checking frame head, still takes the initial frame head as the initial position, and returns to the searching state again to continuously search for a second suspected frame head.
And circularly checking the authenticity of the suspected frame header by calculating the position difference and comparing the error magnitude until the real frame header is found. The frame synchronizer then transitions to the lock state and gives an indication of the frame lock state.
The method designed by the invention can be easily applied to other communication systems needing frame synchronization, and can effectively reduce the probability of frame head error locking of the frame synchronizer.
Claims (8)
1. An optimal frame header locking method in a frame synchronizer includes: the frame synchronizer is always operated in three states, namely a search state, a check state and a locking state, wherein,
in the searching state, the frame synchronizer searches the frame headers bit by bit, marks respective positions and errors after two suspected frame headers meeting the standard are found, and then the frame synchronizer is switched into a checking state;
in the checking state, the frame synchronizer circularly checks the authenticity of the suspected frame header by calculating the position difference and comparing the error magnitude until the real frame header is found, and then the frame synchronizer is switched into the locking state and gives a frame locking state indication;
after entering the locking state, the method does not search bit by bit, only carries out locking verification on the position of the frame head, and returns to the searching state again after the verification fails or the carrier loses the lock.
2. The method as claimed in claim 1, wherein in the search state, the frame synchronizer searches the frame headers bit by bit, marks the respective positions and errors after finding two suspected frame headers meeting the standard, and then goes into the check state, comprising:
after the input signal enters the frame synchronizer, the input signal is firstly in a searching state, and in the searching state, the frame synchronizer searches the input code element signal bit by bit according to a frame format until two suspected frame headers are found. Defining the first suspected frame head found first as an initial frame head, marking the position as an initial position, calculating the bit number which is inconsistent with the standard frame head and marking as an initial error; and marking the position of the second suspected frame head which is found after the definition as a checking frame head, and calculating the bit number which is inconsistent with the standard frame head and recording the bit number as a checking error. The frame synchronizer is switched from the search state to the check state.
3. The method as claimed in claim 2, wherein in the checking state, the frame synchronizer calculates the position difference and compares the error magnitude to check the authenticity of the suspected frame header cyclically until the authentic frame header is found, and then the frame synchronizer shifts to the locking state and gives an indication of the locking state of the frame, comprising:
in the checking state, the frame synchronizer calculates the difference value between the checking position and the initial position, and if the position difference is equal to M + N, the frame synchronizer is switched from the checking state to the locking state.
4. The method as claimed in claim 3, wherein after entering the locked state, the method does not search bit by bit, performs the lock verification only at the frame header position, and returns to the searching state when the verification fails or the carrier is out of lock, comprising:
after entering the locked state, the frame synchronizer does not perform bit-by-bit comparison on the input code element signals any more, extracts the code elements of M bit only at the positions (M + N) bit away from the checking frame head, respectively defines the positions as a checking frame head 1, a checking frame head 2, … … and a checking frame head N, compares each checking frame head with a standard frame head, and if the checking frame head is a suspected frame head, the locking verification is successful; if the verification frame header is not the suspected frame header, the locking verification fails; when the verification fails or the carrier is unlocked, the frame synchronizer returns to the searching state again;
if the position difference is larger than M + N, the frame synchronizer abandons the initial frame head, takes the checking frame head as the initial position, and returns to the searching state again to continuously search for a second suspected frame head. If the position difference is less than M + N, the frame synchronizer compares the initial error with the checking error, if the initial error is greater than the checking error, the frame synchronizer abandons the initial frame header, takes the checking frame header as the initial position, and returns to the searching state again to continuously search for a second suspected frame header; if the initial error is less than or equal to the checking error, the frame synchronizer abandons the checking frame head, still takes the initial frame head as the initial position, and returns to the searching state again to continuously search for a second suspected frame head.
5. The method as claimed in claim 1, wherein the frame synchronizer performs frame extraction on the input symbol signal according to a predetermined frame format and locking strategy to generate frame synchronization pulse and frame locking status indication.
6. The method of claim 5, wherein the frame format defines a framing manner of the frame synchronizer input symbol signal, comprising: any frame signal consists of a standard frame head and a data area, the content and the length of the standard frame head are fixed, the length of the data area is fixed, and a plurality of continuous frames form an input signal.
7. The method as claimed in claim 4, wherein after entering the locked state, the frame header position is compared with the standard frame header only, and if the number of error codes of the consecutive 3 frame headers is greater than 4, the carrier is determined to be unlocked.
8. The method as claimed in claim 4, wherein the suspected frame header is a symbol sequence with the same length and less than or equal to 3 bit errors compared with the standard frame header.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210003988.1A CN114339985A (en) | 2022-01-04 | 2022-01-04 | Optimal frame header locking strategy in frame synchronization |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210003988.1A CN114339985A (en) | 2022-01-04 | 2022-01-04 | Optimal frame header locking strategy in frame synchronization |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114339985A true CN114339985A (en) | 2022-04-12 |
Family
ID=81023832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210003988.1A Withdrawn CN114339985A (en) | 2022-01-04 | 2022-01-04 | Optimal frame header locking strategy in frame synchronization |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114339985A (en) |
-
2022
- 2022-01-04 CN CN202210003988.1A patent/CN114339985A/en not_active Withdrawn
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5204859A (en) | Method and apparatus for detecting a frame alignment word in a data system | |
| US20100251079A1 (en) | Method and device for information block coding and synchronization detecting | |
| CN1881868B (en) | Communication method and apparatus | |
| US6993100B2 (en) | Burst detector | |
| CN105763205A (en) | Spiral interleaver parameter blind estimation method based on Gauss column elimination | |
| CN107317644A (en) | A kind of compatible burst and the frame-synchronizing device of continuous data | |
| US20060062329A1 (en) | Apparatus and method for adaptive digital locking and soft evaluation of data symbols in a wireless digital communication system | |
| US6891906B1 (en) | Demodulator, clock recovery circuit, demodulation method and clock recovery method | |
| CN102378354A (en) | Synchronization method for short-term burst communication | |
| CN111726125B (en) | Error-containing concatenated code identification method based on template matching | |
| CN114339985A (en) | Optimal frame header locking strategy in frame synchronization | |
| CN116488978B (en) | Frame synchronization method suitable for BR Bluetooth in test environment | |
| CN108833321A (en) | Code CPM signal code block synchronization method based on differential phase waveform matching | |
| CN102111239B (en) | Cascading Hadamard code-aided carrier synchronization method under extremely low signal to noise ratio (SNR) | |
| CN113965309B (en) | Optimal frame head locking method in frame synchronizer | |
| US20020090033A1 (en) | Method and apparatus for enabling transmission of variable length encoded data in a low signal to noise ratio environment | |
| US20020150118A1 (en) | Communication system, method and signal for time-slot-coded data transmission | |
| EP2515456B1 (en) | Receiving apparatus and method for multi-frame synchronization | |
| JP3419367B2 (en) | Unique word detection circuit and unique word detection method | |
| CN116506076B (en) | Signal detection method for short preamble | |
| CN111181598B (en) | Method for timing synchronization of burst spread spectrum signal with extremely low signal-to-noise ratio | |
| JP5466432B2 (en) | Frame synchronizer | |
| WO2005114894A1 (en) | Signal receiver and mobile communication device | |
| Jiarui et al. | Low SNR isometric Secondary correlation frame synchronization algorithm | |
| CN115632921A (en) | Encoding auxiliary blind frame synchronization method and system based on threshold detection |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20220412 |
|
| WW01 | Invention patent application withdrawn after publication |