CN113965078A - 基于异质集成的高功率密度同步升压dc-dc转换芯片 - Google Patents
基于异质集成的高功率密度同步升压dc-dc转换芯片 Download PDFInfo
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Abstract
本发明公开一种基于异质集成的高功率密度同步升压DC‑DC转换芯片,包括片上集成部分及片外部分,片上集成部分包括高边增强型GaN功率开关管、低边增强型GaN功率开关管以及基于CMOS工艺的CMOS控制电路,CMOS控制电路包括带隙基准、误差放大器、箝位电路、比较器、锯齿波发生器、电平位移电路、驱动电路模块,片外部分包括电感L和电容C。本发明的本发明基于异质集成的高功率密度同步升压DC‑DC转换器芯片,可以有效提高芯片级DC‑DC转换器的输出功率;大大减小了高功率DC‑DC转换器的体积,有效降低其成本;具备宽输入电压范围,能在高开关频率下实现高的转换效率。
Description
技术领域
本发明涉及电源装置技术领域,特别是涉及一种基于异质集成的高功率密度同步升压DC-DC转换芯片。
背景技术
DC-DC转换器因其具有高转换效率广泛应用于物联网、光伏、便携式移动电子设备中。DC-DC转换器有同步整流和非同步整流两种方式。非同步整流使用二极管作为整流器件,这种方法成本较低同时电路设计简单,但是由于整流二极管上存在压降以及内阻,在大电流情况下会带来较大的效率损耗。而同步整流DC-DC转换器使用功率开关管代替整流二极管能极大的降低其带来的损耗,但会提高电路设计的难度。
由于无源器件(电感、电容等)的大小与频率成反比,为减小DC-DC转换器的体积及成本,提高DC-DC转换器的集成度、开关频率以及功率密度逐渐成为人们关注的焦点。然而由于CMOS工艺受到有限电源电压、本征导通电阻以及寄生二极管等的限制,基于CMOS工艺的高功率、高开关频率的DC-DC转换芯片难以实现。其中电源电压限制了DC-DC转换器的输出功率,寄生二极管、导通电阻使得频率越高,器件和电路的开关与导通损耗越大,DC-DC转换器在高开关频率下难以得到高转换效率。目前市面上高功率、高开关频率的DC-DC转换器主要在印刷电路板上实现。其中部分DC-DC转换器的开关功率管使用GaN/SiC替代传统MOS开关管。这是因为GaN/SiC等第三代半导体相对于MOS管,具有更大的禁带宽度、高的临界击穿电场强度、高电子迁移率以及没有寄生二极管等特点,使其更适用与高压、高温、高频、大功率应用场合下。然而基于GaN/SiC的DC-DC转换器难以集成,往往具有较高的成本与体积。
因此,如何得到具有高功率密度的同步DC-DC转换芯片成为了下一代功率电子技术面临的关键问题。
发明内容
本发明的目的是针对现有技术中存在的技术缺陷,而提供一种基于异质集成的高功率密度同步升压DC-DC转换芯片,该芯片可实现宽输入电压范围内高效率工作,具有大的功率密度。
为实现本发明的目的所采用的技术方案是:
一种基于异质集成的高功率密度同步升压DC-DC转换芯片,包括片上集成部分及片外部分,片上集成部分包括高边增强型GaN功率开关管、低边增强型GaN功率开关管以及基于CMOS工艺的CMOS控制电路,CMOS控制电路包括带隙基准、误差放大器、箝位电路、比较器、锯齿波发生器、电平位移电路、驱动电路模块,片外部分包括电感L和电容C;
锯齿波发生器的锯齿波信号输出端与比较器的负相输入端连接,带隙基准的输出端与误差放大器正相输入端连接,误差放大器的输出端与箝位电路的一端连接,箝位电路的另一端与比较器的正相输入端连接,误差放大器的负相输入端接入反馈电压VFB信号,比较器的输出端接电平位移电路的输入端,电平位移电路输出端连接两个Buf缓冲器的输入端,两个Buf缓冲器的输出端对应的与高边增强型GaN功率开关管以及低边增强型GaN功率开关管的栅极连接,电感L的一端与低边低增强型GaN功率开关管的漏极以及高边增强型GaN功率开关管的漏极相接,电感L的一端与电源的正极相接,高边增强型GaN功率开关管的源极接电容C的一端、负载的一端以及电阻RFB1的一端,低边低增强型GaN功率开关管的源极、电容C的另一端以及负载的另一端接电源的负极,即接地;电阻RFB的另一端与电阻RFB2的一端相接,电阻RFB2的另一端接地,反馈电压VFB信号由电阻RFB1的另一端与电阻RFB2的一端相接点引出。
其中,CMOS控制电路与GaN异质集成方法如下:
设计CMOS控制电路流片得到CMOS晶圆,在设计好的用于flip-chip的键合pad上制作一层凸点下金属化层,将高边增强型GaN功率开关管及低边增强型GaN功率开关管上的金属焊球焊接在凸点下金属化层上,使高边增强型GaN功率开关管及低边增强型GaN功率开关管直接倒装在CMOS晶圆上。
该基于异质集成的高功率密度同步升压DC-DC转换芯片的制作步骤如下:
第一步:指标设计
选择电压模式反馈脉冲宽度调制方式:根据所需的开关频率以及电流电感纹波值计算得到所需电感电容值,对整个DC-DC转换器进行线性化分析,得到其传递函数,根据得到传递函数设计补偿网络,并在simulink中进行仿真,确定补偿网络中RC值;
第二步:原理图仿真
功率管控制电路以及驱动电路采用CMOS工艺设计,包括带隙基准、误差放大器、比较器、锯齿波发生器模块,高边功率管与低边功率管均使用增强型GaN HEMT器件,通过导入器件模型和CMOS工艺库联合仿真确定整体电路的原理图;
第三步:版图设计
采用两种形状pad,除了用于wire-bonding传统矩形pad,还需根据所选的GaN器件设计用于filp-chip的pad,版图绘制后提取RC参数进行后仿真,根据前仿性能对版图进行优化。
本发明的本发明基于异质集成的高功率密度同步升压DC-DC转换器芯片,可以有效提高芯片级DC-DC转换器的输出功率;大大减小了高功率DC-DC转换器的体积,有效降低其成本;具备宽输入电压范围,能在高开关频率下实现高的转换效率。
附图说明
图1是现有技术下的非同步升压DC-DC转换器原理图示意图。
图2是现有技术下的同步升压DC-DC转换器原理图示意图。
图3是本发明实施例的异质集成同步升压DC-DC转换芯片原理图示意图。
图4是本发明实施例的异质集成同步升压DC-DC转换芯片横截面示意图。
具体实施方式
以下结合附图和具体实施例对本发明作进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。
图1为传统非同步DC-DC升压转换器原理图,该电路中无源元件电感L在开关管导通器件存储能量,关断时释放能量,电容C用于存储电荷,二极管控制单向导通整流,从而实现了能量转换。
图2为现有技术下的同步DC-DC升压转换器,其与图1的区别为,使用一个高边开关管来代替二极管,其开关状态与底边开关管相反从而实现单向导通整流功能。
本发明实施例的具体异质集成同步升压DC-DC转换芯片原理图如图3所示,I区域为片上集成部分,包括高边/低边增强型GaN功率开关管以及基于CMOS工艺的CMOS控制电路(CMOS PWM Controller),其中CMOS控制电路包括带隙基准(Band Gap)、误差放大器(EA)、箝位电路(Clamp)、比较器(Comp,Puls Width Generator)、锯齿波发生器(RampGenerator)、电平位移电路(Level Shift)、驱动电路模块,电感L和电容C为片外部分,其值由开关频率f与最小电流/电压纹波决定。
锯齿波发生器(Ramp generator)的锯齿波信号Ramp Singal输出端与比较器的负相输入端连接,带隙基准(Band Gap)的输出端与误差放大器(EA)正相输入端连接,误差放大器(EA)的输出端与箝位电路(Clamp)的一端连接,箝位电路(Clamp)的另一端与比较器的正相输入端连接,误差放大器(EA)的负相输入端接入反馈电压VFB信号,比较器(Comp)的输出端接电平位移电路(Level Shift)的输入端,电平位移电路(Level Shift)输出端连接两个Buf缓冲器的输入端,两个Buf缓冲器的输出端对应的与高边低边增强型GaN功率开关管、低边增强型GaN功率开关管的栅极连接,电感L的一端与低边低增强型GaN功率开关管的漏极以及高边增强型GaN功率开关管的漏极相接,电感L的一端与电源的正极相接,高边增强型GaN功率开关管的源极接电容C的一端、负载的一端以及电阻RFB1的一端,低边低增强型GaN功率开关管的源极、电容C的另一端以及负载的另一端接电源的负极,即接地;电阻RFB1的另一端与电阻RFB2的一端相接,电阻RFB2的另一端接地,反馈电压VFB信号由电阻RFB1的另一端与电阻RFB2的一端相接点引出。
其中,高边开关管与底边开关管可集成在同一块GaN器件上,相对于使用两个GaN器件,大大节约了DC-DC转换器的面积。
图4是本发明实施例的异质集成同步升压DC-DC转换器横截面示意图,其中,在CMOS晶圆1其上集成了PWM控制电路,其上的顶层金属2,未覆盖钝化层3,用做键合pad;顶层金属2的上方是GaN器件4;GaN器件4上有金属焊球5;与未覆盖钝化层3上的凸点下金属化层6焊接。
CMOS控制电路与GaN异质集成方法如下:
首先设计CMOS控制电路流片得到了CMOS晶圆,由于大部分工艺顶层金属为铝,不利于倒装,因此为了便于倒装GaN器件4,需要在设计好的八边形用于flip-chip的用做键合pad上制作一层凸点下金属化层6,使得GaN器件4上的金属焊球5能直接倒装在CMOS晶圆上,得到异质集成同步升压DC-DC转换器,实现了耐高压、高集成度的同步DC-DC转换器。
本发明提出的基于GaN/CMOS的异质集成同步DC-DC升压转换器芯片,可采用以下步骤设计实现:
第一步:指标设计。
选择电压模式反馈脉冲宽度调制方式。根据所需的开关频率以及电流电感纹波值计算得到所需电感电容值。对整个DC-DC转换器进行线性化分析,得到其传递函数。根据得到传递函数设计补偿网络,并在simulink中进行仿真,确定补偿网络中RC值。
第二步:原理图仿真。
功率管控制电路以及驱动电路采用CMOS工艺设计,其中包括带隙基准、误差放大器、比较器、锯齿波发生器等模块。高边功率管与低边功率管均使用增强型GaN HEMT器件,通过导入器件模型和CMOS工艺库联合仿真确定整体电路的原理图。
第三步:版图设计。
本设计需要采用两种形状pad,除了用于wire-bonding传统矩形pad,还需根据所选的GaN器件设计用于filp-chip的pad。版图绘制后提取RC参数进行后仿真,根据前仿性能对版图进行优化。
以上所述仅是本发明的优选实施方式,应当指出的是,对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
Claims (3)
1.基于异质集成的高功率密度同步升压DC-DC转换芯片,其特征在于,包括片上集成部分及片外部分,片上集成部分包括高边增强型GaN功率开关管、低边增强型GaN功率开关管以及基于CMOS工艺的CMOS控制电路,CMOS控制电路包括带隙基准、误差放大器、箝位电路、比较器、锯齿波发生器、电平位移电路、驱动电路模块,片外部分包括电感L和电容C;
锯齿波发生器的锯齿波信号输出端与比较器的负相输入端连接,带隙基准的输出端与误差放大器正相输入端连接,误差放大器的输出端与箝位电路的一端连接,箝位电路的另一端与比较器的正相输入端连接,误差放大器的负相输入端接入反馈电压VFB信号,比较器的输出端接电平位移电路的输入端,电平位移电路输出端连接两个Buf缓冲器的输入端,两个Buf缓冲器的输出端对应的与高边增强型GaN功率开关管以及低边增强型GaN功率开关管的栅极连接,电感L的一端与低边低增强型GaN功率开关管的漏极以及高边增强型GaN功率开关管的漏极相接,电感L的一端与电源的正极相接,高边增强型GaN功率开关管的源极接电容C的一端、负载的一端以及电阻RFB1的一端,低边低增强型GaN功率开关管的源极、电容C的另一端以及负载的另一端接电源的负极,即接地;电阻RFB1的另一端与电阻RFB2的一端相接,电阻RFB2的另一端接地,反馈电压VFB信号由电阻RFB1的另一端与电阻RFB2的一端相接点引出。
2.根据权利要求1所述基于异质集成的高功率密度同步升压DC-DC转换芯片,其特征在于,其中,所述的CMOS控制电路与高边增强型GaN功率开关管、低边增强型GaN功率开关管异质集成方法如下:
设计CMOS控制电路流片得到CMOS晶圆,在设计好的用于flip-chip的键合pad上制作一层凸点下金属化层,将高边增强型GaN功率开关管及低边增强型GaN功率开关管上的金属焊球焊接在凸点下金属化层上,使高边增强型GaN功率开关管及低边增强型GaN功率开关管直接倒装在CMOS晶圆上。
3.根据权利要求1所述基于异质集成的高功率密度同步升压DC-DC转换芯片,其特征在于,该基于异质集成的高功率密度同步升压DC-DC转换芯片的制作步骤如下:
第一步:指标设计
选择电压模式反馈脉冲宽度调制方式:根据所需的开关频率以及电流电感纹波值计算得到所需电感电容值,对整个DC-DC转换器进行线性化分析,得到其传递函数,根据得到传递函数设计补偿网络,并在simulink中进行仿真,确定补偿网络中RC值;
第二步:原理图仿真
功率管控制电路以及驱动电路采用CMOS工艺设计,包括带隙基准、误差放大器、比较器、锯齿波发生器模块,高边功率管与低边功率管均使用增强型GaN HEMT器件,通过导入器件模型和CMOS工艺库联合仿真确定整体电路的原理图;
第三步:版图设计
采用两种形状pad,除了用于wire-bonding传统矩形pad,还需根据所选的GaN器件设计用于filp-chip的pad,版图绘制后提取RC参数进行后仿真,根据前仿性能对版图进行优化。
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