CN113964196B - Depletion type power semiconductor structure, series structure and processing technology - Google Patents
Depletion type power semiconductor structure, series structure and processing technology Download PDFInfo
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Abstract
The invention relates to the technical field of semiconductor devices, in particular to a depletion type power semiconductor structure, a series structure and a processing technology, wherein the cell structure of the depletion type power semiconductor structure comprises: BJT post structure and JFET pre-structure; the JFET pre-stage structure is arranged in the BJT post-stage structure, namely the JFET pre-stage structure is adopted to replace the MOSFET structure of the IGBT device input stage. The depletion type power semiconductor structure does not need to grow a grid oxide film, so that the manufacturability problem caused by the arrangement of various grid oxide layers is solved, the grid oxide layers are easy to be connected in series, and the effects of higher yield and lower production cost can be achieved.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a depletion type power semiconductor structure, a series structure and a processing technology.
Background
As the solid-state semiconductor power device gradually permeates application scenes of traditional gas switches and mechanical switches, the industry puts higher demands on the switching capacity (voltage and current) of the solid-state semiconductor power device. Meanwhile, the improvement of the switching frequency plays a key role in reducing and lightening the weight of the product. Therefore, the demand for high-voltage, high-current, high-frequency solid-state semiconductor power devices is urgent.
The unipolar device in the solid semiconductor power device has good switching performance and is easy to drive, and the depletion device also has the advantage of easy series application; the bipolar device has good current circulation capability, and can effectively reduce the area of a chip and reduce the cost of the device under the same current. The organic combination of the two is originated from an IGBT device invented by Baliga in 1982, and inherits the output characteristic of a bipolar device and the input characteristic of a unipolar device. However, under the influence of materials, the silicon-based IGBT can only realize the switching of 8.4kV voltage class, and commercial devices often do not exceed 6.5kV, which is far from meeting the requirements of ultra-high voltage applications such as ultra-high voltage direct current transmission and the like, and meanwhile, brings great challenges for ultra-high voltage applications such as ultra-high voltage direct current transmission and the like. Researches find that the third generation semiconductor material taking silicon carbide as an example has wider band gap, can effectively improve the working voltage and meet the requirements of ultrahigh voltage application such as ultrahigh voltage direct current transmission and the like, so that the researches on the silicon carbide IGBT device have important significance. However, due to SiO2/SiC interface defects and productivity limitations, there are few units currently available that can produce reliable gate oxide layers for silicon carbide planar MOSFETs, and in other words, gate oxide layers for trench MOSFETs that have higher current densities and more complex manufacturing processes, and thus silicon carbide IGBTs based on MOSFET input stages still have practical manufacturability issues.
In addition, in the high-voltage field (6.5 kV and above), due to the influence of low doping of the drift region, the parasitic structure of the solid-state semiconductor power device is easy to generate secondary breakdown during heavy-current switching, and is limited by the secondary breakdown of the parasitic structure, and the single body voltage resistance of the solid-state semiconductor power device is difficult to meet the requirements of ultrahigh-voltage applications such as ultrahigh-voltage direct-current transmission. Therefore, compared with the immature high-voltage single device, the serial connection of a plurality of relatively low-voltage devices can obtain higher reliability, higher yield and lower production cost, but the serial connection application is complicated, and the high-efficiency large-scale serial connection is difficult to realize due to the fact that no absorption circuit exists in the prior art.
Disclosure of Invention
One of the objectives of the present invention is to provide a depletion mode power semiconductor structure that is easy to connect in series without growing a gate oxide film.
The invention provides a basic scheme I: a depletion mode power semiconductor structure, the cell structure of which comprises: a BJT post structure and a JFET pre-structure;
the JFET pre-stage structure is arranged in the BJT post-stage structure, namely the JFET pre-stage structure is adopted to replace the MOSFET structure of the IGBT device input stage.
The beneficial effects of the first basic scheme are as follows: the IGBT device has good characteristics, so that the IGBT device can meet the requirements of ultrahigh voltage application such as ultrahigh voltage direct current transmission and the like, and is limited by SiO2/SiC interface defects and productivity, researchers generally tend to research how to manufacture a reliable grid oxide layer for a silicon carbide planar MOSFET so as to solve the practical manufacturability problem of the silicon carbide IGBT based on the MOSFET input stage.
And the JFET preceding structure can realize large-scale, self-balancing and simple series connection cascade connection through a Super Cascode topology, and the JFET preceding structure in the structure replaces a MOSFET structure of an IGBT device input stage, so that the structure can perform large-scale, self-balancing and simple series connection cascade connection through the JFET preceding structure, thereby solving the problems that the existing series connection application is complex and high-efficiency large-scale series connection is difficult to realize.
In conclusion, the depletion type power semiconductor structure which does not need to grow a grid oxide film and is easy to be connected in series can achieve the effects of higher yield and lower production cost.
Further, BJT back level structure from top to bottom has set gradually: a metal collector, a collector region of a first conductivity type, a drift/base region of a second conductivity type, a buffer or stop region of a second conductivity type, an emitter region of a first conductivity type, a metal emitter;
JFET preceding stage structure from top to bottom has set gradually: the transistor comprises a grid structure, a source region of a second conduction type, a channel region of the second conduction type and a drift/drain region of the second conduction type;
the JFET pre-stage structure is arranged in the top layer of the drift/base region of the second conduction type, and the drift/drain region of the second conduction type is in contact with the drift/base region of the second conduction type;
collector regions of the first conductivity type are arranged on two sides of the top layer of the drift/base region of the second conductivity type and are in contact with a source region of the second conductivity type and a channel region of the second conductivity type;
the grid structure sets up in the channel region of second conductivity type, has set gradually from top to bottom: an insulator, a metal gate, a gate region of a first conductivity type; wherein the metal gate is disposed in a gate region of the first conductivity type; the gate regions of the first conductivity type are arranged in the channel region of the second conductivity type, and the source regions of the second conductivity type are arranged on two sides of the top layer of the channel region of the second conductivity type and are in contact with the gate regions of the first conductivity type.
Has the advantages that: and when the negative voltage absolute value reaches the pinch-off voltage, the width of the depletion layer is greater than or equal to the width of the channel region of the second conductivity type and completely occupies the channel region of the second conductivity type, and at the moment, the current between the source region of the second conductivity type of the JFET pre-stage structure and the drift/drain region of the second conductivity type approaches to zero. Since the drift/drain region of the second conductivity type of the JFET pre-stage structure is in contact with the drift/base region of the second conductivity type of the BJT post-stage structure, and the source region of the second conductivity type of the JFET pre-stage structure is in contact with the collector region of the first conductivity type of the BJT post-stage structure, when the JFET pre-stage structure is not conductive, the drift/base region of the second conductivity type of the BJT post-stage structure is not conductive to the collector region of the first conductivity type, and therefore the BJT post-stage structure is off, the current flowing through the entire device approaches zero, and the device is in an off state.
No voltage or positive voltage is applied between the metal gate and the metal emitter, a depletion layer is not formed on a gate region of the first conductivity type in the JFET pre-stage structure, so that a channel region of the second conductivity type can allow current to flow, at the moment, a drift/base region of the second conductivity type of the BJT post-stage structure and a collector region of the first conductivity type are communicated through the JFET pre-stage structure, under the amplification of hFE (common emitter current amplification factor) of the BJT post-stage structure, current flows from an emitter region of the first conductivity type of the BJT post-stage structure to the collector region of the first conductivity type, namely current flows from the emitter to the collector of the BJT post-stage structure, and the device is in an on state.
As the applied current becomes larger, that is, the positive voltage is applied between the metal gate and the metal emitter, the carrier concentration of the second conductivity type drift/base region of the BJT back-stage structure rises, and the carrier concentration of the second conductivity type drift/drain region of the JFET front-stage structure also rises at the same time, thereby reducing the on-resistance of the BJT back-stage structure and the JFET front-stage structure. Meanwhile, as the applied current becomes larger, the voltage of the collector region of the first conductivity type of the BJT post-stage structure rises, so that carriers are injected into the channel region of the second conductivity type of the JFET pre-stage structure, and the on-resistance of the JFET pre-stage structure is further reduced. The two effects together reduce the variation of the conduction voltage drop of the device with the current.
Further, the metal gate and the metal collector are isolated by an insulator.
Has the advantages that: the metal grid and the metal collector are isolated by an insulator, so that the contact of the metal grid and the metal collector is prevented, and the use of the whole device is influenced.
Further, the collector region of the first conductivity type is a heavily doped collector region of the first conductivity type;
the first conductive type emitter region is a heavily doped first conductive type emitter region;
the second conductive type source region is a heavily doped second conductive type source region;
the second conductive type drift/base region is a lightly doped second conductive type drift/base region;
the second conductivity type drift/drain region is a lightly doped second conductivity type drift/drain region.
Has the advantages that: the heavy doping mainly aims at reducing the potential barrier when metal is led out, ohmic contact is realized, and the heavy doping of the emitter region can increase the efficiency of injecting electrons of the emitter into the base region, so that high current gain is realized; the drift/drain region is lightly doped to reduce electric field peaks and hot electron effects.
Further, the first conductive type is a P type, and the second conductive type is an N type.
Has the advantages that: the first conduction type is P type, the second conduction type is N type, and therefore the structure of the depletion type power semiconductor structure is achieved.
The second purpose of the present invention is to provide a depletion type power semiconductor series structure formed by connecting depletion type power devices in series, wherein the depletion type power devices include a depletion type power semiconductor structure which is easy to connect in series without growing a gate oxide film, so as to improve the voltage endurance, the yield and the reliability of the depletion type power devices, and reduce the production cost.
The invention provides a second basic scheme: a depletion mode power semiconductor series structure comprising: and the multistage depletion type power devices comprising depletion type power semiconductor structures are connected in series with the low-voltage MOSFET, the emitter of each stage of depletion type power device is connected with the collector of the next stage of depletion type power device, and the emitter of the last stage of depletion type power device is connected with the drain of the low-voltage MOSFET.
The second basic scheme has the beneficial effects that: the collector of the first-stage depletion type power device in the depletion type power semiconductor series structure is the positive stage of the series structure, the source of the MOSFET is the negative electrode of the series structure, the grid of the MOSFET is the control electrode of the series structure, the whole series structure can be regarded as a voltage control switch device, and the voltage control switch device is similar to the MOSFET in specific use. The depletion type power devices are connected in series, so that the voltage tolerance is improved, the dependence on the monomer voltage in an ultrahigh voltage system is reduced, the yield of the depletion type power devices is improved, and the production cost is reduced. Meanwhile, the parasitic BJT of the input stage of the depletion type power semiconductor structure can be inhibited due to the low monomer voltage, so that the reliability of the depletion type power device is improved.
Furthermore, the grid electrode of each stage of depletion type power device is connected with a first resistor in series, and the other end of each first resistor is connected with the grid electrode of the next stage of depletion type power device through a capacitor.
Has the advantages that: the grid electrode of each stage of depletion type power device is connected with a first resistor in series, and the first resistors of all the grid electrodes are synchronously adjusted to control the overall switching speed of the series structure, so that the flexible switching between EMI and switching performance is realized. Meanwhile, the other end of each first resistor is connected with the grid electrode of the next depletion type power device through a capacitor, and the grid electrode is connected with the capacitor in series to regulate and control transient grid electrode current, so that the time sequence of the switching of the depletion type power devices is finely adjusted, and the zero adjustment of the instantaneous time error of the switching is realized. The series capacitor between the grid electrode and the first resistor of the depletion type power device can realize voltage balance in switching transient state, and the charge amount charged and discharged by each stage of capacitor under the corresponding interstage voltage is approximately equal to the sum of the charge of the grid electrode charged and discharged by the current stage in the switching process and the charge flowing through the upper stage of capacitor.
Further, a voltage stabilizing diode is connected in parallel to the capacitor.
Has the advantages that: the voltage stabilizing diode is connected in parallel between the capacitors, so that voltage balance can be realized in a long-time turn-off period.
Further, under the high-voltage condition, the voltage stabilizing diode adopts a PIN type diode.
Has the advantages that: under the high-voltage condition, the voltage stabilizing diode adopts a PIN diode, the avalanche characteristic of the PIN diode can realize the voltage stabilizing diode, and the static turn-off voltage drop of each stage of the series structure is approximately equal to the voltage stabilizing value of the voltage stabilizing diode under the current bias current.
Further, the voltage stabilizing diode is connected with a second resistor in series.
Has the advantages that: the series connection of the voltage stabilizing diode and the second resistor can reduce peak current and average current borne by the voltage stabilizing diode in the dynamic and static conversion process and when avalanche breakdown occurs in the series connection structure, so that the reliability of the series connection structure is improved.
Further, the capacitor adopts parasitic capacitance of a PIN diode.
The beneficial effects are that: because the grid charge of the JFET structure is highly related to the inter-stage voltage, in order to ensure that the series connection structure can always maintain the inter-stage voltage balance within a wide working voltage range, the capacitor is required to simulate the nonlinear capacitance characteristic of the grid of the JFET structure, so that the capacitor is realized by adopting the parasitic capacitance of the PIN diode, and the requirements can be met.
Further, the grid electrode of the first-stage depletion type power device is connected with the collector electrode of the first-stage depletion type power device through a resistance bias network, and the other end of the first resistor, which is serially connected with the grid electrode of the last-stage depletion type power device, is connected with the source electrode of the low-voltage MOSFET.
Has the advantages that: the other end of the first resistor connected in series with the grid of the last-stage depletion type power device is connected with the source electrode of the MOSFET, so that when the MOSFET is turned off, the drain electrode voltage of the MOSFET is pulled high by the current flowing through the series structure, namely the source electrode voltage of the last-stage depletion type power device is pulled high. Similarly, the turn-off of the last stage depletion mode power device triggers the turn-off of the last stage depletion mode power device until the first stage depletion mode power device turns off. The process is reversed when the MOSFET is switched on, namely, the first-stage depletion type power device is switched off and is switched off step by step. In combination with the dynamic balance using the capacitor and the static balance using the zener diode, the series structure can achieve self-driving and self-balancing, so that the characteristic thereof is similar to that of the ultra-high voltage MOSFET from the external view, and ultra-high voltage which is difficult to be achieved by a single device can be achieved.
The invention also aims to provide a processing technology of the depletion type power semiconductor structure which is easy to be connected in series and does not need to grow a grid oxide film so as to produce the depletion type power semiconductor structure which is easy to be connected in series and does not need to grow the grid oxide film.
The invention provides a third basic scheme: a process for manufacturing a depletion mode power semiconductor structure comprises the following steps:
providing a semiconductor substrate;
sequentially epitaxially growing a drift layer of a second conduction type and a channel layer of the second conduction type on the semiconductor substrate;
the third basic scheme has the beneficial effects that: compared with the traditional semiconductor structure processing technology, the depletion type power semiconductor structure produced by the technology has the advantages that impurities are injected into the channel layer, the groove is etched, and metal is deposited during processing to form the JFET pre-stage structure, the MOSFET structure of the input stage of the IGBT device is replaced, the original function of the IGBT device is not influenced, and after the MOSFET structure is replaced, the JFET pre-stage structure does not need to be provided with a grid oxide layer for a silicon carbide planar MOSFET or a grid oxide layer for a groove MOSFET, so that the problem of practical manufacturability caused by the arrangement of various grid oxide layers is solved, the processing difficulty is reduced, the yield is improved, and the production cost is reduced;
and the JFET preceding structure can realize large-scale, self-balancing and simple series cascade connection through a Super Cascode topology, and the JFET preceding structure in the semiconductor structure produced by the processing technology replaces the MOSFET structure of the IGBT device input stage, so that the large-scale, self-balancing and simple series cascade connection can be carried out through the JFET preceding structure, and the problems that the existing series connection application is complex and high-efficiency large-scale series connection is difficult to realize are solved.
Further, the implanting impurities, etching the trench and depositing metal in the channel layer to form a JFET pre-stage structure, includes:
selectively injecting impurities of a first conduction type and impurities of a second conduction type into the channel layer to form a collector region of the first conduction type of the BJT rear-stage structure and a source region of the second conduction type of the JFET front-stage structure;
and etching a groove in the channel layer, injecting or diffusing impurities of the first conduction type into the groove to form a groove region (channel region) of a JFET preceding stage structure, and depositing metal to complete a grid electrode structure.
Has the advantages that: the JFET pre-stage structure is processed according to the processing technology, when negative voltage is added, a groove region of the JFET pre-stage structure is acted by negative voltage to form a depletion layer, the depletion layer is widened along with the rise of the absolute value of the negative voltage, when the absolute value of the negative voltage reaches pinch-off voltage, the width of the depletion layer is larger than or equal to the width of a channel layer of the second conduction type, and the depletion layer completely occupies the channel region of the second conduction type, so that the JFET pre-stage structure is not conducted, and a BJT post-stage structure is not conducted, therefore, the BJT post-stage structure is turned off, the current flowing through the whole device is close to zero, and the device is in a turn-off state. When no voltage or positive voltage is applied, a depletion layer is not formed in the groove region of the JFET preceding stage structure, and the device is in a conducting state; and as the applied current becomes larger, the on-resistance of the BJT post-stage structure and the JFET pre-stage structure is reduced.
Further, the performing subsequent processing includes:
the interconnection among the cells of the top grid and the collector and the formation of an external electrode are completed through the metal layer and the insulating layer;
and thinning the wafer and metalizing the back surface to form a finished wafer.
Has the advantages that: the thickness of the drift region can be reduced by thinning the wafer, so that the conduction voltage drop and the internal resistance are reduced, and the thinning is beneficial to improving the heat dissipation capability.
Further, the semiconductor substrate includes: a semiconductor substrate of a first conductivity type or a semiconductor substrate of a second conductivity type;
if the semiconductor substrate is a semiconductor substrate of a first conduction type, before a drift layer of a second conduction type and a channel layer of the second conduction type are epitaxially grown on the semiconductor substrate in sequence, a field stop/buffer layer of the second conduction type is also epitaxially grown on the semiconductor substrate;
if the semiconductor substrate is a second conductive type semiconductor substrate, after thinning the wafer, injecting the first conductive type impurities to the back surface to form the first conductive type emitter region.
Has the advantages that: the two semiconductor substrates are compatible, so that the technical adaptability is wider.
Furthermore, the first conductive type is a P type, the second conductive type is an N type, and the doping concentrations of the layers and the regions are not all the same.
Has the beneficial effects that: the doping concentrations of the layers and the regions are not all the same, and the doping concentrations of the layers and the regions are adjusted according to actual requirements so as to realize the functions of the layers and the regions.
Drawings
FIG. 1 is a schematic diagram of a cell structure of an embodiment of a depletion mode power semiconductor structure according to the invention;
FIG. 2 is a schematic diagram of a depletion mode power semiconductor series structure in an embodiment of a depletion mode power semiconductor series structure according to the present invention;
FIG. 3 is a schematic flow chart of an embodiment of a process for fabricating a depletion mode power semiconductor structure according to the present invention.
Detailed Description
The following is further detailed by way of specific embodiments:
reference numerals in the drawings of the specification include: a metal collector 1, a collector region 2 of a first conductivity type, a drift/base region 3 of a second conductivity type, a buffer or stop region 4 of a second conductivity type, an emitter region 5 of a first conductivity type, a metal emitter 6, an insulator 7, a metal gate 8, a gate region 9 of a first conductivity type, a source region 10 of a second conductivity type, a channel region 11 of a second conductivity type, a drift/drain region 12 of a second conductivity type.
Example one
This embodiment is substantially as shown in figure 1: a depletion type power semiconductor structure is a semiconductor device, the device is formed by arranging and connecting cells in parallel, and the cell structure comprises: BJT post structure and JFET pre-structure;
the JFET pre-stage structure is arranged in the BJT post-stage structure, namely the JFET pre-stage structure is adopted to replace the MOSFET structure of the IGBT device input stage. Compared with the prior art that the MOSFET structure in the IGBT device needs the grid oxide layer for the silicon carbide planar MOSFET or the grid oxide layer for the trench MOSFET, the JFET pre-stage structure replaces the MOSFET structure of the IGBT device input stage, the original function of the IGBT device is not affected, and after the MOSFET structure is replaced, the JFET pre-stage structure does not need to be provided with the grid oxide layer for the silicon carbide planar MOSFET or the grid oxide layer for the trench MOSFET, so that the practical manufacturability problem caused by the arrangement of various grid oxide layers is solved. And the JFET preceding structure can realize large-scale, self-balancing and simple series cascade through Super Cascode topology, and the structure can carry out large-scale, self-balancing and simple series cascade through the JFET preceding structure, thereby solving the problems that the existing series application is complex and high-efficiency large-scale series connection is difficult to realize. The depletion type power semiconductor structure which does not need to grow a grid oxide film and is easy to be connected in series can achieve the effects of higher yield and lower production cost.
BJT back level structure has set gradually from top to bottom: a metal collector 1, a collector region 2 of a first conductivity type, a drift/base region 3 of a second conductivity type, a buffer or stop region 4 of a second conductivity type, an emitter region 5 of a first conductivity type, a metal emitter 6; the emitter region 5 of the first conductivity type is also its ohmic contact region;
JFET preceding stage structure from top to bottom has set gradually: a gate structure, a source region 10 of a second conductivity type, a channel region 11 of the second conductivity type, a drift/drain region 12 of the second conductivity type; the source region 10 of the second conductivity type is also an ohmic contact region thereof; the JFET pre-stage structure is arranged in the top layer of the drift/base region 3 of the second conductivity type, the drift/drain region 12 of the second conductivity type is in contact with the drift/base region 3 of the second conductivity type, and the drift/drain region 12 of the second conductivity type and the drift/base region 3 of the second conductivity type are shared in this embodiment; collector regions 2 of the first conductivity type are disposed on both sides of a top layer of a drift/base region 3 of the second conductivity type, and are in contact with a source region 10 of the second conductivity type and a channel region 11 of the second conductivity type;
the gate structure is arranged in the channel region 11 of the second conductivity type, and is sequentially arranged from top to bottom: an insulator 7, a metal gate 8, a gate region 9 of the first conductivity type; wherein the metal gate 8 is arranged in a gate region 9 of the first conductivity type; the gate regions 9 of the first conductivity type are arranged in the channel region 11 of the second conductivity type, the source regions 10 of the second conductivity type are arranged on both sides of the top layer of the channel region 11 of the second conductivity type, and are in contact with the gate regions 9 of the first conductivity type, and the metal gate 8 is separated from the metal collector 1 by the insulator 7.
The first conductive semiconductor is a P-type semiconductor, and the second conductive semiconductor is an N-type semiconductor; the doping concentration of each cutting area is not all the same, and specifically comprises the following steps:
the collector region 2 of the first conductivity type is a heavily doped collector region 2 of the first conductivity type;
the emitter region 5 of the first conductivity type is a heavily doped emitter region 5 of the first conductivity type;
the second conductive type source region 10 is a heavily doped second conductive type source region 10;
the second conductive-type drift/base region 3 is a lightly doped second conductive-type drift/base region 3;
the second conductivity type drift/drain region 12 is a lightly doped second conductivity type drift/drain region 12.
The doping concentration of the doping in the embodiment is 10 17 ～10 18 In the order of magnitude, the doping concentration of heavy doping is 10 18 ～10 19 The doping concentration of the order of magnitude and light doping is 10 15 ～10 16 Magnitude; the gate region 9 of the first conductivity type is a gate P/P + region with a doping concentration of 10 17 ～10 19 Magnitude.
The working principle is as follows: and a negative voltage is applied between the metal grid 8 and the metal emitter 6, a grid P/P + region in the JFET pre-stage structure is acted by the negative voltage to form a depletion layer, the depletion layer is widened along with the increase of the absolute value of the negative voltage, when the absolute value of the negative voltage reaches a pinch-off voltage, the width of the depletion layer is greater than or equal to the width of the channel N region and completely occupies the channel N region, and at the moment, the current between the source N + region and the drift/drain N-region of the JFET pre-stage structure approaches zero, namely the current between the source and the drain of the JFET pre-stage structure approaches zero, and almost no current flows. Because the drift/drain N-region of the JFET pre-stage structure is contacted with the drift/base N-region of the BJT post-stage structure, the source N + region of the JFET pre-stage structure is contacted with the collector P + region of the BJT post-stage structure, namely the drain of the JFET pre-stage structure is connected with the base of the BJT post-stage structure, and the source of the JFET pre-stage structure is connected with the collector of the BJT post-stage structure, when the JFET pre-stage structure is not conducted, the drift/base N-region of the BJT post-stage structure is not conducted to the collector P + region, namely the base of the BJT post-stage structure is not conducted to the collector, so the BJT post-stage structure is turned off, the current flowing through the whole device is close to zero, and the device is in a turned-off state.
No voltage or positive voltage is added between the metal grid 8 and the metal emitter 6, a depletion layer is not formed in a grid P region in the JFET pre-stage structure, so that a channel N region can allow current to flow, at the moment, a drift/base N-region and a collector P + region of the BJT post-stage structure are communicated through the JFET pre-stage structure, namely, a base and a collector of the BJT post-stage structure are communicated through the JFET pre-stage structure, under the hFE amplification of the BJT post-stage structure, current flows from an emitter P + region to a collector P + region of the BJT post-stage structure, namely, current flows from an emitter to a collector of the BJT post-stage structure, and the device is in a conducting state.
As the applied current increases, that is, the positive voltage is applied between the metal gate 8 and the metal emitter 6, the carrier concentration of the drift/base N-region of the BJT back-stage structure increases, and the carrier concentration of the drift/drain N-region of the JFET front-stage structure also increases, thereby reducing the on-resistance of the BJT back-stage structure and the JFET front-stage structure. Meanwhile, as the applied current becomes larger, the voltage of the collector P + region of the BJT post-stage structure rises, so that carriers are injected into the channel N region of the JFET pre-stage structure, and the on-resistance of the JFET pre-stage structure is further reduced. The two effects together reduce the variation of the conduction voltage drop of the device with the current.
Example two
This embodiment is substantially as shown in figure 2: a depletion type power semiconductor series structure is composed of a plurality of depletion type power devices (J1, J2, J3, J4, J5 and J6 in figure 2) containing the depletion type power semiconductor structure and a low-voltage MOSFET (M1 in figure 2) which are connected in series, wherein the emitter of each depletion type power device is connected with the collector of the next depletion type power device, the emitter of the last depletion type power device (J6 in figure 2) is connected with the DRAIN of the low-voltage MOSFET, DRAIN in figure 2 represents the positive pole of the whole device after series connection, GATE represents the control pole of the whole device after series connection, and SOURCE represents the negative pole of the whole device after series connection. In this embodiment, six stages are connected in series.
The grid electrode of each stage of depletion type power device is connected with a first resistor (RG 1, RG2, RG3, RG4, RG5 and RG6 in series in fig. 2), the other end of each first resistor is connected with the grid electrode of the next stage of depletion type power device through a capacitor (CG 1, CG2, CG3, CG4 and CG5 in fig. 2), and a voltage stabilizing diode (DA 1, DA2, DA3, DA4 and DA5 in fig. 2) is connected in parallel on the capacitor; each of the zener diodes is connected in series with a second resistor (RA 1, RA2, RA3, RA4, and RA5 in fig. 2), and the zener diodes are connected in series with the second resistors to reduce peak current and average current borne by the zener diodes during dynamic and static conversion and when avalanche breakdown occurs in the series structure, thereby improving reliability of the series structure. Because the grid charge of the JFET structure is highly related to the inter-stage voltage, in order to ensure that the series connection structure can always maintain the inter-stage voltage balance within a wide working voltage range, the capacitor is required to simulate the nonlinear capacitance characteristic of the grid of the JFET structure, therefore, the capacitor is realized by adopting the parasitic capacitance of the PIN diode and can meet the requirement.
The grid electrode of each stage of depletion type power device is connected with a first resistor in series, and the first resistors of all the grid electrodes are synchronously adjusted to control the overall switching speed of the series structure, so that the flexible switching between EMI and switching performance is realized. Meanwhile, the other end of each first resistor is connected with the grid of the next stage depletion type power device through a capacitor, and the grid is connected with the capacitor in series to regulate and control transient grid current, so that the time sequence of the switching of the depletion type power devices is finely adjusted, and the zero adjustment of the instantaneous time error of the switching is realized. The series capacitor between the grid electrode and the first resistor of the depletion type power device can realize voltage balance in switching transient state, and the charge amount charged and discharged by each stage of capacitor under the corresponding interstage voltage is approximately equal to the sum of the charge of the grid electrode charged and discharged by the current stage in the switching process and the charge flowing through the upper stage of capacitor. The voltage stabilizing diode is connected in parallel between the capacitors, so that voltage balance can be realized in a long-time turn-off period.
The grid electrode of the first-stage depletion type power device (J1 in figure 2) is connected with the collector electrode of the first-stage depletion type power device through a resistance bias network (RB 1 in figure 2), the grid electrode of each stage of depletion type power device is connected with the grid electrode of the next-stage depletion type power device through a first grid electrode resistor, a voltage stabilizing diode and a second grid electrode resistor, and the grid electrode of the last-stage depletion type power device is connected with the source electrode of the low-voltage MOSFET through the first grid electrode resistor. The other end of the first resistor connected in series with the grid of the last-stage depletion type power device is connected with the source electrode of the MOSFET, so that when the MOSFET is turned off, the drain electrode voltage of the MOSFET is pulled high by current flowing through the series structure, namely the source electrode voltage of the last-stage depletion type power device is pulled high. Similarly, the turn-off of the last stage depletion mode power device triggers the turn-off of the last stage depletion mode power device until the first stage depletion mode power device turns off. The process is reversed when the MOSFET is switched on, namely, the first-stage depletion type power device is switched off and is switched off step by step. In combination with the dynamic balance using the capacitor and the static balance using the zener diode, the series structure can achieve self-driving and self-balancing, so that the characteristic thereof is similar to that of the ultra-high voltage MOSFET from the external view, and ultra-high voltage which is difficult to be achieved by a single device can be achieved.
The collector of the first-stage depletion type power device in the depletion type power semiconductor series structure is the positive stage of the series structure, the source of the MOSFET is the negative electrode of the series structure, the grid of the MOSFET is the control electrode of the series structure, the whole series structure can be regarded as a voltage control switch device, and the voltage control switch device is similar to the MOSFET in specific use. The depletion type power devices are connected in series, so that the voltage tolerance is improved, the dependence on the monomer voltage in an ultrahigh voltage system is reduced, the yield of the depletion type power devices is improved, and the production cost is reduced. Meanwhile, the parasitic BJT of the input stage of the depletion type power semiconductor structure can be inhibited due to the lower monomer voltage, so that the reliability of the depletion type power device is improved.
EXAMPLE III
This embodiment is substantially as shown in figure 3: a process for manufacturing a depletion mode power semiconductor structure comprises the following steps:
providing a semiconductor substrate; a semiconductor substrate comprising: a semiconductor substrate of a first conductivity type or a semiconductor substrate of a second conductivity type;
sequentially epitaxially growing a drift layer of a second conduction type and a channel layer of the second conduction type on the semiconductor substrate; if the semiconductor substrate is a semiconductor substrate of a first conduction type, before a drift layer of a second conduction type and a channel layer of the second conduction type are epitaxially grown on the semiconductor substrate in sequence, a field stop/buffer layer of the second conduction type is also epitaxially grown on the semiconductor substrate;
injecting impurities, etching a groove and depositing metal in the channel layer to form a JFET (junction field effect transistor) pre-stage structure; the method comprises the following specific steps:
selectively injecting impurities of a first conduction type and impurities of a second conduction type into the channel layer to form a collector region 2 of the first conduction type of a BJT rear-stage structure and a source region 10 of the second conduction type of a JFET front-stage structure;
etching a groove in the channel layer, injecting or diffusing impurities of the first conductivity type into the groove to form a groove region of the JFET preceding stage structure, namely a gate region 9 of the first conductivity type, and depositing metal to complete a gate structure;
performing subsequent processing, namely a subsequent process; the method specifically comprises the following steps: the interconnection among the cells of the top grid and the collector and the formation of an external electrode are completed through the metal layer and the insulating layer; in addition, the subsequent processes also include general processing processes, such as: the termination of the single device is realized by using a field ring, the top layer protection is realized by using a selective PI film, and metal discs of a top gate and a source of the single device are arranged and wired; wherein the use of the field ring to effect the termination of the cell device comprises: injecting alternate first conductive type impurities and/or second conductive type impurities at the periphery of the cellular array to realize the termination of the single device; the general processing technique is the prior art, and the selection and implementation thereof are decided by the implementer, and the details are not described in this embodiment.
Thinning and back metallization are carried out on the wafer to form a finished wafer; if the semiconductor substrate is a second conductive type semiconductor substrate, after thinning the wafer, the first conductive type impurity is also injected to the back surface to form the first conductive type emitter region 5. The depletion type power semiconductor structure is realized by arranging the depletion type power semiconductor structure on a wafer, namely, the processing technology is carried out on the wafer.
In this embodiment, the first conductive type is P-type, the second conductive type is N-type, and the doping concentrations of each layer and each region are not all the same, specifically: the drift layer of the second conduction type is an N-type drift layer; the channel layer of the second conduction type is an N-type channel layer; the field stop/buffer layer of the second conduction type is an N-type field stop/buffer layer; selectively injecting impurities of a first conductive type and impurities of a second conductive type into the channel layer, wherein the impurities of the first conductive type and the impurities of the second conductive type are P + type impurities and N + type impurities, and forming a collector P + region of a BJT rear-stage structure and a source N + region of a JFET front-stage structure; injecting or diffusing the first conductive type impurity into the groove to form a P/P + type impurity; and injecting the first conductive type impurity into the back surface to form an emitter P + region, wherein the first conductive type impurity is a P + type impurity. The semiconductor structure produced by the processing technology is the depletion type power semiconductor structure described in the first embodiment, and the effects and the working principle of the depletion type power semiconductor structure are not described in detail in this embodiment.
The foregoing is merely an example of the present invention, and common general knowledge in the field of known specific structures and characteristics is not described herein in any greater extent than that known in the art at the filing date or prior to the priority date of the application, so that those skilled in the art can now appreciate that all of the above-described techniques in this field and have the ability to apply routine experimentation before this date can be combined with one or more of the present teachings to complete and implement the present invention, and that certain typical known structures or known methods do not pose any impediments to the implementation of the present invention by those skilled in the art. It should be noted that, for those skilled in the art, without departing from the structure of the present invention, several changes and modifications can be made, which should also be regarded as the protection scope of the present invention, and these will not affect the effect of the implementation of the present invention and the practicability of the patent. The scope of the claims of the present application shall be determined by the contents of the claims, and the description of the embodiments and the like in the specification shall be used to explain the contents of the claims.
Claims (15)
1. A depletion-mode power semiconductor structure, characterized by: the cellular structure comprises: a BJT post structure and a JFET pre-structure;
the JFET pre-stage structure is arranged in the BJT post-stage structure, and replaces the MOSFET structure of the IGBT device input stage with the JFET pre-stage structure;
BJT back level structure has set gradually from top to bottom: a metal collector, a collector region of a first conductivity type, a first drift region, i.e. a base region, of a second conductivity type, a buffer or stop region of a second conductivity type, an emitter region of a first conductivity type, a metal emitter;
JFET preceding stage structure has set gradually from top to bottom: a source region of the second conductivity type, a channel region of the second conductivity type, a second drift region of the second conductivity type, i.e. a drain region; a grid structure is also arranged in the JFET preceding stage structure;
the JFET pre-stage structure is arranged in the top layer of the first drift region of the second conduction type, and the second drift region of the second conduction type is in contact with the first drift region of the second conduction type;
collector regions of the first conductivity type are arranged on two sides of the top layer of the first drift region of the second conductivity type and are in contact with a source region of the second conductivity type and a channel region of the second conductivity type;
the grid structure sets up in the channel region of second conductivity type, has set gradually from top to bottom: an insulator, a metal gate, a gate region of a first conductivity type; wherein the metal gate is disposed in a gate region of the first conductivity type; the gate region of the first conduction type is arranged in the channel region of the second conduction type, and the source regions of the second conduction type are arranged on two sides of the top layer of the channel region of the second conduction type and are in contact with the gate region of the first conduction type; the metal grid and the metal collector are isolated by an insulator;
and when the negative voltage absolute value reaches the pinch-off voltage, the width of the depletion layer is greater than or equal to that of the channel region of the second conduction type.
2. The depletion-mode power semiconductor structure of claim 1, wherein: the collector region of the first conduction type is a heavily doped collector region of the first conduction type;
the first conductive type emitter region is a heavily doped first conductive type emitter region;
the second conductive type source region is a heavily doped second conductive type source region;
the first drift region of the second conductivity type is a lightly doped first drift region of the second conductivity type;
the second drift region of the second conductivity type is a lightly doped second conductivity type second drift region.
3. The depletion-mode power semiconductor structure of claim 1, wherein: the first conductive type is a P type, and the second conductive type is an N type.
4. A depletion mode power semiconductor series structure characterized by: a depletion mode power device employing a structure including the depletion mode power semiconductor of any one of claims 1-3, comprising: the multistage depletion type power device is connected with the low-voltage MOSFET in series, the emitter of each stage of depletion type power device is connected with the collector of the next stage of depletion type power device, and the emitter of the last stage of depletion type power device is connected with the drain of the low-voltage MOSFET.
5. Depletion mode power semiconductor series arrangement according to claim 4, characterized in that: the grid electrode of each stage of depletion type power device is connected with a first resistor in series, and the other end of each first resistor is connected with the grid electrode of the next stage of depletion type power device through a capacitor.
6. Depletion mode power semiconductor series arrangement according to claim 5, characterized in that: the capacitor is connected with a voltage stabilizing diode in parallel.
7. Depletion mode power semiconductor series arrangement according to claim 6, characterized in that: under the high-voltage condition, the voltage stabilizing diode adopts a PIN diode.
8. Depletion mode power semiconductor series arrangement according to claim 6, characterized in that: the voltage stabilizing diode is connected in series with the second resistor.
9. Depletion mode power semiconductor series arrangement according to claim 5, characterized in that: the capacitor adopts parasitic capacitance of PIN type diode.
10. Depletion mode power semiconductor series arrangement according to claim 6, characterized in that: the grid electrode of the first-stage depletion type power device is connected with the collector electrode of the first-stage depletion type power device through a resistance bias network, and the other end of a first resistor connected with the grid electrode of the last-stage depletion type power device in series is connected with the source electrode of the low-voltage MOSFET.
11. A depletion mode power semiconductor structure processing technology for processing the depletion mode power semiconductor structure according to any one of claims 1 to 3, comprising the following contents:
providing a semiconductor substrate;
sequentially epitaxially growing a drift layer of a second conduction type and a channel layer of the second conduction type on the semiconductor substrate;
the method is characterized in that: further comprising:
injecting impurities, etching a groove and depositing metal in the channel layer to form a JFET (junction field effect transistor) pre-stage structure;
and carrying out subsequent processing.
12. The process of claim 11, wherein: injecting impurities, etching a groove and depositing metal in the channel layer to form a JFET (junction field effect transistor) preceding stage structure, and the method comprises the following steps:
selectively injecting impurities of a first conductive type and impurities of a second conductive type into the channel layer to form a collector region of the first conductive type of the BJT rear-stage structure and a source region of the second conductive type of the JFET front-stage structure;
and etching a groove in the channel layer, injecting or diffusing impurities of the first conduction type into the groove to form a groove region of a JFET preceding stage structure, and depositing metal to complete a grid structure.
13. The process of claim 11, wherein: the performing of the subsequent processing includes:
the interconnection among the cells of the top grid and the collector and the formation of an external electrode are completed through the metal layer and the insulating layer;
and thinning the wafer and metalizing the back surface to form a finished wafer.
14. The process of claim 11, wherein: the semiconductor substrate includes: a semiconductor substrate of a first conductivity type or a semiconductor substrate of a second conductivity type;
if the semiconductor substrate is a semiconductor substrate of a first conduction type, before a drift layer of a second conduction type and a channel layer of the second conduction type are epitaxially grown on the semiconductor substrate in sequence, a field stop region or a buffer layer of the second conduction type is also epitaxially grown on the semiconductor substrate;
if the semiconductor substrate is a second conductive type semiconductor substrate, after thinning the wafer, injecting impurities of the first conductive type into the back surface to form an emitter region of the first conductive type.
15. The process of claim 12, wherein: the first conductive type is P type, the second conductive type is N type, and the doping concentration of each layer and each region is not all the same.
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