CN113964143A - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN113964143A CN113964143A CN202111389606.5A CN202111389606A CN113964143A CN 113964143 A CN113964143 A CN 113964143A CN 202111389606 A CN202111389606 A CN 202111389606A CN 113964143 A CN113964143 A CN 113964143A
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/126—Shielding, e.g. light-blocking means over the TFTs
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Abstract
The application discloses array substrate, display panel and display device, array substrate includes substrate and a plurality of bearing insulating layer, range upon range of formation in substrate one side, each bears the insulating layer and deviates from a side surface of substrate and is formed with the device cambium of patterning, bear the insulating layer and be inorganic material layer, at least one bears the insulating layer and is equipped with the planarization layer towards a side surface of substrate, so that bear the insulating layer planarization, the surface that the planarization layer deviates from substrate one side is the plane, the planarization layer is organic material layer. The application provides array substrate will bear insulating layer planarization through setting up the planarization layer, avoids appearing bearing insulating layer step department stress concentration's phenomenon, bears the insulating layer and realizes the planarization back, still can improve array substrate's rigidity and support nature, has further improved impact resistance, and simultaneously, the planarization layer that newly increases can absorb impact energy for array substrate's shock resistance is stronger.
Description
Technical Field
The application belongs to the technical field of display, and particularly relates to an array substrate, a display panel and a display device.
Background
With the development of display technology, the screen occupation ratio requirement of display equipment is higher and higher, and the flexible display panel has the advantages of being bendable, good in flexibility, light and thin in size, low in power consumption and the like, so that a display device with folding performance can be formed, the requirement of people for pursuing large-screen display is met, and the user experience is improved.
Along with the flexible display panel has improved bending resistance, the thickness of the flexible display panel is reduced, and the rigidity and the supporting performance of the flexible display panel are weaker and weaker.
Disclosure of Invention
The embodiment of the application provides an array substrate, a display panel and a display device, wherein the array substrate has stronger rigidity and support property, and the impact resistance is further improved.
An embodiment of a first aspect of an embodiment of the present application provides an array substrate, including:
a substrate;
the bearing insulating layers are formed on one side of the substrate in a stacked mode, a patterned device forming layer is formed on the surface, facing away from the substrate, of one side of each bearing insulating layer, the bearing insulating layers are inorganic material layers, a planarization layer is arranged on the surface, facing towards the substrate, of one side of at least one bearing insulating layer to enable the bearing insulating layers to be planarized, the surface, facing away from the substrate, of each planarization layer is a plane, and each planarization layer is an organic material layer.
According to an embodiment of the first aspect of the present application, two of the carrier insulating layers adjacent to each other in a direction perpendicular to the substrate include a first layer on a side close to the substrate and a second layer on a side away from the substrate, and a portion of the planarization layer is formed between the device formation layer and the second layer between the first layer and the second layer.
According to any of the embodiments of the first aspect of the present application, between two adjacent carrier insulating layers in a direction perpendicular to the substrate, the planarization layer is disposed on the same layer as the device formation layer.
According to any one of the embodiments of the first aspect of the present application, at least a portion of the carrier insulating layer is patterned, and the array substrate further includes a sub-planarization layer disposed in the same layer as at least a portion of the patterned carrier insulating layer, where the sub-planarization layer is an organic material layer.
According to any of the preceding embodiments of the first aspect of the present application, a plurality of planarization layers of different materials are included between two adjacent carrier insulation layers in a direction perpendicular to the substrate.
According to any of the preceding embodiments of the first aspect of the present application, the material of the planarization layer is at least one of polyethylene terephthalate, polycarbonate, polyethylene or polyacrylate, and polyimide.
According to any of the preceding embodiments of the first aspect of the present application, the device formation layer is used for forming a transistor and a capacitor, and includes a conductor layer and a semiconductor layer for forming a transistor and a capacitor;
preferably, the semiconductor layer includes at least one of polysilicon and metal oxide; the conductor layer is made of metal.
According to any of the preceding embodiments of the first aspect of the present application, the method further comprises an additional planarization layer on a side of the transistor and the capacitor facing away from the substrate, the additional planarization layer covering the transistor and the capacitor.
Embodiments of the second aspect of the present application further provide a display panel, including any one of the array substrates provided in the first aspect of the present application.
Embodiments of the third aspect of the present application further provide a display device including any one of the display panels provided in the second aspect of the present application.
The array substrate provided by the embodiment of the application comprises a substrate, a device forming layer, a bearing insulating layer and a planarization layer, wherein the planarization layer is formed on one side, facing the substrate, of at least part of the bearing insulating layer, namely the planarization layer is formed below at least part of the bearing insulating layer, and the surface of one side, away from the substrate, of the planarization layer is a plane, so that the bearing insulating layer formed on the planarization layer is planarized conveniently. Since the bearing insulating layer is an inorganic material layer and the device forming layer is arranged in a patterning mode, namely the device forming layer comprises a plurality of parts located on different layers instead of the whole layer, when the bearing insulating layer is directly formed on the device forming layer, the bearing insulating layer comprises a part formed above the device forming layer and a part located on the same layer with the device forming layer, the bearing insulating layer is provided with steps on the periphery of the device forming layer, and stress in the bending process is easily concentrated on the steps. According to the array substrate, after the bearing insulating layer is flattened by the flattening layer, the risk of stress concentration at the step can be reduced; meanwhile, after the planarization layer is arranged on one side, facing the substrate, of the bearing insulating layer on the upper layer, the bearing insulating layer on the lower layer can be separated from the bearing insulating layer on the lower layer through the planarization layer, the overlapping and deposition of the bearing insulating layers with multiple inorganic material layers are avoided, so that the stress between the adjacent bearing insulating layers is reduced, the planarization layer can absorb impact energy, the impact resistance of the array substrate is stronger, the rigidity and the support of the array substrate can be improved after the planarization of the bearing insulating layers is realized, and the impact resistance is further improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of another array substrate provided in the present embodiment;
fig. 3 is a schematic structural diagram of another array substrate provided in the present application;
fig. 4 is a schematic structural diagram of another array substrate provided in an embodiment of the present application;
fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present application.
In the drawings:
10-an array substrate; 1-a substrate; 11-a first support layer; 12-a first buffer layer; 13-a second support layer; 14-a second buffer layer; 2-a carrier insulating layer; 21-a first layer; 22-a second layer; 3-device formation layer; 31-a polysilicon semiconductor layer; 32-a metal oxide semiconductor layer; 33-a gate; 34-source drain; 35-capacitance; 4-a planarization layer; 5-sub planarization layer; 6-additional planarization layer; 20-display panel, 7-light emitting layer; 8-an encapsulation layer; 9-a touch layer; 16-a support layer; 11-a polarizer layer; 12-an optical glue layer; 13-a cover plate; 14-a buffer layer; 15-steel sheet; 30-display device.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The inventor finds that, as the bending resistance of the foldable display panel is improved, the thickness of the display panel is reduced, and the rigidity and the support performance of the display panel are weaker and weaker because: in the stack design of the array substrate in the display panel, on one hand, the graphic design of some inorganic films is complex, so that residual stress and defects are easy to exist in the inorganic film deposition process, particularly in a section difference area and a hole digging area; on the other hand, when the multiple inorganic film layers are stacked and deposited, residual stress and defects are easily generated on the interfaces of the adjacent film layers; when the inorganic film layer with residual stress and defects is impacted by external force, on one hand, the inorganic film layer is deformed due to poor support of the display panel to accelerate the fragmentation; on the other hand, the array substrate is subjected to forward stress impact on the light-emitting surface side of the display panel and reverse gravitational waves departing from the light-emitting surface side, so that the array substrate is prone to fracture due to stress concentration in a non-flat area, particularly a stepped area of the array substrate; after the crack of the inorganic film layer is generated, the crack can gradually extend to the nearby film layer in the impact process, so that the nearby film layer is broken, the rigidity and the support of the array substrate are weaker and weaker, the electric stacking structure is damaged, and the problem of failure of bright and dark points finally occurs. Based on the research on the above problems, the inventors have provided an array substrate, a display panel, and a display device having better bending resistance.
For better understanding of the present application, the array substrate, the display panel and the display device according to the embodiments of the present application will be described in detail below with reference to fig. 1 to 6.
Referring to fig. 1, an embodiment of the present invention provides an array substrate 10, including a substrate 1 and a plurality of insulating bearing layers 2 stacked on one side of the substrate 1, wherein a patterned device forming layer 3 is formed on a surface of each insulating bearing layer 2 facing away from the substrate 1, the insulating bearing layers 2 are inorganic material layers, a planarization layer 4 is disposed on a surface of at least one insulating bearing layer 2 facing toward the substrate 1 to planarize the insulating bearing layer 2, a surface of the planarization layer 4 facing away from the substrate 1 is a plane, and the planarization layer 4 is an organic material layer.
The array substrate 10 provided by the present application includes a substrate 1, a device forming layer 3, a carrier insulating layer 2 and a planarization layer 4, wherein the planarization layer 4 is formed on at least a portion of the carrier insulating layer 2 facing the substrate 1, that is, the planarization layer 4 is formed below at least a portion of the carrier insulating layer 2, and since a surface of a side of the planarization layer 4 facing away from the substrate 1 is a plane, the carrier insulating layer 2 formed on the planarization layer 4 is planarized. Since the insulating carrier layer 2 is an inorganic material layer and the device formation layer 3 is disposed in a patterned manner, that is, the device formation layer 3 includes a plurality of portions located on different layers rather than an entire layer, when the insulating carrier layer 2 is directly formed on the device formation layer 3, the insulating carrier layer 2 includes a portion formed above the device formation layer 3 and a portion located on the same layer as the device formation layer 3, the insulating carrier layer 2 is formed with a step at the periphery of the device formation layer 3, and stress during bending is easily concentrated at the step. According to the array substrate, after the bearing insulating layer 2 is flattened by the flattening layer 4, the risk of stress concentration at a step can be reduced; meanwhile, after the planarization layer 4 is arranged on one side, facing the substrate 1, of the bearing insulating layer 2 on the upper layer, the bearing insulating layer 2 on the lower layer can be separated from the bearing insulating layer 2 on the lower layer through the planarization layer 4, and the overlapping and deposition of the bearing insulating layers 2 with multiple inorganic material layers are avoided, so that the stress between the adjacent bearing insulating layers 2 is reduced, the planarization layer 4 can absorb impact energy, the impact resistance of the array substrate 10 is stronger, after the planarization of the bearing insulating layer 2 is realized, the rigidity and the support of the array substrate 10 can be improved, and the impact resistance is further improved.
Compared with the inorganic material layer, the organic material layer has better buffering capacity, better supporting performance and insulating performance and stronger high-temperature resistance. In the preparation of the device forming layer 3, a high temperature process is generally required, so that the device forming layer 3 needs to be prepared on the insulating carrier layer 2, and the insulating carrier layer 2 does not need to be an inorganic material layer so as to avoid damage to the insulating carrier layer 2. The inorganic insulating layer easily forms a step around the device formation layer 3 due to its material characteristics, and the organic material layer may cover the device formation layer 3 and maintain the flatness of the side facing away from the substrate 1.
The substrate 1 may be a composite substrate 1, and includes a first support layer 11, a first buffer layer 12, a second support layer 13, and a second buffer layer 14, which are sequentially stacked. The first and second support layers 11 and 13 may be made of Polyimide (PI), and the first and second buffer layers 12 and 14 may be made of silicon oxide (SiOx) or amorphous silicon (a-Si). The preparation process of the substrate 1 may be: coating PI slurry on a glass substrate and baking to form a first supporting layer 11; preparing a first buffer layer 12 on the first support layer 11 using a Chemical Vapor Deposition (CVD) preparation process; coating PI slurry on the first buffer layer 12 and baking to form a second supporting layer 13; the second buffer layer 14 is prepared on the second support layer 13 using a Chemical Vapor Deposition (CVD) preparation process. Then, a part of the device formation layer 3 may be directly prepared on the substrate 1.
In a possible embodiment, as shown in fig. 1, the planarization layer 4 is disposed on a side surface of the entire carrier insulation layer 2 facing the substrate 1, so that absorption of impact energy by the array substrate 10 can be improved, impact resistance of the array substrate 10 can be improved, and bending resistance of the array substrate 10 can be increased.
In another possible embodiment, as shown in fig. 2 and 3, a planarization layer 4 is disposed on a side surface of a part of the carrier insulating layer 2 facing the substrate 1, so that the number of planarization layers 4 used can be reduced and the step deposition of a part of the carrier insulating layer 2 can be remained under the condition of ensuring the impact resistance of the array substrate 10, thereby reducing the number of processes for preparing the planarization layer 4 and reducing the use cost of the planarization layer 4.
In one possible embodiment, as shown in fig. 3, two of the carrier insulating layers 2 adjacent to each other in the direction perpendicular to the substrate 1 include a first layer 21 on the side close to the substrate 1 and a second layer 22 on the side away from the substrate 1, and the partial planarization layer 4 is formed between the device formation layer 3 and the second layer 22 between the first layer 21 and the second layer 22.
In the above embodiment, in the adjacent planarization layer 4 and the device forming layer 3, the planarization layer 4 covers the device forming layer 3, so that the surface of the planarization layer 4 on the side away from the substrate 1 is a complete layer, and the bearing insulating layer 2 on the planarization layer 4 is in complete contact with the planarization layer 4, thereby achieving planarization of the bearing insulating layer 2 to a great extent, and since the bearing insulating layer 2 is an inorganic material layer, after the bearing insulating layer 2 is planarized, local stress concentration in the array substrate 10 is prevented, and meanwhile, the rigidity and the support of the array substrate 10 are improved.
In another possible embodiment, as shown in fig. 4, the planarization layer 4 is disposed in the same layer as the device formation layer 3 between two adjacent carrier insulating layers 2 in a direction perpendicular to the substrate 1.
In the above embodiment, the planarization layer 4 and the device forming layer 3 are formed between two adjacent carrier insulating layers 2 in the direction perpendicular to the substrate 1, and the planarization layer 4 and the device forming layer 3 are disposed on the same layer, so that the thickness of the array substrate can be reduced and the light and thin structure can be realized; on the other hand, the material of the planarization layer 4 can be saved, thereby reducing the cost.
In one possible embodiment, as shown in fig. 4, at least a portion of the carrier insulating layer 2 is patterned, and the array substrate 10 further includes a sub-planarization layer 5 disposed on the same layer as the at least a portion of the patterned carrier insulating layer 2, where the sub-planarization layer 5 is an organic material layer.
In the above embodiment, at least a part of the carrier insulating layer 2 is patterned, specifically, only a region corresponding to the device forming layer 3 formed on the carrier insulating layer 2 is left in at least a part of the carrier insulating layer 2, a region not corresponding to the device forming layer 3 on the carrier insulating layer 2 in the carrier insulating layer 2 is removed, and a region not corresponding to the device forming layer 3 on the carrier insulating layer 2 in the carrier insulating layer 2 is replaced with the sub-planarization layer 5 after the removal. I.e. both the adjacent carrier insulating layer 2 and the device forming layer 3 are patterned such that an orthographic projection of the carrier insulating layer 2 on its device forming layer 3 adjacent in the direction away from the substrate covers this device forming layer 3.
Since the sub-planarization layer 5 is an organic material layer, in the above embodiment, after the sub-planarization layer 5 is replaced with the region of the insulating support layer 2 not covered by the device formation layer 3 adjacent to the insulating support layer, the use of the organic material layer in the array substrate 10 is increased, the absorption of the impact energy by the array substrate 10 is improved, and the impact resistance of the array substrate 10 is improved.
In a possible embodiment, a plurality of planarization layers 4 with different materials are included between two adjacent carrier insulation layers 2 in a direction perpendicular to the substrate 1, so that the use of organic material layers in the array substrate 10 is increased, the absorption capacity of the array substrate 10 for impact energy is improved, and the impact resistance of the array substrate 10 is improved.
In a possible embodiment, the material of the planarization layer 4 may be at least one of Polyimide (PI), polyethylene terephthalate, polycarbonate, polyethylene or polyacrylate, and polyimide.
Specifically, the material of the planarization layer 4 may also be other high-temperature-resistant organic materials, and the application is not particularly limited.
The preparation process of the planarization layer 4 comprises the following steps: an organic material is coated over the device formation layer 3 and baked to form a planarization layer 4.
In the array substrate 10, the preparation process of the carrier insulating layer 2 includes: and a CVD preparation process is used for preparing the planarization layer 4.
The array substrate 10 includes devices such as transistors and capacitors 35, and therefore, the device formation layer 3 includes a semiconductor layer for forming an active layer of the transistors, and the material of the semiconductor layer includes at least one of a polysilicon (e.g., p-Si) semiconductor layer and a metal oxide (e.g., IGZO) semiconductor layer, and may further include an amorphous silicon material, and the like; the device forming layer 3 further includes a conductor layer for forming a gate 33, a source/drain 34, and an upper plate and a lower plate of the capacitor 35 in the transistor, and the conductor layer is made of metal, for example: the metal used to form the gate electrode 33 may be molybdenum (Mo) or titanium (Ti) or silver (ag), etc., and the metal used to form the source-drain electrode 34 may be a laminated titanium/aluminum/titanium composite structure.
In the array substrate 10, when the transistor is made of polysilicon, a layer of amorphous silicon (a-Si) may be deposited on the substrate 1 or the insulating support layer 2 by a CVD process, and then polysilicon (P-Si) is generated by an ELA (ELA) process, and then a patterned polysilicon film layer is formed by a yellow light process (photoresist coating, exposure and development), a dry etching process, and a photoresist stripping process.
In the array substrate 10, the preparation process of the conductor layer includes: a metal layer (e.g., Mo) is deposited by PVD process, followed by photolithography (photoresist-exposure-development) and dry etching and photoresist stripping to form a patterned conductor layer.
When the source/drain electrode 34 is manufactured, blind holes are formed on the film layer between the position where the source/drain electrode 34 is manufactured and the source/drain regions of the active layer and the gate electrode 33 through a photolithography process (photoresist coating-exposure-development) and a dry etching and photoresist removing process. A metal film (such as Ti/Al/Ti) is deposited by PVD process at the position where the source/drain electrode 34 is prepared, and then the patterned source/drain electrode 34 is formed by photolithography process (photoresist coating-exposure-development) and dry etching and photoresist stripping process.
In a possible embodiment, the array substrate 10 further includes an additional planarization layer 6 on a side of the device formation layer 3 away from the substrate 1, the side facing away from the substrate 1.
In a possible embodiment, the device formation layer 3 comprises conductor and semiconductor layers for forming transistors and capacitors 35, and the additional planarization layer 6 covers the transistors and capacitors 35.
In the above embodiment, the material of the additional planarization layer 6 may be at least one of polyethylene terephthalate, polycarbonate, polyethylene, polyacrylate, and Polyimide (PI), and the additional planarization layer 6 is used to cover the device formation layer 3, such as the source/drain electrode 34 located at the top of the device formation layer 3, so as to form a planar surface, which is convenient for preparing the subsequent film layer.
The present application further provides a display panel 20, as shown in fig. 5, including any one of the array substrates 10 provided in the above embodiments of the present application.
When the display panel 20 is an OLED display panel, the display panel further includes a light emitting layer 7 formed on a side of the additional planarization layer 6 away from the substrate 1, and the light emitting layer includes a patterned anode, and a pixel defining layer, an auxiliary supporting layer, and the like, an opening corresponding to the anode is formed on the pixel defining layer one by one to expose the anode, and the anode may have a structure of a first indium tin oxide material layer, a silver material layer, and a second indium tin oxide material layer stacked in a direction away from the substrate; the auxiliary support layer is used for supporting the mask plate so as to form a common layer, a light-emitting material layer, a cathode layer and the like through an evaporation process. The common layer is an entire layer covering the pixel defining layer, and includes a portion located in the pixel opening and a portion located on a side of the pixel defining layer away from the substrate 1, and the common layer includes a portion or all of an Electron Injection Layer (EIL), an Electron Transport Layer (ETL), a Hole Blocking Layer (HBL), an Electron Blocking Layer (EBL), a Hole Transport Layer (HTL), and a Hole Injection Layer (HIL). The light emitting material layer includes a phosphorescent material for emitting red light and green light, a fluorescent material for emitting blue light, and the like.
The preparation process of the pixel defining layer and the supporting layer 16 comprises the following steps: the raw materials are coated on predetermined positions, respectively, and exposed and developed to form a patterned pixel defining layer or supporting layer 16.
The display panel 20 may be a liquid crystal display panel or the like, and the present application is not particularly limited.
In the display panel 20 provided by the present application, the neutral plane of the display panel 20 can be adjusted by adjusting the thickness of each planarization layer and the carrier insulating layer 2 in the array substrate 10 and adjusting the number of the planarization layers, so as to improve the bending resistance of the display panel 20. Specifically, the number and thickness information of each film layer can be simulated, and the thicknesses of each planarization layer and the carrier insulating layer 2 are adjusted to obtain the optimal combination, so that the display panel 20 with high bending resistance is obtained, poor display is prevented, and the display quality is improved.
The present application also provides a display device 30, as shown in fig. 6, including the display panel 20 provided in the above embodiment.
In the display panel 20, a package layer 8, a touch layer 9, a support layer 16, a polarizer layer 11, an optical adhesive layer 12, a cover plate 13, and the like may be sequentially formed on the light emitting layer 7, and a support layer 16, a buffer layer 14, a steel sheet 15, and the like may be further formed on the side of the array substrate 10 away from the light emitting layer 7, so as to form a flexible display device with excellent buffer resistance and bending resistance.
The display device may be a mobile terminal such as a mobile phone and a tablet, or may also be a display, a television, or other equipment, and the application is not particularly limited.
In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated. The application is limited only by the claims and their full scope and equivalents.
Claims (10)
1. An array substrate, comprising:
a substrate;
the bearing insulating layers are formed on one side of the substrate in a stacked mode, a patterned device forming layer is formed on the surface, facing away from the substrate, of one side of each bearing insulating layer, the bearing insulating layers are inorganic material layers, a planarization layer is arranged on the surface, facing towards the substrate, of one side of at least one bearing insulating layer to enable the bearing insulating layers to be planarized, the surface, facing away from the substrate, of each planarization layer is a plane, and each planarization layer is an organic material layer.
2. The array substrate of claim 1, wherein two of the carrier insulating layers adjacent to each other in a direction perpendicular to the substrate include a first layer on a side close to the substrate and a second layer on a side away from the substrate, and a portion of the planarization layer is formed between the device formation layer and the second layer between the first layer and the second layer.
3. The array substrate of claim 1, wherein the planarization layer is disposed on a same layer as the device formation layer between two adjacent carrier insulating layers in a direction perpendicular to the substrate.
4. The array substrate of claim 1, wherein at least a portion of the carrier insulating layer is patterned, and further comprising a sub-planarization layer disposed in a same layer as at least a portion of the patterned carrier insulating layer, the sub-planarization layer being an organic material layer.
5. The array substrate of claim 1, wherein a plurality of planarization layers of different materials are included between two adjacent carrier insulation layers in a direction perpendicular to the substrate.
6. The array substrate of any of claims 1-5, wherein the material of the planarization layer is at least one of polyethylene terephthalate, polycarbonate, polyethylene or polyacrylate, and polyimide.
7. The array substrate of claim 1, wherein the device formation layer is used to form transistors and capacitors, and comprises a conductor layer and a semiconductor layer for forming the transistors and capacitors;
preferably, the semiconductor layer includes at least one of polysilicon and metal oxide; the conductor layer is made of metal.
8. The array substrate of claim 7, further comprising an additional planarization layer on a side of the transistors and the capacitors facing away from the substrate, the additional planarization layer covering the transistors and the capacitors.
9. A display panel comprising the array substrate according to any one of claims 1 to 8.
10. A display device characterized by comprising the display panel according to claim 9.
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