CN113964120A - Power semiconductor device and manufacturing method thereof - Google Patents
Power semiconductor device and manufacturing method thereof Download PDFInfo
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- CN113964120A CN113964120A CN202111216204.5A CN202111216204A CN113964120A CN 113964120 A CN113964120 A CN 113964120A CN 202111216204 A CN202111216204 A CN 202111216204A CN 113964120 A CN113964120 A CN 113964120A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000003989 dielectric material Substances 0.000 claims abstract description 36
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims description 41
- 238000000151 deposition Methods 0.000 claims description 36
- 238000005530 etching Methods 0.000 claims description 36
- 230000008569 process Effects 0.000 claims description 36
- 238000001259 photo etching Methods 0.000 claims description 28
- 239000003990 capacitor Substances 0.000 claims description 27
- 230000008021 deposition Effects 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 5
- 230000003213 activating effect Effects 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 4
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- 230000003647 oxidation Effects 0.000 claims description 4
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- 239000010410 layer Substances 0.000 description 78
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- 239000013065 commercial product Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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Abstract
The invention discloses a power semiconductor device and a manufacturing method thereof, the device comprises a silicon carbide N-type substrate, an N-type epitaxial layer is arranged on the silicon carbide N-type substrate, a P base region is arranged on the N-type epitaxial layer, an N + source region and a P + source region are formed in the P base region to form an intermediate device, an insulating dielectric material layer and a gate dielectric material layer are deposited on the surface of the intermediate device, polycrystalline silicon is deposited on the insulating dielectric material layer and the gate dielectric material layer, ohmic contact layers are formed on the surfaces of the N + source region and the P + source region, a Schottky contact layer is formed on the surface of the N-type epitaxial layer between the P + source region and the P + source region, source electrodes are arranged on the ohmic contact layer and the Schottky contact layer, a grid electrode is arranged on the polycrystalline silicon, and a drain electrode is arranged on the back surface of the silicon carbide N-type substrate. The invention has the advantages of reducing grid leakage charges, improving the utilization rate of a chip, reducing the loss of the anti-parallel diode, improving the surge capacity of the anti-parallel diode and the like.
Description
Technical Field
The invention mainly relates to the technical field of semiconductors, in particular to a power semiconductor device and a manufacturing method thereof.
Background
Power MOSFET devices in switching applications must overcome the gate charge to regulate the transistor to a particular voltage, and the switching speed of the transistor decreases significantly at higher gate charges. In addition, transistors suffer from higher gate charge and failure rates increase. The gate-drain charge is the dominant part of the gate charge, and applying a switching voltage to the gate amplifies the gate-drain capacitance due to the miller effect. It is therefore desirable to minimize gate-drain capacitance to reduce gate charge and improve switching speed, efficiency and failure rate of the transistor.
In power electronic systems, power MOSFET devices are often used with Free Wheeling Diodes (FWDs) to ensure the safety and stability of the system. Therefore, in a traditional power MOSFET module or a single-tube device, the FWD is usually connected in parallel with the FWD in an inverse manner, and this scheme not only increases the number of devices, the volume of the module, and the production cost, but also increases the number of solder points during the packaging process, which affects the reliability of the device, and the parasitic effect generated by the metal connection also affects the overall performance of the device.
The device cell structure adopted by the commercial product of the silicon carbide planar gate MOSFET is shown in figure 1. The low channel mobility is a key factor of large on-resistance of a silicon carbide planar gate MOSFET, meanwhile, the silicon carbide can only adopt ion implantation, an N + source region and a P-type well PW of the planar gate MOSFET adopt a two-layer photoetching plate registration mode, and due to easy misalignment, the registration deviation can cause the channel lengths (shown as 31 and 32 in figure 1) of two half-cells to be asymmetric, so that the on-current of the device selects a shorter channel to flow to a drain electrode, and then the half-cell of a longer channel is not utilized.
In summary, the existing power MOSFET device has the defects of large gate-drain charge, low utilization rate of silicon carbide chips, large loss of freewheeling diodes, and the like.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides the power semiconductor device and the manufacturing method thereof, wherein the power semiconductor device can reduce grid leakage charges, improve the utilization rate of a chip, reduce the loss of an anti-parallel diode and improve the surge capacity of the anti-parallel diode.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
a power semiconductor device comprises a silicon carbide N-type substrate, wherein an N-type epitaxial layer is arranged on the silicon carbide N-type substrate, a P base region is arranged on the N-type epitaxial layer, an N + source region and a P + source region are formed in the P base region to form an intermediate device, an insulating dielectric material layer and a gate dielectric material layer are deposited on the surface of the intermediate device, polycrystalline silicon is deposited on the insulating dielectric material layer and the gate dielectric material layer, ohmic contact layers are formed on the surfaces of the N + source region and the P + source region, a Schottky contact layer is formed on the surface of the N-type epitaxial layer between the P + source region and the P + source region, source electrodes are arranged on the ohmic contact layer and the Schottky contact layer, a grid electrode is arranged on the polycrystalline silicon, and a drain electrode is arranged on the back surface of the silicon carbide N-type substrate.
As a further improvement of the above technical solution:
the N-type epitaxial layer, a part of the P base region, the ohmic contact layer and the Schottky contact layer form JBS or MPS.
And the partial P base region, the P + source region, the insulating medium material layer and the polysilicon form a P-type MOS capacitor.
And the silicon carbide N-type substrate, the N-type epitaxial layer, the gate dielectric material layer and the polysilicon form an N-type MOS capacitor.
And the P-type MOS capacitor and the N-type MOS capacitor are connected in series.
The area of the polysilicon may vary.
The invention also discloses a manufacturing method of the power semiconductor device, which comprises the following steps:
step 1: forming an N-type epitaxial layer on a silicon carbide N-type substrate by adopting an epitaxial process;
step 2: forming a P base region above the N-type epitaxial layer by adopting photoetching and ion implantation processes, forming an N + source region and a P + source region in the P base region, and activating impurities in the implantation region by high-temperature annealing;
and 3, step 3: depositing an insulating medium material layer on the surface of the device by adopting deposition, photoetching and etching processes, and etching to remove the redundant insulating medium material layer;
and 4, step 4: generating a gate dielectric material layer on the surface of the device by adopting a thermal oxidation process;
and 5, step 5: depositing a layer of polycrystalline silicon on the surface of the device by adopting deposition, photoetching and etching processes, and etching to remove redundant polycrystalline silicon material;
and 6, step 6: depositing a layer of insulating medium material on the surface of the device by adopting deposition, photoetching and etching processes, and etching to remove redundant edge medium material;
and 7, step 7: forming an ohmic contact layer on the surface of the device by adopting deposition, alloy, photoetching and etching processes;
and 8, step 8: forming a Schottky contact layer on the surface of the device by adopting deposition, alloy, photoetching and etching processes;
step 9: respectively forming a source electrode and a grid electrode by adopting deposition, photoetching and etching processes;
step 10: and forming a drain electrode on the back of the device by adopting laser annealing, metal thickening and deposition processes, and finally obtaining the silicon carbide MOSFET device.
As a further improvement of the above technical solution:
in the step 1, the doping concentration of the N-type epitaxial layer is 5e 14-5 e16cm-3。
In the step 2, the junction depth of the P base region is 0.6-1.5 um, and the peak doping concentration is 1e 18-5 e19cm-3。
In the step 3, the thickness of the insulating medium material layer is 0.05-2 μm.
Compared with the prior art, the invention has the advantages that:
in the power MOSFET structure, MPS is integrated by using half of MOSFET cells, so that the utilization rate of a chip is improved, the loss of an external anti-parallel diode and the device volume are reduced, the bipolar degradation effect of a parasitic body diode of the MOSFET is avoided, the turn-on loss of a Pin diode is avoided on the premise of ensuring the same level of voltage resistance of the body diode and the MOSFET, and the surge capacity of the anti-parallel diode is also improved; according to the C-V curve theory, when the grid source voltage of the MOSFET is close to the platform voltage, the depletion region of the N-type semiconductor drift region of the NMOS capacitor is reduced, the capacitance of the N-type semiconductor drift region of the NMOS capacitor is increased, the depletion region of the P-type region of the PMOS capacitor is expanded, the capacitance of the N-type semiconductor drift region of the NMOS capacitor is reduced, the two capacitors are connected in series, and the total capacitance depends on the smaller capacitor, so that the grid leakage charge is reduced; meanwhile, the insulating dielectric material layer of the PMOS capacitor is thicker than the gate dielectric material layer of the NMOS gate-drain capacitor, and the gate-drain charge is further reduced.
The invention has the following 3 advantages by improving the structure design of the power MOSFET device: 1. reducing gate leakage charge; 2. the utilization rate of the chip is improved; 3. the integrated mixed PiN Schottky diode reduces the loss of the anti-parallel diode, improves the surge capacity of the anti-parallel diode and enhances the robustness of the anti-parallel diode.
Drawings
Fig. 1 is a schematic cross-sectional view of a conventional power MOSFET device.
Fig. 2 is a schematic cross-sectional view of a power MOSFET device according to a first embodiment of the invention.
Fig. 3 is a schematic cross-sectional view of a MOSFET device according to an embodiment of the present invention after step 2.
Fig. 4 is a schematic cross-sectional view of a power MOSFET device after step 3 according to a first embodiment of the invention.
Fig. 5 is a schematic cross-sectional view of a power MOSFET device after step 5 according to a first embodiment of the invention.
Fig. 6 is a schematic cross-sectional view of a power MOSFET device after step 7 according to a first embodiment of the invention.
Fig. 7 is a schematic cross-sectional view of a power MOSFET device after step 8 according to a first embodiment of the invention.
Fig. 8 is a schematic cross-sectional view of a power MOSFET device according to a second embodiment of the invention.
Illustration of the drawings: 1. an N-type substrate; 2. an N-type epitaxial layer; 3. a P base region; 4. an N + source region; 5. a P + source region; 6. a layer of insulating dielectric material; 7. a gate dielectric material layer; 8. polycrystalline silicon; 9. an interlayer dielectric layer; 10. an ohmic contact layer; 11. a Schottky gold contact layer; 12. a source electrode; 13. a gate electrode; 14. a drain electrode; 100. MPS; 101. a PMOS capacitor; 102. and a gate-drain capacitance.
Detailed Description
The invention is further described below with reference to the figures and the specific embodiments of the description.
As shown in fig. 2, the power semiconductor device of this embodiment includes a silicon carbide N-type substrate 1, an N-type epitaxial layer 2 is disposed on the silicon carbide N-type substrate 1, a P-type base region 3 is disposed on the N-type epitaxial layer 2, specifically, three positions, i.e., a left, a middle and a right, are formed in the P-type base region 3, and an N + source region 4 and a P + source region 5 are formed in the P-type base region 3 (wherein the N + source region 4 and the P + source region 5 are formed in the P-type base regions 3 on both sides, and the P + source region 5 is formed in the P-type base region 3 in the middle), so as to form an intermediate device; an insulating dielectric material layer 6 and a gate dielectric material layer 7 are deposited on the surface of the middle device (wherein the insulating dielectric layer 6 is positioned at the left and right positions, the left position is positioned in the region where the middle P base region 3 does not form the P + source region 5, the gate dielectric material layer 7 is positioned at the left and right positions, the left position is positioned on the left P base region 3, the corresponding N + source region 4 and the N type epitaxial layer 2, the right position is positioned on the right P base region 3, the corresponding N + source region 4 and the N type epitaxial layer 2), polycrystalline silicon 8 (with variable areas) is deposited on the insulating dielectric material layer 6 and the gate dielectric material layer 7, ohmic contact layers 10 are formed between the N + source region 4 and the P + source region 5 (specifically three positions, one position on the left side is positioned on the N + source region 4 and the P + source region 5 of the left P base region 3, one position is positioned on the P + source region 5 of the middle P base region 3, and one position on the N + source region 4 and the P + source region 5 of the right P base region 3), a schottky contact layer 11 (located between the middle ohmic contact layer 10 and the right ohmic contact layer 10) is formed between the P + source region 5 and the P + source region 5, source electrodes 12 (specifically, two positions, as shown in fig. 2) are arranged on the ohmic contact layer 10 and the schottky contact layer 11, a gate electrode 13 is arranged on the polysilicon 8, and a drain electrode 14 is arranged on the back surface of the silicon carbide N-type substrate 1.
In the power MOSFET structure, half of the MOSFET cells are integrated with MPS100 (which is composed of a regional silicon carbide N-type substrate 1, an N-type epitaxial layer 2, a P base region 3, a P + source region 5, an ohmic contact layer 10, a Schottky contact layer 11, a source electrode 12 and a drain electrode 14), so that the chip utilization rate is improved, the loss of an external anti-parallel diode and the device volume are reduced, the bipolar degradation effect of a parasitic body diode of the MOSFET is avoided, the turn-on loss of a Pin diode is avoided on the premise of ensuring that the body diode and the MOSFET have the same level of voltage resistance, and the surge capacity of the anti-parallel diode is also improved; wherein, a PMOS capacitor 101 (composed of a region P base region 3, a P + source region 5, an insulating medium material layer 6, a polysilicon 8, an ohmic contact layer 10 and a source electrode 12) is formed by utilizing a part of the integrated MPS and is connected in series with an NMOS gate-drain capacitor 102 (composed of a region silicon carbide N-type substrate 1, an N-type epitaxial layer 2, a gate medium material layer 7, a polysilicon 8 and a drain electrode 14) of the MOSFET through a metal 13, as can be known from C-V curve theory, when the gate-source voltage of the MOSFET is close to a platform voltage, the depletion region of an N-type semiconductor drift region of the NMOS capacitor is reduced, the capacitance thereof is increased, while the depletion region of a P-type region of the PMOS capacitor is expanded, the capacitance thereof is reduced, two capacitors (the PMOS capacitor and the NMOS capacitor) are connected in series, the total capacitance depends on the smaller capacitance, thereby reducing the gate-drain charge, and simultaneously, the insulating medium material layer 6 of the PMOS capacitor is thicker than the gate medium material layer 7 of the NMOS gate-drain capacitor, the gate leakage charge is further reduced.
The invention also discloses a manufacturing method of the power semiconductor device, which comprises the following steps:
step 1: forming an N-type epitaxial layer 2 on a silicon carbide N-type substrate 1 by adopting an epitaxial process;
step 2: forming a P base region 3 above the N type epitaxial layer 2 by adopting photoetching and ion implantation processes, forming an N + source region 4 and a P + source region 5 in the P base region 3, and activating impurities in the implantation region by high-temperature annealing;
and 3, step 3: depositing an insulating dielectric material layer 6 on the surface of the device by adopting deposition, photoetching and etching processes, and etching to remove the redundant insulating dielectric material layer;
and 4, step 4: generating a gate dielectric material layer 7 on the surface of the device by adopting a thermal oxidation process;
and 5, step 5: depositing a layer of polycrystalline silicon 8 on the surface of the device by adopting deposition, photoetching and etching processes, and etching to remove redundant polycrystalline silicon material;
and 6, step 6: depositing an interlayer dielectric layer 9 (insulating dielectric material) on the surface of the device by adopting deposition, photoetching and etching processes, and etching to remove the redundant insulating dielectric material;
and 7, step 7: forming an ohmic contact layer 10 on the surface of the device by adopting deposition, alloying, photoetching and etching processes;
and 8, step 8: forming a Schottky contact layer 11 on the surface of the device by adopting deposition, alloy, photoetching and etching processes;
step 9: respectively forming a source electrode 12 and a grid electrode 13 by deposition, photoetching and etching processes;
step 10: and forming a drain electrode 14 on the back surface of the device by adopting laser annealing, metal thickening and deposition processes, and finally obtaining the silicon carbide MOSFET device.
The invention has the following 3 advantages through the improvement of the structure design of the power MOSFET device, 1, the grid leakage charge is reduced; 2. the utilization rate of the chip is improved; 3. the integrated mixed Pin Schottky diode (MPS) reduces the loss of the anti-parallel diode and improves the surge capacity of the anti-parallel diode.
The invention is further illustrated below with reference to two specific embodiments:
the first embodiment is as follows:
step 1: an epitaxial process is adopted to form an N-type epitaxial layer 2 on a silicon carbide N-type substrate 1, wherein the resistivity of the N-type substrate 1 is 0.01-0.03 omega-cm, the thickness is 200-400 mu m, and the doping concentration of the N-type epitaxial layer 2 is 5e 14-5 e16cm-3；
Step 2: forming a P base region 3 above the N type epitaxial layer 2 by adopting photoetching and ion implantation processes, wherein the junction depth of the P base region 3 is 0.6-1.5 um, and the peak doping concentration is 1e 18-5 e19cm-3Forming an N + source region 4 with a junction depth of 0.2-0.5 um and a peak doping concentration of 5e 18-5 e20cm in the P base region 3-3Forming a P + source region 5 with a junction depth of 0.2-0.5 um and a doping concentration of 5e 18-5 e20cm in the P base region 3-3And activating the impurity of the implantation region by high temperature annealing, as shown in fig. 3;
and 3, step 3: depositing a layer of insulating dielectric material 6 with the thickness of 0.05-2 mu m on the surface of the device by adopting deposition, photoetching and etching processes, and etching to remove the redundant dielectric material 6, as shown in figure 4;
and 4, step 4: generating a layer of gate dielectric material 7 on the surface of the device by adopting a thermal oxidation process;
and 5, step 5: depositing a layer of polysilicon 8 on the surface of the device by deposition, photoetching and etching processes, and etching to remove redundant polysilicon material, as shown in FIG. 5;
and 6, step 6: depositing an interlayer dielectric layer 9 (such as an insulating dielectric material) on the surface of the device by adopting deposition, photoetching and etching processes, and etching to remove redundant edge dielectric materials;
and 7, step 7: forming an ohmic contact 10 on the surface of the device by deposition, alloying, photolithography and etching processes, as shown in fig. 6;
and 8, step 8: forming a schottky contact 11 on the surface of the device by deposition, alloying, photoetching and etching processes, as shown in fig. 7;
step 9: respectively forming a source electrode 12 and a grid electrode 13 by adopting deposition, photoetching and etching processes, and displaying grid electrode metal for clarity;
step 10: and laser annealing, metal thickening and deposition processes are adopted to form the drain electrode 14 on the back surface of the device and the protective adhesive on the front surface, and finally the silicon carbide MOSFET device is prepared, as shown in figure 2.
Where dimensions in the figures (including lateral dimensions, layout dimensions, dielectric thickness, metal thickness, junction depth, etc.) do not represent actual dimensions, but are merely examples of methods for forming structures where devices include, but are not limited to, planar MOSFETs, planar IGBTs, MPS, JBS; semiconductor materials include, but are not limited to, SiC, such as Si, and the like.
Example two:
the MPS is integrated with the MOSFET half-cells as in the first embodiment (dashed box 200 in fig. 8); the difference from the first embodiment is that the gate charge is reduced by reducing the size of the working gate by removing a piece of polysilicon 8 (no polysilicon 8 is in the dashed box 201 in fig. 8), while the MPS portion does not form a PMOS capacitor, as shown in fig. 8.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may be made by those skilled in the art without departing from the principle of the invention.
Claims (10)
1. A power semiconductor device is characterized by comprising a silicon carbide N-type substrate (1), wherein an N-type epitaxial layer (2) is arranged on the silicon carbide N-type substrate (1), a P base region (3) is arranged on the N-type epitaxial layer (2), an N + source region (4) and a P + source region (5) are formed in the P base region (3) to form an intermediate device, an insulating medium material layer (6) and a gate medium material layer (7) are deposited on the surface of the intermediate device, polycrystalline silicon (8) is deposited on the insulating medium material layer (6) and the gate medium material layer (7), ohmic contact layers (10) are formed on the surfaces of the N + source region (4) and the P + source region (5), a Schottky contact layer (11) is formed on the surface of the N-type epitaxial layer between the P + source region (5) and the P + source region (5), and source electrodes (12) are arranged on the ohmic contact layers (10) and the Schottky contact layers (11), a grid (13) is arranged on the polycrystalline silicon (8), and a drain (14) is arranged on the back of the silicon carbide N-type substrate (1).
2. The power semiconductor device according to claim 1, wherein the N-type epitaxial layer (2), the partial P-base region (3), the ohmic contact layer (10), and the schottky contact layer (11) form a JBS or MPS.
3. The power semiconductor device according to claim 1, characterized in that part of the P base region (3), the P + source region (5), the insulating dielectric material layer (6) and the polysilicon (8) form a P-type MOS capacitor.
4. The power semiconductor device according to claim 1, wherein the silicon carbide N-type substrate (1), the N-type epitaxial layer (2), the gate dielectric material layer (7) and the polysilicon (8) form an N-type MOS capacitor.
5. Power semiconductor device according to claims 3 and 4, characterized in that the P-type MOS capacitor and the N-type MOS capacitor are connected in series.
6. Power semiconductor device according to claim 1, characterized in that the area of the polysilicon (8) is variable.
7. A method for manufacturing a power semiconductor device according to any one of claims 1 to 6, comprising the steps of:
step 1: forming an N-type epitaxial layer (2) on a silicon carbide N-type substrate (1) by adopting an epitaxial process;
step 2: forming a P base region (3) above the N type epitaxial layer (2) by adopting photoetching and ion implantation processes, forming an N + source region (4) and a P + source region (5) in the P base region (3), and activating impurities in the implantation region by high-temperature annealing;
and 3, step 3: depositing an insulating dielectric material layer (6) on the surface of the device by adopting deposition, photoetching and etching processes, and etching to remove the redundant insulating dielectric material layer;
and 4, step 4: generating a gate dielectric material layer (7) on the surface of the device by adopting a thermal oxidation process;
and 5, step 5: depositing a layer of polysilicon (8) on the surface of the device by adopting deposition, photoetching and etching processes, and etching to remove redundant polysilicon material;
and 6, step 6: depositing a layer of insulating dielectric material (9) on the surface of the device by adopting deposition, photoetching and etching processes, and etching to remove redundant edge dielectric material;
and 7, step 7: forming an ohmic contact layer (10) on the surface of the device by adopting deposition, alloy, photoetching and etching processes;
and 8, step 8: forming a Schottky contact layer (11) on the surface of the device by adopting deposition, alloy, photoetching and etching processes;
step 9: respectively forming a source electrode (12) and a grid electrode (13) by adopting deposition, photoetching and etching processes;
step 10: and forming a drain electrode (14) on the back surface of the device by adopting laser annealing, metal thickening and deposition processes, and finally obtaining the silicon carbide MOSFET device.
8. The method for manufacturing the power semiconductor device according to claim 7, wherein in the step 1, the doping concentration of the N-type epitaxial layer (2) is 5e 14-5 e16cm-3。
9. The method for manufacturing a power semiconductor device according to claim 8, wherein in the step 2, the junction depth of the P base region (3) is 0.6-1.5 um, and the peak doping concentration is 1e 18-5 e19cm-3。
10. The method for manufacturing a power semiconductor device according to claim 7, wherein in the step 3, the thickness of the insulating medium material layer (6) is 0.05-2 μm.
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