CN113964049A - Connecting method and connecting structure of chip and lining plate and electronic device - Google Patents

Connecting method and connecting structure of chip and lining plate and electronic device Download PDF

Info

Publication number
CN113964049A
CN113964049A CN202111116610.4A CN202111116610A CN113964049A CN 113964049 A CN113964049 A CN 113964049A CN 202111116610 A CN202111116610 A CN 202111116610A CN 113964049 A CN113964049 A CN 113964049A
Authority
CN
China
Prior art keywords
chip
metal layer
layer
lining plate
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111116610.4A
Other languages
Chinese (zh)
Inventor
刘亮
戴小平
柯攀
曾亮
黄蕾
杜隆纯
刘洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hunan Guoxin Semiconductor Technology Co ltd
Original Assignee
Hunan Guoxin Semiconductor Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hunan Guoxin Semiconductor Technology Co ltd filed Critical Hunan Guoxin Semiconductor Technology Co ltd
Priority to CN202111116610.4A priority Critical patent/CN113964049A/en
Publication of CN113964049A publication Critical patent/CN113964049A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/271—Manufacture and pre-treatment of the layer connector preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83053—Bonding environment

Abstract

The invention discloses a method for connecting a chip and a lining plate, a connecting structure and an electronic device, wherein the connecting method comprises the following steps: 1) depositing a first metal layer on the chip; depositing a second metal layer on the lining plate; the melting point difference between the first metal layer and the second metal layer is within a preset range; 2) the chip is placed on the lining plate, the first metal layer is in contact with the second metal layer, preset pressure is applied between the chip and the lining plate, then sintering is carried out, solid-liquid mutual diffusion is carried out on the first metal layer and the second metal layer, intermetallic compounds are generated, and therefore connection between the chip and the lining plate is achieved. The invention has the advantages of simple process, low-temperature connection, high-temperature service, high environmental friendliness and the like.

Description

Connecting method and connecting structure of chip and lining plate and electronic device
Technical Field
The invention mainly relates to the technical field of chip packaging, in particular to a method and a structure for connecting a chip and a lining plate and an electronic device.
Background
In a typical electronic device, the package connection of the chip is completed by using reflow soldering or silver-pressed sintering. In the reflow soldering process using lead-tin solder, due to the harmfulness of lead to the environment and human body, more and more national legislations limit the use of lead, so that the lead-tin solder slowly exits the power module packaging field. And the other one uses a wider tin-silver-copper-silver material, and the thickness of the intermetallic compound is increased due to the overhigh reflow temperature and overlong reflow time, so that the long-term reliability of the welding spot is influenced. In addition, reflow soldering is a connection mode of high-temperature connection and low-temperature service, for example, for a power module, the use temperature of the reflow soldering is generally 50-70 ℃ lower than the melting point of solder, which also limits the operating junction temperature of the power module; another connection mode that is being studied more and more is silver-pressed sintering. The silver pressing sintering is a connection mode of low-temperature connection and high-temperature service, the connection temperature is about 250 ℃, the theoretical use temperature can reach 700 ℃, compared with the conventional reflow solder, the silver sintering material has higher melting point, thermal conductivity and electric conductivity, but the realization of the silver pressing sintering needs to apply 15-20MPa of pressure on the surface of a chip, the chip is easily damaged due to the overhigh pressure, and expensive special equipment is needed to realize the silver pressing sintering, so the use range of the silver pressing sintering is limited.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the problems in the prior art, the invention provides a method for connecting a chip and a lining plate, a connecting structure and an electronic device, wherein the method is simple in process, low-temperature in connection, high-temperature in service and high in environmental friendliness.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
a method for connecting a chip and a lining plate comprises the following steps:
1) depositing a first metal layer on the chip; depositing a second metal layer on the lining plate; the melting point difference between the first metal layer and the second metal layer is within a preset range;
2) the chip is placed on the lining plate, the first metal layer is in contact with the second metal layer, preset pressure is applied between the chip and the lining plate, then sintering is carried out, solid-liquid mutual diffusion is carried out on the first metal layer and the second metal layer, intermetallic compounds are generated, and therefore connection between the chip and the lining plate is achieved.
As a further improvement of the above technical solution:
in step 1), a metal layer with a higher melting point is deposited on a metal layer with a lower melting point as a protective layer.
The first metal layer is an In layer, and the second metal layer is an Ag layer; or the first metal layer is an Ag layer, and the second metal layer is an In layer.
In step 1), the thickness ratio of the metal layer with the lower melting point to the metal layer with the higher melting point is 0.2-0.9.
In step 2), the preset pressure is applied at 0.15-0.5 MPa.
In step 2), the corresponding sintering process comprises: the temperature is increased to 130-150 ℃ in the first stage for 50-150S, and the temperature is kept for 5-10 min; the temperature of the second section is set to 150-250S and then raised to 220-280 ℃, so as to ensure that the temperature of the metal layer with lower melting point is between 200 ℃ and 250 ℃; keeping the temperature constant for 10-30 min; and releasing the pressure between the chip and the lining plate after the heat preservation is finished, and then quickly cooling to finish the connection.
The invention also discloses a connecting structure of the chip and the lining plate, which comprises an intermetallic compound for connecting the chip and the lining plate, wherein the intermetallic compound is obtained by mutually diffusing solid and liquid through two metal layers with different melting points.
The invention further discloses an electronic device which comprises a chip and a lining plate, and further comprises the connecting structure of the chip and the lining plate, wherein the chip and the lining plate are connected through the connecting structure.
As a further improvement of the above technical solution:
the lining plate comprises an upper copper layer, a ceramic layer and a lower copper layer which are sequentially arranged.
Compared with the prior art, the invention has the advantages that:
the invention deposits a low melting point metal layer and a high melting point metal layer on the surfaces of a chip and a lining plate (DBC, AMB, PCB and the like), and then applies micro pressure to the chip and the lining plate at a temperature higher than the melting point of the low melting point metal layer to enable the two liquid metal layers to generate solid-liquid mutual diffusion and generate an intermetallic compound with a high melting point, thereby finally realizing the connection of the chip and the lining plate, and having the following advantages: respectively depositing a first metal layer and a second metal layer required by connection on the surfaces of the chip and the lining plate without printing a connecting material by using a screen printer; the connection method can use a solid-liquid interdiffusion connection method, so that low-temperature connection and high-temperature service are realized; compared with silver pressing sintering, the pressure applied in the connection process is small, the chip is not easy to damage, and the connection can be realized by a common temperature press because the applied pressure is small, so that expensive silver sintering equipment does not need to be purchased; compared with the conventional reflow soldering edge connection mode, the connection mode can realize low-temperature connection and high-temperature service; compared with the lead reflow soldering, the environmental friendliness is improved.
Drawings
Fig. 1 is a schematic structural view of an electronic device of the present invention in first and second embodiments.
Fig. 2 is a schematic structural diagram of an electronic device according to a third embodiment of the present invention.
Illustration of the drawings: 1. a chip; 2. a first metal layer; 3. a protective layer; 4. a second metal layer; 5. a liner plate; 501. coating a copper layer; 502. a ceramic layer; 503. and (7) a lower copper layer.
Detailed Description
The invention is further described below with reference to the figures and the specific embodiments of the description.
The method for connecting the chip and the lining board is suitable for connecting the power chip 1 such as a power IGBT, a MOSFET and the like with the lining board 5, and specifically comprises the following steps:
1) depositing a first metal layer 2 on the chip 1; depositing a second metal layer 4 on the liner plate 5; the melting point difference between the first metal layer 2 and the second metal layer 4 is within a predetermined range, such as 600-;
2) the chip 1 is placed on the lining plate 5, the first metal layer 2 is in contact with the second metal layer 4, preset pressure is applied between the chip 1 and the lining plate 5, then sintering is carried out, solid-liquid mutual diffusion occurs between the first metal layer 2 and the second metal layer 4, intermetallic compounds are generated, and therefore connection between the chip 1 and the lining plate 5 is achieved.
The invention deposits a low melting point metal layer and a high melting point metal layer on the surfaces (DBC, AMB, PCB, etc.) of the chip 1 and the lining board 5 respectively, then the chip 1 and the lining board 5 are applied with micro pressure at the temperature higher than the melting point of the low melting point metal layer to enable the two metals to generate solid-liquid mutual diffusion (the low melting point metal is melted into liquid, and the high melting point metal is still solid, so the solid-liquid mutual diffusion is generated between the two metals) and generate the intermetallic compound with high melting point, and finally the connection of the chip 1 and the lining board 5 is realized, and the invention has the following advantages:
respectively depositing a first metal layer 2 and a second metal layer 4 required by connection on the surfaces of a chip 1 and a lining plate 5 without printing a connecting material by using a screen printer;
the connection method adopts a solid-liquid interdiffusion connection method, so that low-temperature connection and high-temperature service are realized;
compared with silver pressing sintering, the pressure applied in the connection process is small, the chip 1 is not easy to damage, and the connection can be realized by a common temperature press because the applied pressure is small, so that expensive silver sintering equipment does not need to be purchased; compared with the conventional reflow soldering edge connection mode, the connection mode can realize low-temperature connection and high-temperature service; compared with the lead reflow soldering, the environmental friendliness is improved.
In one embodiment, the two metal layers are an In layer and an Ag layer, wherein In is a low melting point metal, Ag is a high melting point metal, In has a melting point of 156 ℃ and Ag has a melting point of 961 ℃, and the two metal layers form an intermetallic compoundCompound Ag9In4And Ag3The In melting point is above 600 ℃.
In one embodiment, one of the deposition methods is to deposit an In layer on the chip 1, deposit a very thin protective Ag layer 3 (where the In layer is susceptible to oxidation and thus the protective Ag layer 3 is deposited to prevent oxidation of the In layer) on top of the In layer, and deposit an Ag layer on the upper copper layer 501 of the backing plate 5. Another way of deposition is to deposit an Ag layer on the chip 1, an In layer on the upper copper layer 501 of the liner 5, and a very thin Ag protective layer 3 on the outside of the In layer.
In a specific embodiment, the thickness ratio of In/Ag deposited on the chip 1 and the lining plate 5 is 0.2-0.9, the chip 1 is placed on the lining plate 5 and then placed into a sintering furnace, the temperature is controlled at 250 ℃ and the pressure is controlled at 0.15-0.5MPa, the time is controlled at 10-30min, and the process is cooled to room temperature after the completion.
The invention also discloses a connecting structure of the chip and the lining plate, which comprises an intermetallic compound for connecting the chip 1 and the lining plate 5, wherein the intermetallic compound is obtained by sintering two metal layers with different melting points, and particularly is obtained by the connecting method. The connection structure of the present invention also has the advantages as described in the above method.
The invention further discloses an electronic device which comprises a chip 1 and a lining plate 5 and further comprises the connecting structure of the chip 1 and the lining plate 5, and the chip 1 is connected with the lining plate 5 through the connecting structure. Wherein the backing plate 5 comprises an upper copper layer 501, a ceramic layer 502 and a lower copper layer 503 arranged in sequence, and a corresponding metal layer is deposited on the upper copper layer 501. The electronic device of the present invention also has the advantages as described above for the connection structure.
The invention is further illustrated in detail by the following three complete specific examples:
the first embodiment is as follows:
as shown In fig. 1, an In layer with a thickness of 2um is deposited on the chip 1, the Ag protection layer 3 has a thickness of 0.05um, and an Ag layer with a thickness of 10um is deposited on the upper copper layer 501 of the lining board 5, so as to ensure that the thickness ratio of In/Ag is 0.2; placing the chip 1 on the lining plate 5 to enable the Ag protective layer 3 to be in contact with the Ag layer; placing the chip 1 and the lining plate 5 on a press, and applying pressure of 0.15-0.5MPa on the surface of the chip 1 by a pressure head of the press; setting 100S in the first section of the temperature of the press, heating to 130-150 ℃, and keeping the temperature for 5-10 min; the temperature of the second section of the press is set to 200S and raised to 220-280 ℃, so that the temperature of the In layer on the chip 1 is ensured to be between 200 ℃ and 250 ℃; keeping the temperature constant for 10-30 min; and after the heat preservation is finished, the pressure head is lifted, the product is taken down and then is rapidly cooled, and the connection is finished.
Example two:
as shown In fig. 1, an In layer with a thickness of 5.5um is deposited on the chip 11, the Ag protection layer 3 has a thickness of 0.05um, and an Ag layer with a thickness of 10um is deposited on the copper layer 501 on the lining board 5, so as to ensure that the thickness ratio of In/Ag is 0.55; placing the chip 11 on the lining plate 5 to make the Ag protective layer 3 contact with the Ag layer; placing the chip 1 and the lining plate 5 on a press, and applying pressure of 0.15-0.5MPa on the surface of the chip 1 by a pressure head of the press; setting 100S in the first section of the temperature of the press, heating to 130-150 ℃, and keeping the temperature for 5-10 min; the temperature of the second section of the press is set to 200S and raised to 220-280 ℃, so that the temperature of the In layer on the chip 1 is ensured to be between 200 ℃ and 250 ℃; keeping the temperature constant for 10-30 min; and after the heat preservation is finished, the pressure head is lifted, the product is taken down and then is rapidly cooled, and the connection is finished.
Example three:
as shown In fig. 2, an Ag layer with a thickness of 10um is deposited on the chip 1, an In layer with a thickness of 9um is deposited on the upper copper layer 501 of the lining board 5, and the thickness of the Ag protection layer 3 is 0.05um, so as to ensure that the thickness ratio of In/Ag is 0.9; placing the chip 1 on the lining plate 5 to enable the Ag protective layer 3 to be in contact with the Ag layer; placing the chip 1 and the lining plate 5 on a press, and applying pressure of 0.15-0.5MPa on the surface of the chip 1 by a pressure head of the press; setting 100S in the first section of the temperature of the press, heating to 130-150 ℃, and keeping the temperature for 5-10 min; the temperature of the second section of the press is set to 200S and raised to 220-280 ℃, so that the temperature of the In layer on the chip 1 is ensured to be between 200 ℃ and 250 ℃; keeping the temperature constant for 10-30 min; and after the heat preservation is finished, the pressure head is lifted, the product is taken down and then is rapidly cooled, and the connection is finished.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may be made by those skilled in the art without departing from the principle of the invention.

Claims (9)

1. A method for connecting a chip and a lining plate is characterized by comprising the following steps:
1) depositing a first metal layer (2) on the chip (1); depositing a second metal layer (4) on the liner plate (5); the melting point difference between the first metal layer (2) and the second metal layer (4) is within a preset range;
2) the chip (1) is placed on the lining plate (5), the first metal layer (2) is in contact with the second metal layer (4), preset pressure is applied between the chip (1) and the lining plate (5), then sintering is carried out, solid-liquid mutual diffusion occurs between the first metal layer (2) and the second metal layer (4), intermetallic compounds are generated, and therefore connection between the chip (1) and the lining plate (5) is achieved.
2. The method for connecting a chip to a substrate according to claim 1, wherein in step 1), a metal layer with a higher melting point is deposited on the metal layer with a lower melting point as the protective layer (3).
3. The method of connecting a chip to a substrate according to claim 1 or 2, wherein the first metal layer (2) is an In layer and the second metal layer (4) is an Ag layer; or the first metal layer (2) is an Ag layer, and the second metal layer (4) is an In layer.
4. The method for connecting a chip and a board according to claim 1 or 2, wherein in step 1), the thickness ratio of the metal layer corresponding to the lower melting point to the metal layer corresponding to the higher melting point is 0.2 to 0.9.
5. The method for connecting a chip and a backing plate according to claim 1 or 2, wherein the predetermined pressure applied in step 2) is 0.15 to 0.5 Mpa.
6. The method for connecting a chip and a liner plate according to claim 1 or 2, wherein in step 2), the corresponding sintering process comprises:
the temperature is increased to 130-150 ℃ in the first stage for 50-150S, and the temperature is kept for 5-10 min; the temperature of the second section is set to 150-250S and then raised to 220-280 ℃, so as to ensure that the temperature of the metal layer with lower melting point is between 200 ℃ and 250 ℃; keeping the temperature constant for 10-30 min; and releasing the pressure between the chip (1) and the lining plate (5) after the heat preservation is finished, and then rapidly cooling to finish the connection.
7. A connecting structure of a chip and a lining plate is characterized by comprising an intermetallic compound for connecting the chip (1) and the lining plate (5), wherein the intermetallic compound is obtained by solid-liquid mutual diffusion of two metal layers with different melting points.
8. An electronic device comprising a chip and a substrate, characterized in that it further comprises a connection structure of the chip (1) and the substrate (5) according to claim 7, wherein the chip (1) and the substrate (5) are connected by the connection structure.
9. Electronic device according to claim 8, characterized in that the backing plate (5) comprises an upper copper layer (501), a ceramic layer (502) and a lower copper layer (503) arranged in sequence.
CN202111116610.4A 2021-09-23 2021-09-23 Connecting method and connecting structure of chip and lining plate and electronic device Pending CN113964049A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111116610.4A CN113964049A (en) 2021-09-23 2021-09-23 Connecting method and connecting structure of chip and lining plate and electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111116610.4A CN113964049A (en) 2021-09-23 2021-09-23 Connecting method and connecting structure of chip and lining plate and electronic device

Publications (1)

Publication Number Publication Date
CN113964049A true CN113964049A (en) 2022-01-21

Family

ID=79462410

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111116610.4A Pending CN113964049A (en) 2021-09-23 2021-09-23 Connecting method and connecting structure of chip and lining plate and electronic device

Country Status (1)

Country Link
CN (1) CN113964049A (en)

Similar Documents

Publication Publication Date Title
US6084775A (en) Heatsink and package structures with fusible release layer
KR20130129965A (en) Sintering materials and attachment methods using same
CN105479026A (en) Method for improving connecting strength of nano sliver paste and chemical nickel-plated gold substrate
US7874475B2 (en) Method for the planar joining of components of semiconductor devices and a diffusion joining structure
JP2011216772A (en) Method of manufacturing semiconductor device, and bonding jig
CN113206018B (en) Low-temperature large-area uniform sintering method for nano-silver soldering paste
CN102610537B (en) Method for low-temperature solid bonding of semiconductor device
US20230361071A1 (en) Electronics assemblies employing copper in multiple locations
JP2007044754A (en) Metal plate joining method
CN109175568B (en) Brazing method for large-area grounding of large-size antenna and microstrip plate
CN113964049A (en) Connecting method and connecting structure of chip and lining plate and electronic device
CN109411372B (en) Method for uniformly current-assisted sintering of nano-silver solder paste temperature field based on copper-clad ceramic substrate
CN110744163B (en) Heat migration resistant micro welding spot structure and preparation method thereof
CN116352244A (en) Preparation method for presetting gold-tin soldering lug by utilizing transient liquid phase diffusion soldering
CN110278667B (en) Microwave dielectric plate and carrier integrated welding method
KR20120021154A (en) Manufacturing method of substrate for power module equiptted with heat sink, substrate for power module equiptted with heat sink, and power module
CN111885852A (en) Preparation method of ceramic copper-clad plate
CN114940004B (en) Copper-clad nitride ceramic substrate and preparation method thereof
EP3257109B1 (en) Electrical connection tape
CN114043122B (en) High-temperature brazing filler metal containing Cu @ Sn core-shell bimetallic powder and preparation method and application thereof
JP5796299B2 (en) Power module substrate with heat sink, manufacturing method of power module substrate with heat sink, and power module
CN215266267U (en) Spacer and double-sided cooling power module
CN116779584B (en) Low-chip temperature gradient power semiconductor module packaging structure and method
JP7259084B2 (en) Sinter-ready silver film
CN111699067B (en) Method for producing a structural unit and method for connecting a component to such a structural unit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination