CN113947048B - Interface connection method for verifying design to be tested and related equipment - Google Patents
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Abstract
The present disclosure provides an interfacing method and related devices for verifying a design to be tested, the method comprising: packaging a first layer design module to be designed to generate a first layer packaging module; declaring struct type members in the agent component in the port declaration list, and defining connections and data type conversions between wire type ports and struct type ports; generating a first interface file in a first layer verification environment based on a port statement list, a first layer packaging module and a preset interface connection method; and generating a first connection file based on the first interface file and the bind statement, and connecting the first-layer verification environment to the first-layer module package module based on the first connection file so as to realize data transmission between the first-layer verification environment and the first-layer design module. According to the method and the device, automatic declaration, connection and configuration transfer of the interface are achieved, so that development efficiency is improved, and project progress is quickened.
Description
Technical Field
The present disclosure relates to the field of verification, and in particular, to an interfacing method and related apparatus for verifying a design under test.
Background
In the verification of register transfer level circuitry RTL (Register Transfer Level), all interfaces typically need to be declared, connected, and configuration passed in a top-level verification environment. However, as RTL designs become more and more complex, the more the hierarchy becomes, and possibly a complex chip may be composed of hundreds of sub-modules, so that hundreds of corresponding interfaces may be reached, and in the top-level verification environment, only declaring an interface requires at least thousands of times, so that errors are easily missed. Moreover, the instantiation path level inside the chip is lengthy and complex, and human errors are easily generated in the process of interface connection and configuration transfer. If all interfaces below their hierarchy are declared, connected and configured at the top level of the verification platform, there will be a great deal of repetitive work affecting development efficiency. In addition, the existing RTL verification tool VCS does not support the conversion of the automatic connection direction of the struct port data type during the simulation, so that the automatic connection of the interface of the struct port data type cannot be realized.
Disclosure of Invention
In view of the above, an object of the present disclosure is to provide an interfacing method for verifying a design under test, and related apparatus and program product.
According to a first aspect of the present disclosure, there is provided an interfacing method for verifying a design under test, the interface type of the design under test including a struct type, the method comprising:
packaging the first layer design module to be designed to generate a first layer packaging module so as to instantiate the first layer design module; the wire type port of the first layer of module is connected with the struct type interface of the first layer of module;
declaring struct type members in the agent component in a port declaration list, and defining connections and data type conversions between the wire type port and the struct type port;
generating the first interface file in the first-layer verification environment based on the port statement list, the first-layer packaging module and a preset interface connection method;
and generating a first connection file based on the first interface file and the bind statement, and connecting the first-layer verification environment to the first-layer module packaging module based on the first connection file so as to realize data transmission between the first-layer verification environment and the first-layer design module.
According to a second aspect of the present disclosure, there is provided a verification method of a design under test, the design under test including a struct type interface, the method comprising:
According to the method of the first aspect, data transmission between the first verification environment and the first layer design module is realized;
the first-layer verification environment sends first excitation data of a wire type to a wire type port of the first-layer packaging module;
the first layer packaging module converts the first excitation data of the wire type into second excitation data of the struct type based on the first connection file, and sends the second excitation data to a struct type interface of the first layer design module;
the first design module generates first return data of struct type in response to the second excitation data;
the first layer packaging module acquires the first return data and converts the first return data into second return data of a wire type based on the first connection file; and sending the second return data to the first layer verification environment;
and the first layer verification environment compares whether the received second returned data is consistent with a preset reference signal or not so as to determine the performance of the design to be tested.
According to a third aspect of the present disclosure, there is provided an interfacing apparatus for verifying a design under test, the interface type of the design under test including a struct type, the apparatus comprising:
The wire type packaging module is used for packaging the first layer design module to be designed to generate a first layer packaging module so as to instantiate the first layer design module; the wire type port of the first layer of module is connected with the struct type interface of the first layer of module;
a port declaration module, configured to declare a struct type member in the agent component in a port declaration list, and define a connection between the wire type port and the struct type port, and a data type conversion;
the first-layer verification module is used for generating the first interface file in the first-layer verification environment based on the port statement list, the first-layer packaging module and a preset interface connection method;
and generating a first connection file based on the first interface file and the bind statement, and connecting the first-layer verification environment to the first-layer module based on the first connection file so as to realize data transmission between the first-layer verification environment and the first-layer design module.
According to a fourth aspect of the present disclosure there is provided an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method according to the first aspect when executing the program.
According to a fifth aspect of the present disclosure, there is provided a non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of the first aspect.
According to a sixth aspect of the present disclosure, there is provided a computer program product comprising a computer readable storage medium storing instructions that, when executed, cause at least one central processor unit of a computing device to perform the method according to the first aspect.
As can be seen from the above description, the interface connection method for verifying a design to be tested, that is, related equipment and program product, provided by the present disclosure, encapsulates the interface in the verification environment, completes connection between the verification environment and the design to be tested by adopting a bind statement, and transmits the interface connection configuration of the present level to the next verification environment by using a configuration database, thereby automatically completing multi-level interface statement, connection and configuration transmission, improving development efficiency of the verification platform, reducing repetitive development work, improving work efficiency of developers, playing a role in accelerating project progress, and thus ensuring streaming time of chip projects.
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In order to more clearly illustrate the technical solutions of the present disclosure or related art, the drawings required for the embodiments or related art description will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
FIG. 1 is a schematic block diagram of a UVM verification platform;
FIG. 2 is a schematic block diagram of a verification environment architecture and an RTL design architecture in accordance with an embodiment of the present disclosure;
FIG. 3 is a schematic flow chart of an interfacing method for verifying a design under test in accordance with an embodiment of the disclosure;
FIG. 4 is a schematic diagram of a verification method of a design under test according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of an interfacing apparatus for verifying a design under test according to an embodiment of the present disclosure;
fig. 6 is a schematic block diagram of an electronic device of an embodiment of the present disclosure.
Detailed Description
For the purposes of promoting an understanding of the principles and advantages of the disclosure, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same.
It should be noted that unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first," "second," and the like, as used in embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
UVM (Universal Verification Methodology) verification platform is a set of verification platform developed based on TLM (Transaction Level Modeling) communication, and can help verification developers build a configurable reusable verification environment. As shown in fig. 1, fig. 1 shows a schematic block diagram of a UVM verification platform. The verification platform test in fig. 1 performs verification test on the design under verification DUT module through the interface. During testing, all interfaces (interfaces) typically need to be declared, connected, and configured in a top-level verification environment. Whereas for complex RTL designs, asserting only the interface may require at least thousands of times, leaving errors easily missed. Furthermore, conventional interfacing typically requires manual or script implementation of signal connections to all interfaces in the design under test, which is cumbersome and error-prone for hierarchically complex design modules. There are often master-slave modules, and some input interfaces of the modules need to be driven by the verification environment and some by the preamble design module, so that connections need to be made according to the directional characteristics of the ports during the interfacing process. For complex design modules, there are often hundreds or thousands of interface signals, so that distinguishing the signal connection directions of interfaces one by one is easy to cause errors, and development efficiency is affected.
The use of struct data types in the interface for design and verification can greatly reduce the amount of codes for connectivity, for example, typically more than 2500 different signal ports are easily available within a medium-sized SOC, then one line of codes is used to declare wire net type variables, one line of codes is used to connect the source of the signal, another line of codes is used to connect the terminal of the signal, then at least 2500 x 3 = 7500 lines of codes need to be written for these intricate ports within the optical connection. The above-mentioned code amount is greatly reduced if the signal ports associated with each other are combined together using a structure. The use of struct data types in the interface also allows signal ports associated with each other to be combined together for easy understanding by the developer, thereby facilitating development and debugging. The defined struct port data type is used, so that naming and reuse can be standardized, project management is convenient, data signal members can be easily increased or decreased in the struct data type, and adjustment in the development process is convenient. However, the existing RTL verification tool VCS does not support the conversion of the automatic connection direction of the struct port data type at the time of simulation, so that it cannot implement the automatic connection of the interface of the struct port data type.
In view of this, the embodiments of the present disclosure provide an interface connection method for verifying a design to be tested, and related devices and program products, encapsulate the design to be tested and implement conversion of wire type data and struct type data, and encapsulate an interface in a verification environment, and complete connection between the verification environment and the design to be tested by adopting a bind statement, thereby implementing support compatibility for supporting a struct structure type of a port type in an RTL design, achieving an effect of supporting conversion of an automatic connection direction of the struct port data type when a VCS is simulated, and implementing connection of all interface signals in the design to be tested without manual or by scripts, so that code quantity is reduced and development efficiency is improved by using characteristics that the VCS can automatically convert directions according to driving conditions when running.
Referring to FIG. 2, FIG. 2 shows a schematic block diagram of a verification environment architecture and an RTL design architecture in accordance with an embodiment of the present disclosure. In fig. 2, the authentication environment interface includes: the top verification environment top_env corresponds to a top module top_module in the RTL design, and is used for verifying the top module top_module and belongs to the same layer. The top verification environment top_env is nested with the bottom verification environment env, corresponds to a sub-module sub_module in the RTL design, is nested in the top module top_module, is used for verifying the sub-module sub_module, and belongs to the same layer. The top module top_module may instantiate the sub-module sub_module. The agent components of the bottom verification environment env are in one-to-one correspondence with interfaces of the RTL design structure, for example, 3 bottom verification environments env are in one-to-one correspondence with 3 sub-modules sub_modules, and 2 agent components in each bottom verification environment env are respectively corresponding to an input interface and an output interface of the sub-modules sub_modules. Since declaration, connection and configuration transfer of interfaces encapsulated by agent components in all underlying verification environments need to be completed in the verification platform. At this time, the declaration, connection and configuration transfer of interfaces at the verification platform have become more complex, however, if the RTL design hierarchy is more complex as shown in fig. 2, the declaration, connection and configuration transfer of interfaces encapsulated by all agent components needs to be continued in the verification platform, and the path hierarchy and code statements can become very tedious and complex, and are prone to errors. In a complex RTL design this is almost impossible to do.
Because the VCS only supports the conversion of the automatic connection direction of the port data type of the wire logic type in the simulation, the applicant of the present disclosure creatively discovers that a layer of dutjwrapper can be packaged on the outer layer of the DUT to be tested, and then the DUT to be tested is connected to the DUT to be tested through the wire, namely the conversion from the wire data type to the struct data type is completed, so that the support compatibility of the automatic conversion connection direction of the port type to the struct structure type in the design to be tested is realized.
With the above considerations in mind, referring to FIG. 3, FIG. 3 shows a schematic flow chart diagram of an interfacing method for verifying a design under test, in accordance with an embodiment of the present disclosure. The verification environment and the design to be tested may be as shown in fig. 2, where a first layer of verification environment env is nested in a second layer of verification environment top_env, the first layer of design module sub_module is nested in the second layer of design module top_module, the first layer of verification environment env is used for packaging the first layer of design module sub_module so as to provide the second layer of verification environment top_env for instantiation and reuse, and the second layer of verification environment top_env is used for packaging the second layer of design module top_module so as to provide the upper layer of verification environment for instantiation and reuse; based on each layer of verification environment, test cases can be written on the verification environments to simulate and debug modules of corresponding layers of the design to be tested, so that verification of the DUT of the design to be tested is completed.
As shown in fig. 3, the interface type of the design under test includes a struct type, and the interfacing method 300 for verifying the design under test includes:
step S310, packaging the first layer design module to be designed to generate a first layer packaging module so as to instantiate the first layer design module; the wire type port of the first layer module is connected with the struct type interface of the first layer design module.
Because the interface type of the design to be tested is struct type, the outer layer of the interface type can be packaged to generate a first layer packaging module, and the first layer packaging module is connected to the struct type interface of the first layer design module through a wire type port so as to convert the logic data type of the first layer packaging module and the data type of the packet struct of the first layer design module, thereby realizing the support compatibility of the struct structure type of the port type in RTL design. The first layer design module sub_module as in fig. 2 may be implemented using the following exemplary code program:
the first layer design module sub_module is packaged to obtain a sub_module_wrapper file, which can be implemented by adopting the following exemplary code program:
Step S320, declaring struct type members in the agent component in the first layer verification environment in a port declaration list, and defining connection and data type conversion between the wire type port and the struct type port.
And declaring the struct type members in the agent component in the port declaration list, namely adding struct variables of the design to be tested into the port declaration list. The data port between the layer one package module and the layer one design module may then be connected accordingly to facilitate later driving of stimulus data from the layer one verification environment to the layer one design module via the data port or returning of return data by the layer one design module to the layer one verification environment via the data port. In particular implementations, the port declaration list demo_ uvc _interface may be implemented using the following exemplary code:
step S330, generating the first interface file in the first layer verification environment based on the port declaration list, the first layer packaging module and a preset interfacing method.
The first interface file may include a port of the first layer verification environment corresponding to the first layer design module and a connection method thereof. In some embodiments, the interfacing method in the first interface file includes a set_vif function. In a specific embodiment, in a first layer verification environment env corresponding to a first layer design module sub_module, a first interface file demo_env_interface_wrapper is newly added to complete the declaration and configuration transfer of an interface included in a design to be tested, where the first interface file may be implemented by using the following program codes:
It can be seen that the first encapsulation module sub_module_wrapper is designated when the interface is declared in the first interface file demo_env_interface_wrapper.
And step S340, generating a first connection file based on the first interface file and the bind statement, and connecting the first-layer verification environment to the first-layer module based on the first connection file so as to realize data transmission between the first-layer verification environment and the first-layer design module.
In specific implementation, the interface configuration transfer of the first layer may be performed by using the set_vif function, which is an interface connection method in the first interface file, and the following exemplary program code implementation may be adopted:
then, the bind statement may be used to socket the first layer packaging module sub_module_wrapper with the first interface file demo_env_interface_wrapper, so as to generate a first connection file, so as to implement the interface connection between the first layer packaging module and the first layer verification environment, thereby transmitting data between the first layer design module and the first layer verification environment. The first connection file module tb rtl inst top may be implemented using the following exemplary program code:
the method can realize the support compatibility of VCS to the port type of struct structure in the design to be tested, realize the rapid declaration, connection and configuration transfer of interfaces involved in the complex design to be tested, promote the development efficiency of the verification platform, realize the reusability of the declaration, connection and configuration transfer codes of the interfaces of the verification platform, and reduce the repeated development work.
In some embodiments, the method 300 further comprises:
generating an interface configuration file of a second-layer verification environment based on the first connection file and the interface setting of the second-layer design module, and transmitting the interface configuration file to the second-layer verification environment through a configuration database;
the first layer verification environment is nested in the second layer verification environment, the first layer design module is nested in the second layer design module, the first layer verification environment is used for packaging the first layer design module so as to provide the second layer verification environment for instantiation and reuse, and the second layer verification environment is used for packaging the second layer design module so as to provide the upper layer verification environment for instantiation and reuse.
In some embodiments, the interface configuration file includes an interface configuration macro and a reusable connection file, generating an interface configuration file for a second layer verification environment based on the first connection file includes:
generating the reusable connection file based on the first connection file;
and generating the interface configuration macro based on the interface connection method in the first connection file.
In a specific implementation, the reusable connection file is used to implement the reusability of the code of the first connection file, and the reusability connection file demo_env_interface_bind may be implemented by using the following exemplary program code:
the interface configuration macro demo_env_definitions may also be generated based on the interface connection method set_vif in the first connection file to transfer the interface connection manner of the first hierarchy to the next hierarchy (e.g., top_env in fig. 2) through the configuration database (e.g., config_db in the UVM platform). The configuration macro demo_env_definitions may be implemented using the following exemplary code:
in some embodiments, the method 300 may further comprise:
generating a second interface file in the second-layer verification environment based on the port declaration list, a second-layer encapsulation module, and the interface configuration file; and the second-layer packaging module is used for packaging and generating the second-layer design module to be designed so as to exemplify the second-layer design module.
The process of packaging the second layer design module of the design to be tested to generate the second layer packaging module is similar to that of the first layer packaging module, and will not be described herein. And similarly, the second-layer verification environment is connected to the second-layer module, and after the data type conversion is completed through the second-layer module, the second-layer verification environment is in data transmission with the second-layer design module.
In some embodiments, the interface arrangement of the second tier design module comprises the second tier design module being provided with a separate interface;
and generating the second interface file based on the port statement list, the second layer packaging module and the interface configuration macro.
In some embodiments, the interface arrangement of the second tier design module includes the second tier design module not being provided with a separate interface;
and generating the second interface file based on the port statement list and a second layer encapsulation module.
In a specific implementation, when the second layer design module top_module does not set an independent interface, the corresponding second layer encapsulation module top_module_wrapper does not set an independent interface, but is only used for instantiating the first layer encapsulation module sub_module_wrapper corresponding to the first layer design module sub_module, and at this time, the second interface file demo_env_top_interface_wrapper can be generated only based on the port declaration list and the second layer encapsulation module, which can be implemented by adopting the following exemplary program code:
it can be seen that here the interface port is connected to the second layer encapsulation module top_module_wrapper, where the set_vif function is a null function, since top_module has no separate interface, but is responsible for instantiating the connection to the first layer design module sub_module, and the corresponding second layer encapsulation module top_module_wrapper has no separate interface.
When the second layer encapsulation module top_module_wrapper is provided with a separate interface, the set_vif function in the exemplary program code of the second interface file demo_env_top_interface_wrapper may not be a null function, and the set_vif function may be similar to the set_vif function in the first interface file demo_env_interface_wrapper, which is not described herein.
In some embodiments, the method 500 may further comprise:
and generating a second connection file based on the second interface file and the bind statement, and connecting the second-layer verification environment to the second-layer module package module based on the second connection file so as to realize data transmission between the second-layer verification environment and the second-layer design module.
In specific implementation, the second-level interface configuration transfer may be performed by using the set_vif function, which is an interface connection method in the second interface file, however, the second-level encapsulation module top_module_wrapper corresponding to the second-level design module top_module in fig. 2 is not provided with an independent interface, and then the second-level interface configuration transfer may be performed by using the interface configuration macro in the first-level verification environment env corresponding to the first-level encapsulation module sub_module_wrapper, which may be implemented by using the following exemplary program code:
Next, to achieve code reusability of the second connection file, a second level reusable connection file demo_env_top_interface_bind is generated, which may be implemented using the following exemplary program code:
and when the second layer encapsulation module top_module_wrapper is provided with an independent interface, generating a second layer interface configuration macro based on an interface connection method set_vif in the second connection file; when the second layer encapsulation module top_module_wrapper is not provided with a separate interface, as shown in fig. 2, the interface configuration macro in the first layer verification environment env corresponding to the first layer encapsulation module sub_module_wrapper may be adopted to pass it to the next layer through the configuration database (such as config_db in the UVM platform). The configuration macro of the second level, demo_env_top_definitions, may be implemented using the following exemplary code:
and based on that the second-layer encapsulation module top_module_wrapper can be sleeved with the second interface file demo_env_top_interface_wrapper by adopting the second-layer reusable connection file demo_env_top_interface_bind, generating a second connection file so as to realize the interface connection between the second-layer encapsulation module and the second-layer verification environment, and further realize the data transmission between the second-layer verification environment and the second-layer design module. The second connection file module tb rtl inst top may be implemented using the following exemplary program code:
Compared with the traditional interface connection method, the embodiment of the disclosure does not need to connect all interface signals in the DUT module manually or through scripts, and the characteristic that the VCS automatically changes direction according to the driving condition is utilized when the VCS runs, so that the code quantity is reduced, and the development efficiency is improved. And the complexity of connection according to the direction characteristics of the ports, which is caused by the design of the master-slave module and the different driving sources of the module input interface, is eliminated, so that the development efficiency is further improved, the UVM development framework is standardized, and team cooperation and project management are facilitated. Meanwhile, the method has the advantages of designing and verifying by using struct data types in the interface, such as reducing the code quantity of connectivity, and combining signal ports related to each other, so that the method is easy for a developer to understand, and is convenient for development and debugging. The defined struct port data type is used, so that naming and reuse can be standardized, project management is facilitated, data signal members can be easily increased or decreased in the struct data type, and adjustment in the development process is facilitated. Finally, the working efficiency of the developer is greatly improved, and the project progress is accelerated, so that the chip project streaming time is ensured.
It should be appreciated that the above examples are merely illustrative of the verification environment and the design under test in fig. 2, and are intended to set the verification environment and the design under test, which may include more levels, and are not limited thereto. When the verification environment and the design to be tested include more layers, the declaration, connection and configuration of the interfaces in the first layer verification environment and the second layer verification environment can be repeatedly performed until all layers are completed.
According to an embodiment of the present disclosure, as shown in fig. 4, there is also provided a verification method of a design to be tested, including:
according to the method, data transmission between the first verification environment and the first layer design module is achieved;
the first-layer verification environment sends first excitation data of a wire type to a wire type port of the first-layer packaging module;
the first layer packaging module converts the first excitation data of the wire type into second excitation data of the struct type based on the first connection file, and sends the second excitation data to a struct type interface of the first layer design module;
the first design module generates first return data of struct type in response to the second excitation data;
The first layer packaging module acquires the first return data and converts the first return data into second return data of a wire type based on the first connection file; and sending the second return data to the first layer verification environment;
and the first layer verification environment compares whether the received second returned data is consistent with a preset reference signal or not so as to determine the performance of the design to be tested.
It should be noted that the method of the embodiments of the present disclosure may be performed by a single device, such as a computer or a server. The method of the embodiment can also be applied to a distributed scene, and is completed by mutually matching a plurality of devices. In the case of such a distributed scenario, one of the devices may perform only one or more steps of the methods of embodiments of the present disclosure, the devices interacting with each other to accomplish the methods.
It should be noted that the foregoing describes some embodiments of the present disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments described above and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
According to an embodiment of the present disclosure, corresponding to the method of any embodiment described above, the present disclosure further provides an interfacing device for verifying a design to be tested. Referring to fig. 5, an interfacing apparatus for verifying a design under test, comprising:
the wire type packaging module is used for packaging the first layer design module to be designed to generate a first layer packaging module so as to instantiate the first layer design module; the wire type port of the first layer of module is connected with the struct type interface of the first layer of module;
a port declaration module, configured to declare a struct type member in the agent component in a port declaration list, and define a connection between the wire type port and the struct type port, and a data type conversion;
the first-layer verification module is used for generating the first interface file in the first-layer verification environment based on the port statement list, the first-layer packaging module and a preset interface connection method;
and generating a first connection file based on the first interface file and the bind statement, and connecting the first-layer verification environment to the first-layer module based on the first connection file so as to realize data transmission between the first-layer verification environment and the first-layer design module.
In some embodiments, the interfacing means for verifying the design under test further comprises:
a second layer verification module, configured to generate a second interface file based on the port declaration list, a second layer encapsulation module, and the interface configuration file in the second layer verification environment; the second-layer packaging module is used for packaging and generating the second-layer design module to be designed so as to instantiate the second-layer design module;
and generating a second connection file based on the second interface file and the bind statement, and connecting the second-layer verification environment to the second-layer module package module based on the second connection file so as to realize data transmission between the second-layer verification environment and the second-layer design module.
It should be appreciated that embodiments according to the present disclosure may further include more layers of verification modules, which are not described herein.
For convenience of description, the above devices are described as being functionally divided into various modules, respectively. Of course, the functions of the various modules may be implemented in the same one or more pieces of software and/or hardware when implementing the present disclosure.
The device of the foregoing embodiment is configured to implement the interfacing method in the corresponding authentication environment in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiment, which is not described herein.
According to an embodiment of the present disclosure, corresponding to the method of any embodiment, the present disclosure further provides an electronic device, including a memory, a processor, and a computer program stored on the memory and capable of running on the processor, where the processor implements the interfacing method for verifying a design under test according to any embodiment when executing the program.
Fig. 6 shows a schematic block diagram of an electronic device according to an embodiment of the disclosure. The apparatus may include: processor 610, memory 620, input/output interface 630, communication interface 640, and bus 650. Wherein processor 610, memory 620, input/output interface 630, and communication interface 640 enable communication connections among each other within the device via bus 650.
The processor 610 may be implemented by a general-purpose CPU (Central Processing Unit ), microprocessor, application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, etc. for executing relevant programs to implement the technical solutions provided in the embodiments of the present disclosure.
The Memory 620 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory ), a static storage device, a dynamic storage device, or the like. Memory 620 may store an operating system and other application programs, and when the technical solutions provided by the embodiments of the present specification are implemented in software or firmware, relevant program codes are stored in memory 620 and invoked for execution by processor 610.
The input/output interface 630 is used for connecting with an input/output module to realize information input and output. The input/output module may be configured as a component in a device (not shown) or may be external to the device to provide corresponding functionality. Wherein the input devices may include a keyboard, mouse, touch screen, microphone, various types of sensors, etc., and the output devices may include a display, speaker, vibrator, indicator lights, etc.
The communication interface 640 is used to connect a communication module (not shown in the figure) to enable communication interaction between the present device and other devices. The communication module may implement communication through a wired manner (such as USB, network cable, etc.), or may implement communication through a wireless manner (such as mobile network, WIFI, bluetooth, etc.).
It should be noted that although the above device only shows the processor 610, the memory 620, the input/output interface 630, the communication interface 640, and the bus 650, in the implementation, the device may further include other components necessary for achieving normal operation. Furthermore, it will be understood by those skilled in the art that the above-described apparatus may include only the components necessary to implement the embodiments of the present description, and not all the components shown in the drawings.
The electronic device of the foregoing embodiment is configured to implement the corresponding interface connection method for verifying the design to be tested in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiment, which is not described herein.
According to an embodiment of the present disclosure, corresponding to any of the embodiment methods described above, the present disclosure also provides a computer program product comprising a computer-readable storage medium storing instructions that, when executed, cause at least one central processor unit of a computing device to perform the method for verifying an interface connection of a design under test according to an embodiment of the present disclosure.
According to an embodiment of the present disclosure, corresponding to the method of any embodiment described above, the present disclosure further provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform the interfacing method for verifying a design under test as described in any embodiment described above.
The computer readable media of the present embodiments, including both permanent and non-permanent, removable and non-removable media, may be used to implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device.
The storage medium of the foregoing embodiment stores computer instructions for causing the computer to execute the interfacing method for verifying a design under test according to any one of the foregoing embodiments, and has the advantages of the corresponding method embodiments, which are not described herein.
Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of the disclosure, including the claims, is limited to these examples; the technical features of the above embodiments or in the different embodiments may also be combined under the idea of the present disclosure, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure as described above, which are not provided in details for the sake of brevity.
Additionally, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown within the provided figures, in order to simplify the illustration and discussion, and so as not to obscure the embodiments of the present disclosure. Furthermore, the devices may be shown in block diagram form in order to avoid obscuring the embodiments of the present disclosure, and this also accounts for the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform on which the embodiments of the present disclosure are to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that embodiments of the disclosure can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.
While the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of those embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.
The disclosed embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Accordingly, any omissions, modifications, equivalents, improvements, and the like, which are within the spirit and principles of the embodiments of the disclosure, are intended to be included within the scope of the disclosure.
Claims (10)
1. An interfacing method for verifying a design under test, wherein an interface type of the design under test comprises a struct type, the method comprising:
packaging the first layer design module to be designed to generate a first layer packaging module so as to instantiate the first layer design module; the wire type port of the first layer packaging module is connected with the struct type interface of the first layer design module; the first layer packaging module is connected to a struct type interface of the first layer design module through a wire type port so as to convert a logic data type of the first layer packaging module and a data type of a packdsstruct of the first layer design module;
Declaring struct type members of the agent component in the first layer verification environment in the port declaration list;
generating a first interface file in the first-layer verification environment based on the port statement list, the first-layer packaging module and a preset interface connection method;
and generating a first connection file based on the first interface file and the bind statement, and connecting the first-layer verification environment to the first-layer packaging module based on the first connection file so as to realize data transmission between the first-layer verification environment and the first-layer design module.
2. The method according to claim 1, wherein the method further comprises:
generating an interface configuration file of a second-layer verification environment based on the interface settings of the first connection file and the second-layer design module, and transmitting the interface configuration file to the second-layer verification environment through a configuration database;
the first layer verification environment is nested in the second layer verification environment, the first layer design module is nested in the second layer design module, the first layer verification environment is used for packaging the first layer design module so as to provide the second layer verification environment for instantiation and reuse, and the second layer verification environment is used for packaging the second layer design module so as to provide the upper layer verification environment for instantiation and reuse.
3. The method of claim 2, wherein the interface configuration file comprises an interface configuration macro and a reusable connection file, generating an interface configuration file for a second tier authentication environment based on the first connection file, comprising:
generating the reusable connection file based on the first connection file for reusable instantiation of the second-layer verification environment;
and generating the interface configuration macro based on the interface connection method in the first connection file.
4. A method according to claim 3, characterized in that the method further comprises:
generating a second interface file in the second-layer verification environment based on the port declaration list, a second-layer encapsulation module, and the interface configuration file; the second-layer packaging module is used for packaging and generating the second-layer design module to be designed so as to instantiate the second-layer design module;
and generating a second connection file based on the second interface file and the bind statement, and connecting the second-layer verification environment to the second-layer packaging module based on the second connection file so as to realize data transmission between the second-layer verification environment and the second-layer design module.
5. The method of claim 4, wherein the interface arrangement of the second tier design module comprises the second tier design module being provided with a separate interface;
and generating the second interface file based on the port statement list, the second layer packaging module and the interface configuration macro.
6. The method of claim 4, wherein the interface setting of the second tier design module comprises the second tier design module not setting a separate interface;
and generating the second interface file based on the port statement list and a second layer encapsulation module.
7. A method of verifying a design under test, the design under test comprising a struct type interface, the method comprising:
the method of any of claims 1-6 enabling data transfer of a first layer verification environment with the first layer design module;
the first-layer verification environment sends first excitation data of a wire type to a wire type port of the first-layer packaging module;
the first layer packaging module converts the first excitation data of the wire type into second excitation data of the struct type based on the first connection file, and sends the second excitation data to a struct type interface of the first layer design module;
The first layer design module generates first return data of struct type in response to the second excitation data;
the first layer packaging module acquires the first return data and converts the first return data into second return data of a wire type based on the first connection file; and sending the second return data to the first layer verification environment;
and the first layer verification environment compares whether the received second returned data is consistent with a preset reference signal or not so as to determine the performance of the design to be tested.
8. An interfacing apparatus for verifying a design under test, wherein an interface type of the design under test comprises a struct type, the apparatus comprising:
the wire type packaging module is used for packaging the first layer design module to be designed to generate a first layer packaging module so as to instantiate the first layer design module; the wire type port of the first layer packaging module is connected with the struct type interface of the first layer design module; the first layer packaging module is connected to a struct type interface of the first layer design module through a wire type port so as to convert a logic data type of the first layer packaging module and a data type of a packdsstruct of the first layer design module;
The port declaration module is used for declaring struct type members of the agent components in the first-layer verification environment in the port declaration list;
the first-layer verification module is used for generating a first interface file in the first-layer verification environment based on the port statement list, the first-layer packaging module and a preset interface connection method;
and generating a first connection file based on the first interface file and the bind statement, and connecting the first-layer verification environment to the first-layer packaging module based on the first connection file so as to realize data transmission between the first-layer verification environment and the first-layer design module.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method of any one of claims 1 to 7 when the program is executed.
10. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method of any one of claims 1 to 7.
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