CN114564394A - Test case determination method, system and related components - Google Patents
Test case determination method, system and related components Download PDFInfo
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- CN114564394A CN114564394A CN202210182265.2A CN202210182265A CN114564394A CN 114564394 A CN114564394 A CN 114564394A CN 202210182265 A CN202210182265 A CN 202210182265A CN 114564394 A CN114564394 A CN 114564394A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3672—Test management
- G06F11/3684—Test management for test design, e.g. generating new test cases
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
Abstract
The application discloses a test case determination method, a test case determination system and related components, wherein the method comprises the following steps: receiving target test parameters; inquiring whether a test excitation sequence corresponding to the target test parameter exists in an excitation pool or not; if not, generating the test excitation sequence according to the target test parameters and the test function; and outputting the test excitation sequence to generate a test case for the design verification to be tested. According to the method and the device, the test excitation sequence is automatically output according to the target test parameters, the excitation sequence can directly generate the test case to carry out the design verification to be tested, the complicated manual configuration and flow carding are avoided, and the method and the device have the advantages of flexible multiplexing and project iteration utilization.
Description
Technical Field
The invention relates to the field of system test, in particular to a method and a system for determining a test case and a related component.
Background
Currently, test verification is a crucial process in the chip development process, and is a key point for determining that a design to be tested normally and correctly works. At present, the most common Verification method is to adopt a Universal Verification Method (UVM) method, from building a UVM Verification platform to developing a test case based on an SV language, where an excitation Sequence is the most important loop, and is used to generate a test excitation so as to enable a device under test to work, and further observe a test result.
When the device to be tested is SoC (system on Chip), due to the oversize, numerous debugging resources need to be debugged, which will undoubtedly increase the debugging complexity of the verification personnel. When test cases developed based on SV (System Verilog, System hardware description language) language are compiled, the compilation of the entire UVM verification environment is involved, and then executable files (simv) are generated. The process is long in time consumption, large in consumption of server resources, not suitable for frequently modifying the test cases, and not strong in flexibility for the tested devices with high test case requirements.
Therefore, how to provide a solution to the above technical problems is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention provides a method, a system and related components for determining a test case efficiently and quickly. The specific scheme is as follows:
a test case determination method comprises the following steps:
receiving target test parameters;
inquiring whether a test excitation sequence corresponding to the target test parameter exists in an excitation pool or not;
if not, generating the test excitation sequence according to the target test parameters and the test function;
and outputting the test excitation sequence to generate a test case for the design verification to be tested.
Preferably, the process of generating the test excitation sequence according to the target test parameter and the test function includes: and generating the test excitation sequence through a JTAG interface chain according to the target test parameters and the test functions.
Preferably, the test stimulus sequence is specifically an IR sequence and a DR sequence.
Preferably, the design under test is a design under test comprising a DAP.
Preferably, the process of generating the test excitation sequence according to the target test parameter and the test function includes:
and generating and combining a DPI-C interface method to output the test excitation sequence according to the target test parameters and the test function.
Preferably, the test function includes:
a VIP reset and un-reset function;
IR/DR load function;
TDO checking function;
basic test case functions.
Preferably, the test case is a C language test case;
correspondingly, the process of the test case for the design verification to be tested comprises the following steps: and sending a preset format file generated in the compiling process of the test case to an executable file so as to start the verification of the design to be tested.
Correspondingly, the application also discloses a test case determination system, which comprises:
the parameter interface is used for receiving target test parameters;
the action module is used for inquiring whether a test excitation sequence corresponding to the target test parameter exists in the excitation pool or not; if not, generating the test excitation sequence according to the target test parameters and the test function;
and the output module is used for outputting the test excitation sequence so as to generate a test case for the design verification to be tested.
Correspondingly, the present application also discloses a test case determining apparatus, including:
a memory for storing a computer program;
a processor for implementing the steps of the test case determination method according to any one of the above when executing the computer program.
Accordingly, the present application also discloses a readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the steps of the test case determination method according to any one of the above.
The application discloses a test case determining method, which comprises the following steps: receiving target test parameters; inquiring whether a test excitation sequence corresponding to the target test parameter exists in an excitation pool or not; if not, generating the test excitation sequence according to the target test parameters and the test function; and outputting the test excitation sequence to generate a test case for the design verification to be tested. According to the method and the device, the test excitation sequence is automatically output according to the target test parameters, the excitation sequence can directly generate the test case to carry out the design verification to be tested, the complicated manual configuration and flow carding are avoided, and the method and the device have the advantages of flexible multiplexing and project iteration utilization.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flowchart illustrating steps of a test case determination method according to an embodiment of the present invention;
FIG. 2 is a process diagram of a test case determination method according to an embodiment of the present invention;
FIG. 3 is a structure diagram of a test case determination system according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
When the device to be tested is at SoC level, many debugging resources need to be debugged due to the overlarge scale, which undoubtedly increases the debugging complexity of the verification personnel. When compiling a test case developed based on the SV language, compilation of the entire UVM verification environment will be involved, followed by generation of an executable file (simv). The process is long in time consumption, large in consumption of server resources, not suitable for frequently modifying test cases, and not strong in flexibility for tested equipment with high test case requirements.
According to the method and the device, the test excitation sequence is automatically output according to the target test parameters, the excitation sequence can directly generate the test case to carry out the design verification to be tested, the complicated manual configuration and flow carding are avoided, and the method and the device have the advantages of flexible multiplexing and project iteration utilization.
The embodiment of the invention discloses a method for determining a test case, which is shown in figure 1 and comprises the following steps:
s1: receiving target test parameters;
s2: inquiring whether a test excitation sequence corresponding to the target test parameter exists in the excitation pool; if not, sequentially executing the steps S3 and S4, and if yes, directly executing the step S4;
s3: generating a test excitation sequence according to the target test parameters and the test function;
s4: and outputting the test excitation sequence to generate a test case for the design verification to be tested.
It is understood that the test stimulus sequence generated in step S3 can be stored in the stimulus pool, and if the test stimulus sequence is needed again in the subsequent test, the test stimulus sequence can be directly output for use.
It can be understood that, the basic flow of accessing system resources based on DAP (Debug Access Port) is similar in the prior art, but the debugging function process is complex, that is, according to the position of DAP in the JTAG (Joint Test Action Group), the DP (Debug Port ) type, the position and type of AP (Access Port ), the Access object, etc., for different verification targets, the required Test stimulus is different, and these Test stimuli require manual setting by a worker, which is very tedious and time-consuming.
By the test case determining method in the embodiment, the test excitation sequence corresponding to the target test parameter can be directly output, so that the test case corresponding to the target test parameter is generated to complete related design verification to be tested, a worker does not need to manually modify the code of the test case, and flexible multiplexing can be realized.
In some specific embodiments, the target test parameters include, but are not limited to, a verification target parameter verf _ obj, and/or a structure parameter dap _ offset/ap _ offset/ap _ type, and/or an object parameter obj _ id/obj _ reg _ addr.
In some specific embodiments, the generating the test excitation sequence according to the target test parameter and the test function includes: and generating the test excitation sequence through a JTAG interface chain according to the target test parameters and the test function. Specifically, a plurality of devices are connected in series through a JTAG interface in a JTAG interface chain, the output of the former device is used as the input of the latter device, and the devices in the system can be respectively debugged according to the chain structure; further, the test excitation sequence is specifically an IR sequence and a DR sequence; at this time, the Design Under Test (DUT) of the Test case may be applied in this embodiment, and may be a Design Under Test including a DAP, or a Design Under Test that is debugged in another form. Typically, the DAP receives JTAG data from an external port, translates it into a selection of an AP inside the DAP, which in turn translates it into a memory-mapped bus access to access system internal resources.
As shown in FIG. 2, each of the device TAPs 1-TAP3 has its own IR and DR widths and its own position in the JTAG chain. Assuming that the DAP to be designed is located at a position in the graph, the corresponding position is set as DAP _ offset, the widths of IR (Instruction Register) and DR (Data Register) are IR _ width and DR _ width respectively, the structural parameters, the accessed debugging object, bypass requirement and other parameters are used as target test parameters, splicing of IR and DR contents is carried out respectively, the structure of the JTAG chain can be determined, and the IR sequence and the DR sequence can be determined.
When verifying a to-be-tested design including a DAP, compiling a test case developed based on SV language generally involves compiling the whole UVM verification environment and then generating an executable file simv, so that the early verification process is long in time consumption and consumes large server resources.
The so file is used as a parameter to be transmitted to the previously generated executable file simv, so that the simulation is started, the DPI-C interface is selected to generate the C language test case, the recompilation time of the verification environment can be greatly saved, and the subsequent verification can be quickly started. Therefore, the process of generating the test excitation sequence according to the target test parameters and the test function at step S3 includes: and generating and combining a DPI-C interface method to output the test excitation sequence according to the target test parameters and the test function.
Specifically, the test function includes:
a VIP reset and reset-release function;
IR/DR load function;
TDO checking function;
basic test case functions.
Specifically, the VIP reset and reset function provides a function JTAG _ reset () for resetting and resetting the JTAG VIP, and the specific function operation process includes: instantiating an excitation sequence of a reset; the stimulus sequence is initiated. Where id represents a configuration parameter of the VIP.
Specifically, when the DAP input is effectively accessed by writing according to the JTAG protocol, a pre-specified instruction needs to be updated to the instruction register through the protocol interface input signal, and then transferred to the DAP input signal by bit, and at this time, the DAP selects the corresponding DP register by parsing the instruction. Therefore, the IR/DR load function provides the function tag _ load _ IR ()/jtag _ load _ DR (), and the specific function working process includes: inputting the width of the IR/DR chain; instantiate a sequence for loading IR/DR; setting parameters (such as IR/DR data and the like) in sequence; sequence is initiated. Where IR represents a pre-specified input instruction and IR _ CHAIN _ WIDTH represents the IR CHAIN maximum bit WIDTH.
Specifically, when it is necessary to capture the output signal (TDO) of the DAP to acquire the debug information, it is necessary to sample the TDO of JTAG _ VIP, and this sampling process may be performed in the Shift _ IR state or in the Shift _ DR state and output through JTAG VIP, the output value is compared with the expected value, and the debug information may be further analyzed according to the comparison result. Thus, the TDO checking function provides the function jtag _ check _ ir ()/jtag _ check _ dr (), the function work procedure including: inputting the width of an IR/DR chain and inputting an IR/DR instruction; setting a DR value of a desired output; instantiate a sequence to check DR; setting parameters (such as IR/DR data and the like) in sequence; comparing the DR value output currently with an expected value, and printing a comparison result; sequence is initiated.
It is understood that, after the SV task is defined in the present embodiment, a DPI link between the C language and the SV language needs to be established. All SV function interfaces are realized in SV header files, when the SV is used in a DPI-C case, the interfaces are imported into a DPI-C case side by adopting a DPI method, the SV-based C function interface can be created only by an 'export' keyword, and the general function definition is as follows:
export“DPI-C”dpi_jtag_load_ir＝task jtag_load_ir；
further, all the well-defined functions above can be encapsulated in a DPI-C library file (DPI _ lib.h) for calling and multiplexing.
Further, since the entire verification environment is built based on the UVM verification platform, a basic test case needs to be created to use the DPI-C interface. And creating a DPI test case top _ DPI _ test.sv of SV language, and communicating with the DPI-C test case my _ test.c through DPI _ C _ thread (), wherein the function is defined in the DPI-C test case and the content is customized test excitation. Thus, the basic test case function provides a function import "DPI-C" context task DPI _ C _ thread (), which creates a C-language-based SV task or function interface through an import key.
In addition, the synchronization between the DPI case and the UVM environment can be realized through writing, reading the memory, delaying and the like, and the synchronous interface function can be specifically expanded according to the requirements of verification personnel.
It can be understood that the test case is a C language test case;
correspondingly, the process of the test case for the design verification to be tested comprises the following steps: and sending a preset format file generated in the compiling process of the test case to an executable file so as to start the verification of the design to be tested.
As mentioned above, the test case based on C language does not need to recompile the entire UVM verification environment, but only needs to transmit the so file generated in the compilation process as a parameter to the previously generated executable file simv, so as to start simulation, and the preset format file is the so file, and the executable file is simv.
The application discloses a test case determining method, which comprises the following steps: receiving target test parameters; inquiring whether a test excitation sequence corresponding to the target test parameter exists in an excitation pool or not; if not, generating the test excitation sequence according to the target test parameters and the test function; and outputting the test excitation sequence to generate a test case for the design verification to be tested. According to the method and the device, the test excitation sequence is automatically output according to the target test parameters, the excitation sequence can directly generate the test case to carry out the design verification to be tested, the complicated manual configuration and flow carding are avoided, and the method and the device have the advantages of flexible multiplexing and project iteration utilization.
Correspondingly, the embodiment of the present application further discloses a test case determination system, which is shown in fig. 3 and includes:
a parameter interface 1 for receiving target test parameters;
the action module 2 is used for inquiring whether a test excitation sequence corresponding to the target test parameter exists in an excitation pool or not; if not, generating the test excitation sequence according to the target test parameters and the test function;
and the output module 3 is used for outputting the test excitation sequence to generate a test case for the design verification to be tested.
According to the method and the device, the test excitation sequence is automatically output according to the target test parameters, the excitation sequence can directly generate the test case to carry out the design verification to be tested, the complicated manual configuration and flow carding are avoided, and the method and the device have the advantages of flexible reuse and project iteration utilization.
In some specific embodiments, the process of generating the test excitation sequence according to the target test parameter and the test function by the action module 2 includes: and generating the test excitation sequence through a JTAG interface chain according to the target test parameters and the test function.
In some specific embodiments, the test stimulus sequences are specifically an IR sequence and a DR sequence.
In some specific embodiments, the design under test is a design under test that includes a DAP.
In some specific embodiments, the process of the action module 2 generating the test excitation sequence according to the target test parameter and the test function includes: and generating and combining a DPI-C interface method to output the test excitation sequence according to the target test parameters and the test function.
In some specific embodiments, the test function includes: a VIP reset and un-reset function; IR/DR load function; TDO checking function; basic test case functions.
In some specific embodiments, the test case is a C language test case; correspondingly, the process of the test case for the design verification to be tested comprises the following steps: and sending a preset format file generated in the compiling process of the test case to an executable file so as to start the verification of the design to be tested.
Correspondingly, the embodiment of the present application further discloses a device for determining test cases, which includes:
a memory for storing a computer program;
a processor for implementing the steps of the test case determination method according to any one of the above when the computer program is executed.
Correspondingly, the embodiment of the present application also discloses a readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the steps of the test case determination method according to any one of the above.
The specific content of the test case determining method in this embodiment may refer to the related description in the above embodiments, and is not described herein again.
The test case determining apparatus and the readable storage medium in this embodiment have the same technical effects as the test case determining method in the foregoing embodiment, and are not described herein again.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The method, the system and the related components for determining the test case provided by the invention are introduced in detail, specific examples are applied in the text to explain the principle and the implementation of the invention, and the description of the above embodiments is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A method for determining test cases is characterized by comprising the following steps:
receiving target test parameters;
inquiring whether a test excitation sequence corresponding to the target test parameter exists in an excitation pool or not;
if not, generating the test excitation sequence according to the target test parameters and the test function;
and outputting the test excitation sequence to generate a test case for the design verification to be tested.
2. The method for determining test cases according to claim 1, wherein the process of generating the test stimulus sequence according to the target test parameters and the test function includes: and generating the test excitation sequence through a JTAG interface chain according to the target test parameters and the test functions.
3. The test case determination method according to claim 2,
the test excitation sequence is specifically an IR sequence and a DR sequence.
4. The method for determining test cases according to claim 3, wherein the design under test is a design under test including a DAP.
5. The method for determining the test case according to any one of claims 1 to 4, wherein the process of generating the test stimulus sequence according to the target test parameters and the test function includes:
and generating and combining a DPI-C interface method to output the test excitation sequence according to the target test parameters and the test function.
6. The method for determining test cases according to claim 5, wherein the test function comprises:
a VIP reset and un-reset function;
IR/DR load function;
TDO checking function;
basic test case functions.
7. The method for determining the test case according to claim 6, wherein the test case is a C language test case;
correspondingly, the process of the test case for the design verification to be tested comprises the following steps: and sending a preset format file generated in the compiling process of the test case to an executable file so as to start the verification of the design to be tested.
8. A test case determination system, comprising:
the parameter interface is used for receiving target test parameters;
the action module is used for inquiring whether a test excitation sequence corresponding to the target test parameter exists in the excitation pool or not; if not, generating the test excitation sequence according to the target test parameters and the test function;
and the output module is used for outputting the test excitation sequence so as to generate a test case for the design verification to be tested.
9. A test case determination apparatus, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the test case determination method according to any one of claims 1 to 7 when executing the computer program.
10. A readable storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the steps of the test case determination method according to any one of claims 1 to 7.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115563019A (en) * | 2022-12-05 | 2023-01-03 | 天津哈威克科技有限公司 | UVM and C combined verification method and system |
| CN117389818A (en) * | 2023-12-12 | 2024-01-12 | 牛芯半导体(深圳)有限公司 | Verification method and device applied to UVM verification platform |
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2022
- 2022-02-25 CN CN202210182265.2A patent/CN114564394A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115563019A (en) * | 2022-12-05 | 2023-01-03 | 天津哈威克科技有限公司 | UVM and C combined verification method and system |
| CN117389818A (en) * | 2023-12-12 | 2024-01-12 | 牛芯半导体(深圳)有限公司 | Verification method and device applied to UVM verification platform |
| CN117389818B (en) * | 2023-12-12 | 2024-03-29 | 牛芯半导体(深圳)有限公司 | Verification method and device applied to UVM verification platform |
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