CN113937770A - Circuit and method for intelligent platform area topology identification - Google Patents
Circuit and method for intelligent platform area topology identification Download PDFInfo
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- CN113937770A CN113937770A CN202111306051.3A CN202111306051A CN113937770A CN 113937770 A CN113937770 A CN 113937770A CN 202111306051 A CN202111306051 A CN 202111306051A CN 113937770 A CN113937770 A CN 113937770A
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- 238000000034 method Methods 0.000 title claims abstract description 12
- 238000005070 sampling Methods 0.000 claims abstract description 48
- 238000002347 injection Methods 0.000 claims abstract description 43
- 239000007924 injection Substances 0.000 claims abstract description 43
- 230000000630 rising effect Effects 0.000 claims abstract description 16
- 230000004927 fusion Effects 0.000 claims abstract description 6
- 239000003990 capacitor Substances 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 abstract description 6
- 238000004128 high performance liquid chromatography Methods 0.000 abstract 1
- 239000000243 solution Substances 0.000 description 5
- 230000002238 attenuated effect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000007306 turnover Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
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- 230000000750 progressive effect Effects 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J2203/00—Indexing scheme relating to details of circuit arrangements for AC mains or AC distribution networks
- H02J2203/10—Power transmission or distribution systems management focussing at grid-level, e.g. load flow analysis, node profile computation, meshed network optimisation, active network management or spinning reserve management
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S10/00—Systems supporting electrical power generation, transmission or distribution
- Y04S10/16—Electric power substations
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Abstract
The invention discloses a circuit and a method for identifying intelligent distribution area topology, which are electrically connected with an MCU (microprogrammed control unit) and comprise the following steps: the device comprises an alternating voltage sampling comparison circuit, a current pulse signal injection circuit and a current pulse signal capturing and converting circuit; the alternating voltage sampling comparison circuit and the current pulse signal injection circuit are both electrically connected with the MCU; the current pulse signal capturing and converting circuit is respectively electrically connected with the current pulse signal injection circuit and the MCU; the alternating voltage sampling comparison circuit can output a rising edge signal allowing pulse current injection, the current pulse signal injection circuit can generate a reliable current pulse waveform and the current pulse signal capture circuit converts the pulse width of an output signal to be processed by the MCU, and the data are collected to the platform region fusion terminal through HPLC to generate an upper and lower level topological relation diagram of equipment at the lower end of the platform region.
Description
Technical Field
The invention relates to the technical field of intelligent power grids, in particular to a circuit and a method for identifying intelligent platform area topology.
Background
With the development of the smart power grid, obtaining an accurate topological relation under a low-voltage transformer area becomes the foundation of smart power grid construction. Especially, in some transformer areas, the devices are multiple, the wiring is complex, the topological relation of the upper and lower layers is disordered, and certain management difficulty is caused to engineering teams. And the lean management such as accurate calculation of line loss, three-phase imbalance management, electricity stealing prevention, quick fault position positioning and the like of the transformer area can be better carried out only by accurately mastering the topological hierarchical relationship of the transformer area. At present, no stable and reliable technical scheme is available for realizing the detection of the upper and lower hierarchical relation of the topology, and the circuit and the method for identifying the topology of the intelligent transformer area are generated under the condition.
Therefore, it is an urgent need to solve the problem of the art to provide a circuit and a method for intelligent cell topology identification with high stability and precise cell management.
Disclosure of Invention
In view of this, the present invention provides a circuit and a method for identifying an intelligent platform area topology, which inject current pulses into the platform area through each device, and transmit the decoded pulse conversion signals to a fusion terminal to generate a topology relationship diagram of an upper layer and a lower layer, so as to achieve the purpose of accurately managing the platform area.
In order to achieve the purpose, the invention adopts the following technical scheme:
a circuit for intelligent cell topology identification, electrically connected to an MCU, comprising: the device comprises an alternating voltage sampling comparison circuit, a current pulse signal injection circuit and a current pulse signal capturing and converting circuit;
the alternating voltage sampling comparison circuit and the current pulse signal injection circuit are both electrically connected with the MCU; the current pulse signal capturing and converting circuit is electrically connected with the current pulse signal injection circuit and the MCU respectively;
the alternating-current voltage sampling comparison circuit sequentially comprises a voltage transformer PT1, an operational amplifier U1 and a voltage comparator U2, wherein the primary side of the voltage transformer PT1 is connected with a primary side sampling resistor R1, the secondary side of the voltage transformer PT1 is connected with a secondary side sampling resistor R3, the other end of the primary side sampling resistor R1 is connected to any phase line of ABC of alternating current, the secondary side sampling resistor R3 is grounded, and the output end of the voltage comparator U2 is electrically connected with the MCU;
the current pulse signal injection circuit sequentially comprises a unidirectional silicon controlled rectifier Q1, a photoelectric silicon controlled rectifier optocoupler U7 and a triode Q2, wherein the unidirectional silicon controlled rectifier Q1 is further connected with a power inductor L1, the other end of the power inductor L1 is connected to an ABC phase node of alternating current, and the triode Q2 is electrically connected with the MCU through a resistor R22;
the current pulse signal capturing and converting circuit sequentially comprises a straight-through current transformer CT1, a current converting circuit and a comparator U6, wherein the straight-through current transformer CT1 is sleeved on a cable in front of a switch node of a phase connected with the alternating voltage sampling and comparing circuit, and the output end of the comparator U6 is electrically connected with the MCU.
Preferably, the ac voltage sampling comparison circuit further includes: a resistor R2, a resistor R4 and a resistor R5;
one end of the primary side sampling resistor R1 is connected with any phase line ABC of alternating current, the other end of the resistor R1 is connected to the 2 nd pin of the voltage transformer PT1, the 1 st pin of the voltage transformer PT1 is connected to the N phase line of alternating current voltage, the 3 rd pin of the voltage transformer PT1 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the 4 th pin of the voltage transformer PT1 and grounded;
one end of the resistor R2 is connected with the 3 rd pin of the potential transformer PT1, and the other end of the resistor R2 is connected with the 3 rd pin of the operational amplifier U1; the 4 th pin of the operational amplifier U1 is connected to the ground through the resistor R5, the 4 th pin of the operational amplifier U1 is also connected to one end of the resistor R4, the other end of the resistor R4 is connected to the 1 st pin of the operational amplifier U1, and the 1 st pin of the operational amplifier U1 is connected to the 4 th pin of the voltage comparator U2;
the 3 rd pin of the voltage comparator U2 is connected with a reference voltage Vref _1, and the 1 st pin of the voltage comparator U2 is connected with the IO pin of the MCU.
Preferably, the current pulse signal injection circuit further includes: a current limiting resistor R21, a resistor R19 and a resistor R20;
one end of the power inductor L1 is connected with an ABC phase node of alternating current, and the other end of the power inductor L1 is connected with a No. 2 pin of the unidirectional thyristor Q1 and a No. 6 pin of the photo-thyristor optocoupler U7;
one end of the resistor R21 is connected with the 4 th pin of the photo-thyristor optocoupler U7, the other end of the resistor R21 is connected with the 3 rd pin of the unidirectional thyristor Q1, and the 1 st pin of the unidirectional thyristor Q1 is connected with an N-phase line of alternating current;
the 1 st pin of photothyristor opto-coupler U7 is connected resistance R19, resistance R19 another termination power VCC, the 2 nd pin of photothyristor opto-coupler U7 is connected to resistance R20, another termination power VCC of resistance R20, the 2 nd pin of photothyristor opto-coupler U7 still is connected to triode Q2's collecting electrode, triode Q2's projecting pole ground connection, triode Q2's base connects to resistance R22's one end, the other end of resistance R22 is connected to MCU's IO pin.
Preferably, the current pulse signal capturing and converting circuit further includes: the current sampling resistor R10, resistance R7 and resistance R12, the current conversion circuit includes specifically: the circuit comprises an operational amplifier U3, an operational amplifier U4, an operational amplifier U5, a resistor R14, a resistor R8, a resistor R9, a resistor R15, a resistor R17, a capacitor C1, a capacitor C2, a resistor R6, a resistor R13, a resistor R16, a resistor R18, a resistor R11 and a capacitor C3;
a 2 nd pin of the feedthrough current transformer CT1 is connected to the resistor R10, the other end of the resistor R10 is connected to a 1 st pin of the feedthrough current transformer CT1 and grounded, one end of the resistor R7 is connected to a 2 nd pin of the feedthrough current transformer CT1, and the other end of the resistor R7 is connected to a 3 rd pin of the operational amplifier U3;
the 4 th pin of the operational amplifier U3 is connected to the resistor R12, the other end of the resistor R12 is grounded, the 4 th pin of the operational amplifier U3 is further connected to the resistor R14, the other end of the resistor R14 is connected to the 1 st pin of the operational amplifier U3, the 1 st pin of the operational amplifier U3 is further connected to the resistor R9, the other end of the resistor R9 is connected to the 3 rd pin of the operational amplifier U4, the 3 rd pin of the operational amplifier U4 is further connected to the resistor R8, the other end of the resistor R8 is connected to the power Vbias, the 4 th pin of the operational amplifier U4 is connected to the resistor R17, the other end of the resistor R17 is grounded, the 4 th pin of the operational amplifier U4 is further connected to the resistor R15, the other end of the resistor R15 is connected to the 1 st pin of the operational amplifier U4, the 1 st pin of the operational amplifier U4 is further connected to the capacitor C1, the other end of a capacitor C1 is connected with the capacitor C2 and the resistor R6, the other end of the capacitor C2 is connected with a pin 3 of the operational amplifier U5, the other end of the resistor R6 is connected with a pin 1 of the operational amplifier U5, a pin 3 of the operational amplifier U5 is connected with the resistor R13, the other end of the resistor R13 is grounded, a pin 4 of the operational amplifier U5 is connected with the resistor R18 and the resistor R16 at any time, the other end of the resistor R18 is grounded, the other end of the resistor R16 is connected with a pin 1 of the operational amplifier U5, and a pin 1 of the operational amplifier U5 is connected with the resistor R11;
the other end of the resistor R11 is connected with the capacitor C3 and the 3 rd pin of the comparator U6, the other end of the capacitor C3 is grounded, the 4 th pin of the comparator U6 is connected with a power supply Vref _2, and the 1 st pin of the comparator U6 is connected with the IO pin of the MCU.
Preferably, the 5 th pins of the operational amplifiers U1, U2, U3, U4, U5 and U6 are all connected to a power supply VCC, the 2 nd pins of the operational amplifiers U1, U2, U4, U5 and U6 are all connected to a signal ground GND, and the 2 nd pin of the operational amplifier U3 is connected to a power supply negative power supply-VCC.
When an injection command is received, the alternating voltage sampling comparison circuit outputs a signal1 signal rising edge to the MCU before the zero crossing point, and a signal1 signal rising edge is used as the judgment of an alternating current period; the next period is the arrival of the rising edge of the signal1, the injection current pulse signal detected in the period is bit1, the injection current pulse signal not detected in the period is bit0, and coding injection is carried out;
when the alternating voltage sampling comparison circuit outputs a rising edge to the MCU, the MCU immediately sets a signal2 pin within a time length range of 50uS-1mS and then pulls down the signal2 pin, the time can be set based on starting parameters of the unidirectional silicon controlled rectifier, the unidirectional silicon controlled rectifier can automatically stop at a zero crossing point, the alternating voltage sampling comparison circuit can receive a short-time current pulse signal superposed on power frequency current at the moment of pulling up the signal, and the current pulse signal appears at a positive half-wave zero crossing point and automatically returns to zero when the current pulse signal crosses zero;
the current pulse signal capturing and converting circuit acquires the current pulse signal, converts the injected current pulse signal into a square wave pulse width and sends the square wave pulse width to the MCU, the MCU decodes and checks the square wave pulse width to obtain effective data, the effective data is sent to the fusion terminal, and finally a topological relation graph is generated.
Preferably, signal2 pin is kept low at all times when the injection of the current pulse signal is not required.
According to the technical scheme, compared with the prior art, the circuit and the method for identifying the intelligent distribution area topology are disclosed, the alternating voltage sampling comparison circuit accurately identifies a proper time, the rising edge signal is output to inform the MCU, the MCU drives the current pulse signal injection circuit to generate short-time pulse current between the alternating voltage phase line loops, and the current pulse signal capture and conversion circuit can filter the signal and then output a characteristic pulse width sequence to be decoded and identified by the MCU. The three circuit modules are electrically isolated, and the safety is improved. The current pulse signal injection circuit adopts the unidirectional silicon controlled rectifier to carry out current injection, only needs to drive the current pulse signal injection circuit before the zero crossing point, and the unidirectional silicon controlled rectifier can be automatically cut off at the zero crossing point after being switched on, and MCU intervention is not needed, thereby improving the reliability of products. Through verification, the technical scheme can accurately realize the characteristic current signal injection and detection. The equipment is arranged at each switch node under the transformer area, so that the upper and lower hierarchical relations of each node can be effectively cleared, and the purpose of effectively managing each node under the transformer area is achieved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic diagram of an overall structure of a circuit for identifying topology of an intelligent distribution room according to the present invention;
fig. 2 is a schematic diagram of an ac voltage sampling comparison circuit in a circuit for identifying topology of an intelligent distribution room according to the present invention;
FIG. 3 is a schematic diagram of a current pulse signal injection circuit in a circuit for identifying topology of an intelligent distribution room according to the present invention;
fig. 4 is a schematic structural diagram of a current pulse signal capturing and converting circuit in a circuit for identifying intelligent platform zone topology provided by the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses a circuit for identifying intelligent distribution area topology, which is electrically connected with an MCU (microprogrammed control unit), as shown in figure 1, and comprises the following components: the device comprises an alternating voltage sampling comparison circuit, a current pulse signal injection circuit and a current pulse signal capturing and converting circuit;
the alternating voltage sampling comparison circuit and the current pulse signal injection circuit are both electrically connected with the MCU; the current pulse signal capturing and converting circuit is respectively electrically connected with the current pulse signal injection circuit and the MCU;
the alternating-current voltage sampling comparison circuit sequentially comprises a voltage transformer PT1, an operational amplifier U1 and a voltage comparator U2, wherein the primary side of the voltage transformer PT1 is connected with a primary side sampling resistor R1, the secondary side of the voltage transformer PT1 is connected with a secondary side sampling resistor R3, the other end of the primary side sampling resistor R1 is connected to any phase of alternating current ABC, the secondary side sampling resistor R3 is grounded, and the output end of the voltage comparator U2 is electrically connected with an MCU;
the current pulse signal injection circuit sequentially comprises a unidirectional silicon controlled rectifier Q1, a photoelectric silicon controlled rectifier optocoupler U7 and a triode Q2, wherein the unidirectional silicon controlled rectifier Q1 is further connected with a power inductor L1, the other end of the power inductor L1 is connected to an ABC phase node of alternating current, and the triode Q2 is electrically connected with the MCU through a resistor R22;
the current pulse signal capturing and converting circuit sequentially comprises a straight-through current transformer CT1, a current converting circuit and a comparator U6, wherein the straight-through current transformer CT1 is sleeved on a cable in front of a switch node of a phase connected with the alternating voltage sampling and comparing circuit, and the output end of the comparator U6 is electrically connected with the MCU.
In order to further implement the above technical solution, as shown in fig. 2, the ac voltage sampling comparison circuit further includes: a resistor R2, a resistor R4 and a resistor R5;
one end of a primary side sampling resistor R1 is connected with any phase line ABC of alternating current, the other end of the resistor R1 is connected with a 2 nd pin of a voltage transformer PT1, a 1 st pin of the voltage transformer PT1 is connected with an N phase line of alternating current voltage, a 3 rd pin of the voltage transformer PT1 is connected with one end of a resistor R3, and the other end of the resistor R3 is connected with a 4 th pin of the voltage transformer PT1 and is grounded;
one end of the resistor R2 is connected with the 3 rd pin of the potential transformer PT1, and the other end of the resistor R2 is connected with the 3 rd pin of the operational amplifier U1; the 4 th pin of the operational amplifier U1 is connected to the ground through a resistor R5, the 4 th pin of the operational amplifier U1 is further connected to one end of a resistor R4, the other end of the resistor R4 is connected to the 1 st pin of the operational amplifier U1, and the 1 st pin of the operational amplifier U1 is connected to the 4 th pin of a voltage comparator U2;
the 3 rd pin of the voltage comparator U2 is connected to the reference voltage Vref _1, and the 1 st pin of the voltage comparator U2 has its output connected to the IO pin of the MCU.
In order to further implement the above technical solution, as shown in fig. 3, the current pulse signal injection circuit further includes: a current limiting resistor R21, a resistor R19 and a resistor R20;
one end of a power inductor L1 is connected with an ABC phase node of alternating current, and the other end of the power inductor L1 is connected with a No. 2 pin of a one-way thyristor Q1 and a No. 6 pin of a photo-thyristor optocoupler U7;
one end of the resistor R21 is connected with the 4 th pin of the photoelectric thyristor optocoupler U7, the other end of the resistor R21 is connected with the 3 rd pin of the unidirectional thyristor Q1, and the 1 st pin of the unidirectional thyristor Q1 is connected with an N phase line of alternating current;
the 1 st pin connecting resistance R19 of photothyristor opto-coupler U7, another termination power VCC of resistance R19, the 2 nd pin of photothyristor opto-coupler U7 is connected to resistance R20, another termination power VCC of resistance R20, the 2 nd pin of photothyristor opto-coupler U7 still is connected to triode Q2's collecting electrode, triode Q2's emitter ground, triode Q2's base connects to resistance R22's one end, resistance R22's the other end is connected to MCU's IO pin.
In order to further implement the above technical solution, as shown in fig. 4, the current pulse signal capturing and converting circuit further includes: current sampling resistance R10, resistance R7 and resistance R12, the current conversion circuit specifically includes: the circuit comprises an operational amplifier U3, an operational amplifier U4, an operational amplifier U5, a resistor R14, a resistor R8, a resistor R9, a resistor R15, a resistor R17, a capacitor C1, a capacitor C2, a resistor R6, a resistor R13, a resistor R16, a resistor R18, a resistor R11 and a capacitor C3;
a 2 nd pin of the straight-through current transformer CT1 is connected with a resistor R10, the other end of the resistor R10 is connected with a 1 st pin of the straight-through current transformer CT1 and is grounded, one end of the resistor R7 is connected with a 2 nd pin of the straight-through current transformer CT1, and the other end of the resistor R7 is connected with a 3 rd pin of an operational amplifier U3;
the 4 th pin of the operational amplifier U3 is connected to the resistor R12, the other end of the resistor R12 is connected to ground, the 4 th pin of the operational amplifier U3 is further connected to the resistor R14, the other end of the resistor R14 is connected to the 1 st pin of the operational amplifier U3, the 1 st pin of the operational amplifier U3 is further connected to the resistor R9, the other end of the resistor R9 is connected to the 3 rd pin of the operational amplifier U9, the 3 rd pin of the operational amplifier U9 is further connected to the resistor R9, the other end of the resistor R9 is connected to the power Vbias, the 4 th pin of the operational amplifier U9 is connected to the resistor R9, the other end of the resistor R9 is connected to ground, the 4 th pin of the operational amplifier U9 is further connected to the resistor R9, the other end of the resistor R9 is connected to the 1 st pin of the operational amplifier U9, the 1 st pin of the operational amplifier U9 is further connected to the capacitor C9, the other end of the capacitor C9 is connected to the first pin of the operational amplifier U9, the 3 rd pin of the operational amplifier U5 is connected to the resistor R13, the other end of the resistor R13 is grounded, the 4 th pin of the operational amplifier U5 is connected to the random resistor R18 and the resistor R16, the other end of the resistor R18 is grounded, the other end of the resistor R16 is connected to the 1 st pin of the operational amplifier U5, and the 1 st pin of the operational amplifier U5 is connected to the resistor R11;
the other end of the resistor R11 is connected with a pin 3 of the capacitor C3 and the comparator U6, the other end of the capacitor C3 is grounded, a pin 4 of the comparator U6 is connected with a power supply Vref _2, and a pin 1 of the comparator U6 is connected to an IO pin of the MCU.
In order to further implement the technical scheme, the 5 th pins of the operational amplifiers U1, U2, U3, U4, U5 and U6 are all connected with a power supply VCC, the 2 nd pins of the operational amplifiers U1, U2, U4, U5 and U6 are all connected with a signal ground GND, and the 2 nd pin of the operational amplifier U3 is connected with a power supply negative VCC.
It should be noted that:
in the invention, the alternating current voltage sampling comparison circuit acquires alternating current through the primary side of the voltage transformer, the secondary side of the voltage transformer acquires an alternating current isolation small signal, a rising edge signal of one level turnover is output at the zero crossing point of each cycle voltage through the comparator, and a signal of the zero crossing point is acquired through the rising edge of the level turnover.
The current pulse signal injection circuit is driven and injected based on a rising edge signal output by the alternating voltage sampling comparison circuit, a photoelectric silicon controlled rectifier optical coupler is adopted to realize drive signal isolation, when the MCU sends a current pulse signal, the power unidirectional silicon controlled rectifier at the alternating current end is driven to be conducted, a power inductor is connected to two ends of alternating current to form an instantaneous pulse current, and the current is continuously recovered to 0 when the alternating current crosses zero.
The current pulse signal capturing and converting circuit is used for obtaining instantaneous pulse current formed by a current pulse signal injection circuit, after the current is obtained through a current transformer, 50HZ alternating current is attenuated through a high-pass filter, the instantaneous pulse current signal cannot be attenuated, the instantaneous pulse current signal outputs pulse square waves through a comparator, a square wave signal is converted to be output when an instantaneous pulse current signal is not obtained, and the square wave signal is processed through an MCU to obtain information.
When equipment receives an injection command sent by a fusion terminal, firstly, an alternating voltage sampling and comparing circuit outputs a signal1 signal rising edge to an MCU (microprogrammed control Unit) before approaching a zero crossing point, the signal is used as the judgment of an alternating current period, and the injection current needs to drive a current pulse signal injection circuit; the next period is the next period when the rising edge of the signal1 comes, coding is carried out according to a specific Bit, the injection current signal detected in the period is Bit1, and the injection current signal not detected in the period is Bit0, and coding injection is carried out;
when the alternating voltage sampling comparison circuit outputs a rising edge to the MCU, the MCU immediately sets a signal2 pin within a time length range of 50uS-1mS and then pulls down the signal2 pin, the time can be set based on a starting parameter of the unidirectional silicon controlled rectifier, the unidirectional silicon controlled rectifier can automatically stop at a zero crossing point, the alternating voltage sampling comparison circuit can receive a short-time current pulse signal superposed on power frequency current at the moment of pulling up the signal, the current pulse signal can appear at a positive half-wave zero crossing point and automatically returns to zero at the zero crossing point without the intervention of the MCU;
other intelligent equipment can acquire signals according to the current pulse signal capturing and converting circuit, the current pulse signal capturing and converting circuit can convert the injected current signal into a square wave pulse width and send the square wave pulse width to the MCU, effective data can be acquired through decoding and checking of the MCU, and the data are sent to the fusion terminal one by one to finally generate a topological relation graph.
In order to further implement the technical scheme, when the current pulse signal is not required to be injected, the pin of the signal2 is kept at a low level all the time.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (7)
1. A circuit for intelligent platform district topology identification, is connected with MCU electricity, its characterized in that includes: the device comprises an alternating voltage sampling comparison circuit, a current pulse signal injection circuit and a current pulse signal capturing and converting circuit;
the alternating voltage sampling comparison circuit and the current pulse signal injection circuit are both electrically connected with the MCU; the current pulse signal capturing and converting circuit is electrically connected with the current pulse signal injection circuit and the MCU respectively;
the alternating-current voltage sampling comparison circuit sequentially comprises a voltage transformer PT1, an operational amplifier U1 and a voltage comparator U2, wherein the primary side of the voltage transformer PT1 is connected with a primary side sampling resistor R1, the secondary side of the voltage transformer PT1 is connected with a secondary side sampling resistor R3, the other end of the primary side sampling resistor R1 is connected to any phase of alternating current ABC, the secondary side sampling resistor R3 is grounded, and the output end of the voltage comparator U2 is electrically connected with the MCU;
the current pulse signal injection circuit sequentially comprises a unidirectional silicon controlled rectifier Q1, a photoelectric silicon controlled rectifier optocoupler U7 and a triode Q2, wherein the unidirectional silicon controlled rectifier Q1 is further connected with a power inductor L1, the other end of the power inductor L1 is connected to an ABC phase node of alternating current, and the triode Q2 is electrically connected with the MCU through a resistor R22;
the current pulse signal capturing and converting circuit sequentially comprises a straight-through current transformer CT1, a current converting circuit and a comparator U6, wherein the straight-through current transformer CT1 is sleeved on a cable in front of a switch node of a phase connected with the alternating voltage sampling and comparing circuit, and the output end of the comparator U6 is electrically connected with the MCU.
2. The circuit for intelligent district topology identification as recited in claim 1, wherein said ac voltage sample comparison circuit further comprises: a resistor R2, a resistor R4 and a resistor R5;
one end of the primary side sampling resistor R1 is connected with any phase line ABC of alternating current, the other end of the resistor R1 is connected to the 2 nd pin of the voltage transformer PT1, the 1 st pin of the voltage transformer PT1 is connected to the N phase line of alternating current voltage, the 3 rd pin of the voltage transformer PT1 is connected to one end of the resistor R3, and the other end of the resistor R3 is connected to the 4 th pin of the voltage transformer PT1 and grounded;
one end of the resistor R2 is connected with the 3 rd pin of the potential transformer PT1, and the other end of the resistor R2 is connected with the 3 rd pin of the operational amplifier U1; the 4 th pin of the operational amplifier U1 is connected to the ground through the resistor R5, the 4 th pin of the operational amplifier U1 is also connected to one end of the resistor R4, the other end of the resistor R4 is connected to the 1 st pin of the operational amplifier U1, and the 1 st pin of the operational amplifier U1 is connected to the 4 th pin of the voltage comparator U2;
the 3 rd pin of the voltage comparator U2 is connected with a reference voltage Vref _1, and the 1 st pin of the voltage comparator U2 is connected with the IO pin of the MCU.
3. The circuit for intelligent cell topology identification as recited in claim 1, wherein said current pulse signal injection circuit further comprises: a current limiting resistor R21, a resistor R19 and a resistor R20;
one end of the power inductor L1 is connected with an ABC phase node of alternating current, and the other end of the power inductor L1 is connected with a No. 2 pin of the unidirectional thyristor Q1 and a No. 6 pin of the photo-thyristor optocoupler U7;
one end of the resistor R21 is connected with the 4 th pin of the photo-thyristor optocoupler U7, the other end of the resistor R21 is connected with the 3 rd pin of the unidirectional thyristor Q1, and the 1 st pin of the unidirectional thyristor Q1 is connected with an N-phase line of alternating current;
the 1 st pin of photothyristor opto-coupler U7 is connected resistance R19, resistance R19 another termination power VCC, the 2 nd pin of photothyristor opto-coupler U7 is connected to resistance R20, another termination power VCC of resistance R20, the 2 nd pin of photothyristor opto-coupler U7 still is connected to triode Q2's collecting electrode, triode Q2's projecting pole ground connection, triode Q2's base connects to resistance R22's one end, the other end of resistance R22 is connected to MCU's IO pin.
4. The circuit for intelligent station area topology identification as recited in claim 1, wherein said current pulse signal capture conversion circuit further comprises: the current sampling resistor R10, resistance R7 and resistance R12, the current conversion circuit includes specifically: the circuit comprises an operational amplifier U3, an operational amplifier U4, an operational amplifier U5, a resistor R14, a resistor R8, a resistor R9, a resistor R15, a resistor R17, a capacitor C1, a capacitor C2, a resistor R6, a resistor R13, a resistor R16, a resistor R18, a resistor R11 and a capacitor C3;
a 2 nd pin of the feedthrough current transformer CT1 is connected to the resistor R10, the other end of the resistor R10 is connected to a 1 st pin of the feedthrough current transformer CT1 and grounded, one end of the resistor R7 is connected to a 2 nd pin of the feedthrough current transformer CT1, and the other end of the resistor R7 is connected to a 3 rd pin of the operational amplifier U3;
the 4 th pin of the operational amplifier U3 is connected to the resistor R12, the other end of the resistor R12 is grounded, the 4 th pin of the operational amplifier U3 is further connected to the resistor R14, the other end of the resistor R14 is connected to the 1 st pin of the operational amplifier U3, the 1 st pin of the operational amplifier U3 is further connected to the resistor R9, the other end of the resistor R9 is connected to the 3 rd pin of the operational amplifier U4, the 3 rd pin of the operational amplifier U4 is further connected to the resistor R8, the other end of the resistor R8 is connected to the power Vbias, the 4 th pin of the operational amplifier U4 is connected to the resistor R17, the other end of the resistor R17 is grounded, the 4 th pin of the operational amplifier U4 is further connected to the resistor R15, the other end of the resistor R15 is connected to the 1 st pin of the operational amplifier U4, the 1 st pin of the operational amplifier U4 is further connected to the capacitor C1, the other end of a capacitor C1 is connected with the capacitor C2 and the resistor R6, the other end of the capacitor C2 is connected with a pin 3 of the operational amplifier U5, the other end of the resistor R6 is connected with a pin 1 of the operational amplifier U5, a pin 3 of the operational amplifier U5 is connected with the resistor R13, the other end of the resistor R13 is grounded, a pin 4 of the operational amplifier U5 is connected with the resistor R18 and the resistor R16 at any time, the other end of the resistor R18 is grounded, the other end of the resistor R16 is connected with a pin 1 of the operational amplifier U5, and a pin 1 of the operational amplifier U5 is connected with the resistor R11;
the other end of the resistor R11 is connected with the capacitor C3 and the 3 rd pin of the comparator U6, the other end of the capacitor C3 is grounded, the 4 th pin of the comparator U6 is connected with a power supply Vref _2, and the 1 st pin of the comparator U6 is connected with the IO pin of the MCU.
5. The circuit for intelligent station topology identification of claim X, wherein the 5 th pins of the operational amplifiers U1, U2, U3, U4, U5 and U6 are all connected with a power supply VCC, the 2 nd pins of the operational amplifiers U1, U2, U4, U5 and U6 are all connected with a signal ground GND, and the 2 nd pin of the operational amplifier U3 is connected with a power supply negative power supply VCC.
6. A method for intelligent district topology identification, based on a circuit for intelligent district topology identification according to any of claims 1-5,
when an injection command is received, the alternating voltage sampling comparison circuit outputs a signal1 signal rising edge to the MCU before the zero crossing point, and the signal1 signal rising edge is used as the judgment of an alternating current period; the next period is the arrival of the rising edge of the signal1, the injection current pulse signal detected in the period is bit1, the injection current pulse signal not detected in the period is bit0, and coding injection is carried out;
when the alternating voltage sampling comparison circuit outputs a rising edge to the MCU, the MCU immediately pulls a signal2 pin up for 50uS-1mS within a time range and then pulls down, the time can be set based on the starting parameter of the unidirectional silicon controlled rectifier, the unidirectional silicon controlled rectifier can automatically stop at a zero crossing point, the alternating voltage sampling comparison circuit can receive a short-time current pulse signal superposed on power frequency current at the moment of pulling up, and the current pulse signal appears at a positive half-wave zero crossing point and automatically returns to zero at the zero crossing point;
the current pulse signal capturing and converting circuit acquires the current pulse signal, converts the injected current pulse signal into a square wave pulse width and sends the square wave pulse width to the MCU, the MCU decodes and checks the square wave pulse width to obtain effective data, the effective data is sent to the fusion terminal, and finally a topological relation graph is generated.
7. The method of claim 6, wherein signal2 pin is kept low at all times when no current pulse signal is injected.
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