CN113937743B - Impact current suppression circuit - Google Patents
Impact current suppression circuit Download PDFInfo
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- CN113937743B CN113937743B CN202111210526.9A CN202111210526A CN113937743B CN 113937743 B CN113937743 B CN 113937743B CN 202111210526 A CN202111210526 A CN 202111210526A CN 113937743 B CN113937743 B CN 113937743B
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- 238000006243 chemical reaction Methods 0.000 claims description 21
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- 238000010586 diagram Methods 0.000 description 10
- 238000004088 simulation Methods 0.000 description 5
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/005—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection avoiding undesired transient conditions
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Abstract
The invention discloses an impulse current suppression circuit. The rush current suppression circuit includes: the switching device comprises a switching module, a current limiting module and a switching control module. The switch module is used for responding to the signal of the control end to turn on or off; the input end of the current limiting module is electrically connected with the first end of the power supply, and the output end of the current limiting module is electrically connected with the second end of the switch module; the first input end of the switch control module is connected with a delay power supply signal, the second input end of the switch control module is electrically connected with the output end of the current limiting module, the third input end of the switch control module is electrically connected with the second end of the power supply, and the output end of the switch control module is electrically connected with the control end of the switch module; the equivalent impedance of the switch module when being conducted is smaller than that of the current limiting module; and in the preset time after the power supply is electrified, the delay power supply signal does not reach the preset voltage, and the switch control module responds to the delay power supply signal to control the switch module to be disconnected, so that the power supply supplies power to the rear-stage circuit through the current limiting module. The invention can effectively inhibit the impact current generated when the power supply is electrified.
Description
Technical Field
The embodiment of the invention relates to the technical field of circuits, in particular to an impact current suppression circuit.
Background
At present, the piezoelectric power of electric equipment such as vehicle-mounted products is usually supplied by an external power supply such as a battery, and the impact current is inevitably generated at the moment of starting the products when the power supply is electrified; due to the internal resistance of a power supply and other reasons, the larger impact current can lead to the drop of the power supply voltage, and the normal work of the product is affected. Therefore, how to effectively suppress the impact current during the start-up of the product is a problem to be solved by those skilled in the art.
Disclosure of Invention
The embodiment of the invention provides an impact current suppression circuit which is used for effectively suppressing impact current generated when a power supply is electrified.
The embodiment of the invention provides an impact current suppression circuit. The rush current suppression circuit includes:
The switch module comprises a control end, a first end and a second end; the first end of the switch module is electrically connected with the first end of the power supply, and the second end of the switch module is electrically connected with the rear-stage circuit; the switch module is used for responding to the signal of the control end to turn on or off;
The current limiting module comprises an input end and an output end; the input end of the current limiting module is electrically connected with the first end of the power supply, and the output end of the current limiting module is electrically connected with the second end of the switch module;
The switch control module comprises a first input end, a second input end, a third input end and an output end; the first input end of the switch control module is connected with a delay power supply signal, the second input end of the switch control module is electrically connected with the output end of the current limiting module, the third input end of the switch control module is electrically connected with the second end of the power supply, and the output end of the switch control module is electrically connected with the control end of the switch module;
Wherein, the equivalent impedance of the switch module when being conducted is smaller than that of the current limiting module; and in the preset time after the power supply is electrified, the delay power supply signal does not reach the preset voltage, and the switch control module is used for responding to the delay power supply signal to control the switch module to be disconnected so that the power supply supplies power to the rear-stage circuit through the current limiting module.
Optionally, the rush current suppression circuit further includes: the power conversion module comprises an input end and an output end; the input end of the power conversion module is electrically connected with the first end of the power supply, and the output end of the power conversion module is electrically connected with the first input end of the switch control module; the power conversion module is used for converting the power signal output by the power supply into the time delay power signal.
Optionally, the switch module includes: a first transistor; the control electrode of the first transistor is used as the control end of the switch module, the first electrode of the first transistor is used as the first end of the switch module, and the second electrode of the first transistor is used as the second end of the switch module.
Optionally, the current limiting module includes: a current limiting resistor; the first end of the current limiting resistor is used as the first end of the current limiting module, and the second end of the current limiting resistor is used as the second end of the current limiting module.
Optionally, the current limiting module further comprises: a diode; the first pole of the diode is used as the first end of the current limiting module, and the second pole of the diode is electrically connected with the first end of the current limiting resistor.
Optionally, the switch control module includes:
the voltage setting unit comprises a first input end, a second input end and an output end; the first input end of the voltage setting unit is connected with the delay power supply signal, and the second input end of the voltage setting unit is electrically connected with the second end of the power supply; the voltage setting unit is used for setting the preset voltage;
the control unit comprises a first input end, a second input end, a third input end and an output end; the first input end of the control unit is electrically connected with the output end of the voltage setting unit, the second input end of the control unit is electrically connected with the output end of the current limiting module, and the third input end of the control unit is electrically connected with the second end of the power supply; the control unit is used for controlling the control unit to output a signal of a first end of the power supply or a signal of a second end of the power supply according to the output signal of the voltage setting unit;
the first output unit comprises a first input end, a second input end and an output end; the first input end of the first output unit is electrically connected with the output end of the control unit, the second input end of the first output unit is electrically connected with the second end of the power supply, and the output end of the first output unit is electrically connected with the control end of the switch module; the first output unit is used for being conducted when the control unit outputs a signal of a first end of the power supply and outputting a signal of a second end of the power supply;
The second output unit comprises an input end and an output end; the input end of the second output unit is connected with the delay power supply signal, and the output end of the second output unit is electrically connected with the control end of the switch module; the second output unit is used for outputting the delay power supply signal.
Optionally, the voltage setting unit includes: a first zener diode and a first resistor; a first pole of the first zener diode is used as a first input end of the voltage setting unit; the second pole of the first zener diode is electrically connected with the first end of the first resistor and is used as the output end of the voltage setting unit; the second end of the first resistor is used as a second input end of the voltage setting unit;
Or the voltage setting unit includes: the second voltage stabilizing diode, the second resistor and the third resistor; the first end of the second resistor is used as a first input end of the voltage setting unit; the second end of the second resistor is electrically connected with the first pole of the second zener diode and is used as the output end of the voltage setting unit; the second pole of the second zener diode is electrically connected with the first end of the third resistor; the second end of the third resistor is used as a second input end of the voltage setting unit.
Optionally, the control unit includes: a second transistor and a fourth resistor; the control electrode of the second transistor is used as a first input end of the control unit; the first electrode of the second transistor is electrically connected with the second end of the fourth resistor and is used as an output end of the control unit; a second pole of the second transistor is used as a third input end of the control unit; the first end of the fourth resistor is used as a second input end of the control unit.
Optionally, the first output unit includes: a third transistor; the control electrode of the third transistor is used as a first input end of the first output unit, the first electrode of the third transistor is used as an output end of the first output unit, and the second electrode of the third transistor is used as a second input end of the first output unit.
Optionally, the second output unit includes: a fifth resistor; the first end of the fifth resistor is used as the input end of the second output unit, and the second end of the fifth resistor is used as the output end of the second output unit.
The surge current suppression circuit provided by the embodiment of the invention is provided with a switch module, a current limiting module and a switch control module; the following procedure may be implemented: in the preset time after the power supply is electrified, the delay power supply signal does not reach the preset voltage, and the switch control module controls the switch module to be reliably turned off, so that the power supply signal provided by the power supply can only be transmitted through the current limiting module with larger impedance, and the influence of the impact current is effectively reduced; after the delay power supply signal reaches the preset voltage, the switch control module controls the switch module to be conducted, so that the power supply signal is transmitted through the switch module with smaller impedance, and the power consumption is effectively reduced. Therefore, compared with the prior art, the embodiment of the invention can effectively inhibit the impact current generated when the power supply is electrified.
Drawings
Fig. 1 is a schematic structural diagram of an inrush current suppression circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another rush current suppression circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another surge current suppression circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another surge current suppression circuit according to an embodiment of the present invention;
Fig. 5 is a diagram showing a comparison of simulation results of a set versus no set inrush current suppression circuit according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
The embodiment of the invention provides an impact current suppression circuit. Fig. 1 is a schematic structural diagram of an inrush current suppression circuit according to an embodiment of the present invention. Referring to fig. 1, the rush current suppression circuit includes: a switch module 310, a current limiting module 320, and a switch control module 330.
The switch module 310 includes a control terminal 33, a first terminal 31, and a second terminal 32; the first end 31 of the switch module 310 is electrically connected with the first end 11 of the power supply 10, and the second end 32 is electrically connected with the rear-stage circuit 20; the switch module 310 is used to turn on or off in response to a signal at its control terminal 33. The current limiting module 320 includes an input 34 and an output 35; the input terminal 34 of the current limiting module 320 is electrically connected to the first terminal 11 of the power supply 10, and the output terminal 35 is electrically connected to the second terminal 32 of the switching module 310. The switch control module 330 includes a first input 36, a second input 37, a third input 38, and an output 39; the first input 36 of the switch control module 330 is connected to the delayed power signal Vd, the second input 37 is electrically connected to the output 35 of the current limiting module 320, the third input 38 is electrically connected to the second end 12 of the power supply 10, and the output 39 is electrically connected to the control end 33 of the switch module 310.
Wherein, the equivalent impedance of the switch module 310 when turned on is smaller than the equivalent impedance of the current limiting module 320; in a preset time after the power supply 10 is powered on, the delayed power supply signal Vd does not reach a preset voltage, and the switch control module 310 is configured to control the switch module 310 to be turned off in response to the delayed power supply signal Vd, so that the power supply 10 supplies power to the post-stage circuit 20 through the current limiting module 320.
The rush current suppression circuit may be applied to a motor controller of a new energy automobile, and the power supply 10 may be a dc power supply externally provided such as a battery; the second end of the power supply 10 may be a ground end thereof, to which a ground signal is connected; the rear stage circuit 20 may be an electrical load in an automobile. The switching module 310 may be formed of a switching device such as a transistor or a relay. The delay power supply signal Vd is a voltage signal which changes with time; for example, a voltage signal which continues to increase with time up to a peak value, a voltage signal having a stepwise waveform, or the like may be used as long as a predetermined voltage is not reached within a predetermined time after the power supply 10 is powered on.
Illustratively, the operation of the rush current suppression circuit includes:
The delayed power supply signal Vd does not reach the preset voltage within the preset time after the power supply 10 is powered on. The period can be considered as the period when the electric equipment such as an automobile is started and the power supply 10 is just connected, and larger impact current is easy to generate. At this time, the power signal output from the first end 11 of the power supply 10 may be transmitted through the switching module 310 or the current limiting module 320; the initial state of the switching module 310 is preferably set to an off state to secure power supply stability. The delayed power supply signal Vd does not reach the preset voltage, so that whether the path between the third input terminal 38 and the output terminal 39 of the switch control module 330 is turned on is controlled by the power supply signal transmitted to the second input terminal 37 of the switch control module 330; at this time, the power signal controls conduction between the third input terminal 38 and the output terminal 39 of the switch control module 330; the signal (ground signal) output by the second terminal 12 of the power supply 10 is transmitted to the control terminal of the switch module 33 through the switch control module 330, so as to control the switch module 330 to be turned off, or to maintain the switch module 330 in an off state; so that the power supply 10 can only supply power to the subsequent stage circuit 20 through the current limiting module 320 with larger equivalent impedance in the preset time, and the impact current can be effectively suppressed.
After reaching the preset time, the delayed power supply signal Vd reaches the preset voltage. The period of time can be considered that the electric equipment such as an automobile works normally. At this time, the delayed power supply signal Vd controls the path between the third input terminal 38 and the output terminal 39 of the switch control module 330 to be disconnected; the delay power signal Vd is transmitted to the control end 33 of the switch module 310 through the output end 39 of the switch control module 330, and the switch module 310 is controlled to be turned on; since the equivalent impedance of the switch module 310 when turned on is smaller than that of the current limiting module 320, the power supply 10 supplies power to the rear stage circuit 20 through the switch module 310; to reduce power consumption when the device is operating normally.
The preset voltage may be understood as a critical value that the delayed power signal Vd can control the switch control module 330 between the third input terminal 38 and the output terminal 39 from on to off. Alternatively, a path may be always conductive between the first input 36 and the output 39 of the switch control module 330; in a preset time after the power supply 10 is powered on, the delayed power supply signal Vd is empty or does not reach a preset voltage, so that the switch module 310 cannot be turned on, and thus the function of the inrush current suppression circuit is not affected. And, when the delayed power signal Vd does not reach the preset voltage, the third input end 38 and the output end 39 of the switch control module 330 are controlled by the power signal, so that the signal of the second end 12 of the power supply 10 can be stably transmitted to the control end 33 of the switch module 310, so as to ensure that the switch module 310 is always kept in an off state within a preset time, and ensure the reliability of the impact current suppression circuit.
In the surge current suppression circuit provided by the embodiment of the invention, a switch module 310, a current limiting module 320 and a switch control module 330 are arranged; the following procedure may be implemented: in a preset time after the power supply 10 is powered on, the delayed power supply signal Vd does not reach a preset voltage, and the switch control module 330 controls the switch module 310 to be reliably turned off, so that the power supply signal provided by the power supply 10 can only be transmitted through the current limiting module 320 with larger impedance, and the influence of the impact current is effectively reduced; after the delayed power signal Vd reaches the preset voltage, the switch control module 330 controls the switch module 310 to be turned on, so that the power signal is transmitted through the switch module 310 with smaller impedance, thereby effectively reducing power consumption. Therefore, the embodiment of the invention can effectively inhibit the impact current generated when the power supply 10 is powered on.
Fig. 2 is a schematic diagram of another surge current suppression circuit according to an embodiment of the present invention. Optionally, referring to fig. 2, on the basis of the above embodiments, the rush current suppression circuit further includes: the power conversion module 340. The input end of the power conversion module 340 is electrically connected with the first end of the power supply 10, and the output end of the power conversion module 340 is electrically connected with the first input end of the switch control module 330; the power conversion module 340 is configured to convert a power signal output by the power supply 10 into a delayed power signal.
By the arrangement, the delay power supply signal is converted from the power supply signal output by the power supply 10, and the delay power supply signal is not required to be additionally arranged, so that the universality of the impact current suppression circuit is improved.
On the basis of the above embodiments, optionally, the power conversion module 340 is an original conversion module in a control device such as an automobile motor controller, where the control device applies an impact current suppression circuit, and only uses an output signal of the conversion module as a delay power signal; accordingly, the preset time may be set in a period in which the power conversion module 340 has not converted the power signal into the power supply voltage of other functional components connected to the conversion module in the control device. By this arrangement, the structure of the rush current suppressing circuit can be simplified by utilizing the original structure in the control apparatus.
With continued reference to fig. 2, optionally, based on the embodiments described above, the switch control module 330 includes: a voltage setting unit 331, a control unit 332, a first output unit 333, and a second output unit 334. The first input end of the voltage setting unit 331 is connected with a delay power supply signal, and the second input end of the voltage setting unit is electrically connected with the second end of the power supply 10; the voltage setting unit 331 is used for setting a preset voltage. The preset voltage may be understood as a value that the delay power signal should reach when the voltage setting unit 331 outputs the on voltage between the third input terminal and the output terminal of the control unit 332. The first input end of the control unit 332 is electrically connected with the output end of the voltage setting unit 331, the second input end is electrically connected with the output end of the current limiting module 320, and the third input end is electrically connected with the second end of the power supply 10; the control unit 332 is configured to control the control unit 332 to output a signal (power signal) of the first terminal of the power supply 10 or a signal (ground signal) of the second terminal of the power supply 10 according to an output signal of the voltage setting unit 331. A first input end of the first output unit 333 is electrically connected to an output end of the control unit 332, a second input end is electrically connected to a second end of the power supply 10, and an output end is electrically connected to a control end of the switch module 310; the first output unit 333 is configured to be turned on when the control unit 332 outputs a signal of the first terminal of the power supply 10, and output a signal of the second terminal of the power supply 10. The input end of the second output unit 334 is connected with the delay power supply signal, and the output end of the second output unit is electrically connected with the control end of the switch module 310; the second output unit 334 is used for outputting a delayed power supply signal.
Illustratively, the operation of the switch control module 330 includes:
When the delayed power supply signal does not reach the preset voltage, the output signal of the voltage setting unit 331 controls the path between the third input terminal and the output terminal of the control unit 332 to be disconnected; the signal (power signal) of the first end of the power supply 10 is transmitted to the first input end of the first output unit 333 through the second input end and the output end of the control unit 332, the first output unit 333 is controlled to be turned on, the signal (ground signal) of the second end of the power supply 10 is transmitted to the control end of the switch module 310 through the second input end and the output end of the first output unit 333, and the switch module 310 is controlled to be turned off.
When the delay power supply signal reaches the preset voltage, the output signal of the voltage setting unit 331 controls the path between the third input end and the output end of the control unit 332 to be conducted; the ground signal is transmitted to the first input end of the first output unit 333 through the third input end and the output end of the control unit 332, and the first output unit 333 is controlled to be turned off; the delayed power signal is transmitted to the control terminal of the switch module 310 through the second output unit 334, and controls the switch module 310 to be turned on.
The above embodiments exemplarily give a block structure of the rush current suppressing circuit, and a specific structure of the rush current suppressing circuit will be described below, but the present invention is not limited thereto.
Fig. 3 is a schematic diagram of a structure of another rush current suppression circuit according to an embodiment of the present invention. Referring to fig. 3, in one embodiment, optionally, the switch module 310 includes: a first transistor Q1; the control electrode of the first transistor Q1 is used as the control terminal of the switch module 310, the first electrode is used as the first terminal of the switch module 310, and the second electrode is used as the second terminal of the switch module 310. This arrangement makes the structure of the switch module 310 simple and easy to implement. The first transistor Q1 may be an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), for example. Optionally, the switch module 310 further includes: a resistor R11 connected as a protection resistor between the control electrode and the second electrode of the first transistor Q1; illustratively, the resistance of the resistor R11 may be relatively large, such as 10kΩ.
With continued reference to fig. 3, in one embodiment, optionally the flow restriction module 320 includes: a current limiting resistor Rs; the first terminal of the current limiting resistor Rs is used as the first terminal of the current limiting module 320, and the second terminal is used as the second terminal of the current limiting module 320. Illustratively, the resistance of the current limiting resistor Rs may be set according to the voltage level of the power supply 10. Further, the current limiting module 320 further includes: the diode D1, as a rectifier diode, can limit the current transmission direction. The first pole of the diode D1 is used as a first terminal of the current limiting module 320, and the second pole is electrically connected to a first terminal of the current limiting resistor Rs.
With continued reference to fig. 3, in one embodiment, optionally, the voltage setting unit 331 includes: a first zener diode U1 and a first resistor R1; a first pole of the first zener diode U1 is used as a first input end of the voltage setting unit 331, and is connected to the delay power signal Vd; the second pole of the first zener diode U1 is electrically connected to the first end of the first resistor R1 and is used as the output end of the voltage setting unit 331; the second terminal of the first resistor R1 serves as a second input terminal of the voltage setting unit 331. In this way, the preset voltage of the delayed power signal Vd and the on voltage of the control unit 332 can be matched through the first zener diode U1 and the first resistor R1, so that the flexibility of the rush current suppression circuit is improved, and the rush current suppression circuit is adapted to the existing conversion modules in various control devices.
With continued reference to fig. 3, in one embodiment, optionally, the control unit 332 includes: a second transistor Q2 and a fourth resistor R4; a control electrode of the second transistor Q2 serves as a first input terminal of the control unit 332; the first pole of the second transistor Q2 is electrically connected to the second end of the fourth resistor R4 and serves as an output end of the control unit 332; the second pole of the second transistor Q2 is used as the third input terminal of the control unit 332; the first terminal of the fourth resistor R4 serves as a second input terminal of the control unit 332. The second transistor Q2 may be a transistor, for example. Further, the control unit 332 further includes a resistor R6 and a resistor R7 as protection resistors of the second transistor Q2; a resistor R6 is connected between the output terminal of the voltage setting unit 331 and the control electrode of the second transistor Q2; a resistor R7 is connected between the control electrode and the second electrode of the second transistor Q2.
With continued reference to fig. 3, in one embodiment, optionally the first output unit 333 includes: a third transistor Q3; the control electrode of the third transistor Q3 is used as the first input terminal of the first output unit 333, the first electrode is used as the output terminal of the first output unit 333, and the second electrode is used as the second input terminal of the first output unit 333. This arrangement makes the structure of the first output unit 333 simple and easy to implement. The third transistor Q3 may be a transistor, for example. Further, the first output unit 333 further includes a resistor R8, a resistor R9, and a resistor R10 as protection resistors; a resistor R8 is connected between the output terminal of the control unit 332 and the control electrode of the third transistor Q3; a resistor R9 is connected between the control electrode and the second electrode of the third transistor Q3; a resistor R10 is connected between the first pole of the third transistor Q3 and the control terminal of the switching module 310.
With continued reference to fig. 3, in one embodiment, optionally the second output unit 334 includes: a fifth resistor R5; the first terminal of the fifth resistor R5 is used as an input terminal of the second output unit 334, and the second terminal is used as an output terminal of the second output unit 334. This arrangement makes the structure of the second output unit 334 simple and easy to implement.
With continued reference to fig. 3, the surge current suppression circuit may further include a capacitor C1, as a filter capacitor, connected between the output terminal of the current limiting module 320 and the ground terminal, to improve power supply stability. The power supply 10 may comprise a direct current power supply DC, for example a low voltage direct current power supply.
The following specifically describes the working process of the impact current suppression circuit by taking the output signal of the original conversion module in the control device as an example of the delayed power supply signal Vd with reference to fig. 3:
After the control device is started, in a preset time after the power supply 10 is powered on, since the conversion module does not work normally yet, the delay power supply signal Vd is 0 or does not reach a preset voltage, and the second transistor Q2 is turned off; the power supply signal is transmitted to the control electrode of the third transistor Q3 through the fourth resistor R4 and the resistor R8, and the third transistor Q3 is controlled to be conducted; the control electrode of the first transistor Q1 is pulled down to ground through the third transistor Q3 and the resistor R10, so that the control electrode of the first transistor Q1 is reverse biased with the second electrode, the first transistor Q1 is turned off, and the power supply 10 supplies power to the post-stage circuit 20 through the diode D1 and the current limiting resistor R.
After a preset time, the conversion module works normally, and the delay power supply signal Vd reaches a preset voltage, so that the second transistor Q2 is conducted; the ground signal is transmitted to the control electrode of the third transistor Q3 through the second transistor Q2 and the resistor R8, so that the voltage difference between the control electrode of the third transistor Q3 and the second electrode is 0, and the third transistor Q3 is turned off; at this time, the delay power signal Vd turns on the first transistor Q1 through the fifth resistor R5, providing a low impedance path, and the power supply 10 supplies power to the post-stage circuit 20 through the first transistor Q1.
In summary, the inrush current suppression circuit reduces the inrush current at the moment of starting the product by adding the current limiting module 320 in the power supply loop of the power supply 10. That is, the present embodiment enables the current limiting module 320 as a current transmission path to reduce the impact current during a period when the power supply 10 is powered on and is liable to generate the impact current by the control of the switch control module 330 at the start of the product; when the product is operating normally after the turn-on period is avoided, the current limiting module 320 is bypassed, and the switching module 310 is enabled to serve as a power transmission path to reduce power consumption when the product is operating normally.
Fig. 4 is a schematic structural diagram of yet another rush current suppression circuit according to an embodiment of the present invention. Referring to fig. 4, in one embodiment, the circuit is optionally similar to the structure of fig. 3, except that: in the present embodiment, the voltage setting unit 331 includes: the second voltage stabilizing diode U2, the second resistor R2 and the third resistor R3; a first end of the second resistor R2 is used as a first input end of the voltage setting unit 331; the second end of the second resistor R2 is electrically connected with the first pole of the second zener diode U2 and is used as the output end of the voltage setting unit 331; the second pole of the second zener diode U2 is electrically connected with the first end of the third resistor R3; the second terminal of the third resistor R3 serves as a second input terminal of the voltage setting unit 331. The present embodiment provides the voltage setting unit 331 of another structure, providing more choices for the structure of the rush current suppressing circuit.
With continued reference to fig. 4, the switch control module 330 may further include a second capacitor C2, as a filter capacitor, connected between the delayed power signal terminal and the ground terminal, to improve the stability of the inrush current suppression circuit.
Fig. 5 is a diagram showing a comparison of simulation results of a set versus no set inrush current suppression circuit according to an embodiment of the present invention. In the simulation experiment, the circuit configuration in fig. 4 is taken as a simulation circuit at the time of setting the rush current suppressing circuit. Referring to fig. 5, illustratively, the abscissa represents the simulation time and the ordinate represents the current transmitted to the subsequent stage circuit; the time t1 is the power-on time of the power supply when the impact current suppression circuit is not arranged; and the time t2 is the power-on time of the power supply when the impact current suppression circuit is arranged. As shown in fig. 5, when the rush current suppression circuit is not provided, the absolute value of the rush current peak value at the time of power-on of the power supply is larger than 9A; when the surge current suppression circuit is arranged, the absolute value of the surge current peak value at the power-on time of the power supply is smaller than 1A, which indicates that the surge current suppression circuit provided by the embodiment of the invention can effectively suppress the surge current generated when the power supply is powered on.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (9)
1. An inrush current suppression circuit, comprising:
The switch module comprises a control end, a first end and a second end; the first end of the switch module is electrically connected with the first end of the power supply, and the second end of the switch module is electrically connected with the rear-stage circuit; the switch module is used for responding to the signal of the control end to turn on or off;
The current limiting module comprises an input end and an output end; the input end of the current limiting module is electrically connected with the first end of the power supply, and the output end of the current limiting module is electrically connected with the second end of the switch module;
The switch control module comprises a first input end, a second input end, a third input end and an output end; the first input end of the switch control module is connected with a delay power supply signal, the second input end of the switch control module is electrically connected with the output end of the current limiting module, the third input end of the switch control module is electrically connected with the second end of the power supply, and the output end of the switch control module is electrically connected with the control end of the switch module;
Wherein, the equivalent impedance of the switch module when being conducted is smaller than that of the current limiting module; the switch control module is used for responding to the delay power supply signal to control the switch module to be disconnected so that the power supply supplies power to the rear-stage circuit through the current limiting module;
The switch control module includes:
the voltage setting unit comprises a first input end, a second input end and an output end; the first input end of the voltage setting unit is connected with the delay power supply signal, and the second input end of the voltage setting unit is electrically connected with the second end of the power supply; the voltage setting unit is used for setting the preset voltage;
the control unit comprises a first input end, a second input end, a third input end and an output end; the first input end of the control unit is electrically connected with the output end of the voltage setting unit, the second input end of the control unit is electrically connected with the output end of the current limiting module, and the third input end of the control unit is electrically connected with the second end of the power supply; the control unit is used for controlling the control unit to output a signal of a first end of the power supply or a signal of a second end of the power supply according to the output signal of the voltage setting unit;
the first output unit comprises a first input end, a second input end and an output end; the first input end of the first output unit is electrically connected with the output end of the control unit, the second input end of the first output unit is electrically connected with the second end of the power supply, and the output end of the first output unit is electrically connected with the control end of the switch module; the first output unit is used for being conducted when the control unit outputs a signal of a first end of the power supply and outputting a signal of a second end of the power supply;
The second output unit comprises an input end and an output end; the input end of the second output unit is connected with the delay power supply signal, and the output end of the second output unit is electrically connected with the control end of the switch module; the second output unit is used for outputting the delay power supply signal.
2. The rush current suppression circuit according to claim 1, further comprising: the power conversion module comprises an input end and an output end; the input end of the power conversion module is electrically connected with the first end of the power supply, and the output end of the power conversion module is electrically connected with the first input end of the switch control module; the power conversion module is used for converting the power signal output by the power supply into the time delay power signal.
3. The rush current suppression circuit according to claim 1, wherein the switch module comprises: a first transistor; the control electrode of the first transistor is used as the control end of the switch module, the first electrode of the first transistor is used as the first end of the switch module, and the second electrode of the first transistor is used as the second end of the switch module.
4. The rush current suppression circuit according to claim 1, wherein the current limiting module comprises: a current limiting resistor; the first end of the current limiting resistor is used as the first end of the current limiting module, and the second end of the current limiting resistor is used as the second end of the current limiting module.
5. The rush current suppression circuit of claim 4, wherein the current limiting module further comprises: a diode; the first pole of the diode is used as the first end of the current limiting module, and the second pole of the diode is electrically connected with the first end of the current limiting resistor.
6. The rush current suppression circuit according to claim 1, wherein the voltage setting unit includes: a first zener diode and a first resistor; a first pole of the first zener diode is used as a first input end of the voltage setting unit; the second pole of the first zener diode is electrically connected with the first end of the first resistor and is used as the output end of the voltage setting unit; the second end of the first resistor is used as a second input end of the voltage setting unit;
Or the voltage setting unit includes: the second voltage stabilizing diode, the second resistor and the third resistor; the first end of the second resistor is used as a first input end of the voltage setting unit; the second end of the second resistor is electrically connected with the first pole of the second zener diode and is used as the output end of the voltage setting unit; the second pole of the second zener diode is electrically connected with the first end of the third resistor; the second end of the third resistor is used as a second input end of the voltage setting unit.
7. The rush current suppression circuit according to claim 1, wherein the control unit includes: a second transistor and a fourth resistor; the control electrode of the second transistor is used as a first input end of the control unit; the first electrode of the second transistor is electrically connected with the second end of the fourth resistor and is used as an output end of the control unit; a second pole of the second transistor is used as a third input end of the control unit; the first end of the fourth resistor is used as a second input end of the control unit.
8. The rush current suppression circuit according to claim 1, wherein the first output unit includes: a third transistor; the control electrode of the third transistor is used as a first input end of the first output unit, the first electrode of the third transistor is used as an output end of the first output unit, and the second electrode of the third transistor is used as a second input end of the first output unit.
9. The rush current suppression circuit according to claim 1, wherein the second output unit includes: a fifth resistor; the first end of the fifth resistor is used as the input end of the second output unit, and the second end of the fifth resistor is used as the output end of the second output unit.
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| CN202111210526.9A CN113937743B (en) | 2021-10-18 | 2021-10-18 | Impact current suppression circuit |
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| CN202111210526.9A CN113937743B (en) | 2021-10-18 | 2021-10-18 | Impact current suppression circuit |
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Also Published As
| Publication number | Publication date |
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| CN113937743A (en) | 2022-01-14 |
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