CN113937013A - Semiconductor packaging method and semiconductor packaging structure - Google Patents

Semiconductor packaging method and semiconductor packaging structure Download PDF

Info

Publication number
CN113937013A
CN113937013A CN202010669912.3A CN202010669912A CN113937013A CN 113937013 A CN113937013 A CN 113937013A CN 202010669912 A CN202010669912 A CN 202010669912A CN 113937013 A CN113937013 A CN 113937013A
Authority
CN
China
Prior art keywords
conductive
packaged
layer
bare chip
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010669912.3A
Other languages
Chinese (zh)
Inventor
周辉星
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SIPLP Microelectronics Chongqing Ltd
Original Assignee
SIPLP Microelectronics Chongqing Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SIPLP Microelectronics Chongqing Ltd filed Critical SIPLP Microelectronics Chongqing Ltd
Priority to CN202010669912.3A priority Critical patent/CN113937013A/en
Priority to PCT/CN2021/106011 priority patent/WO2022012532A1/en
Publication of CN113937013A publication Critical patent/CN113937013A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The application provides a semiconductor packaging method and a semiconductor packaging structure. In the present application, a semiconductor packaging method includes: fixing a first bare chip to be packaged, a second bare chip to be packaged and conductive columns on a carrier plate, wherein an inductance element is arranged on the back surface of the first bare chip to be packaged, and the conductive columns are arranged between the first bare chip to be packaged and the second bare chip to be packaged; forming a plastic packaging layer on the carrier plate, wherein the plastic packaging layer wraps the first bare chip to be packaged, the second bare chip to be packaged, the inductance element and the conductive columns, and the first electric connection point of the inductance element and one end of each conductive column are exposed out of the plastic packaging layer; forming a first conductive trace on one side of the plastic packaging layer close to the back surface of the first bare chip to be packaged, wherein the first conductive trace is connected with a first electric connection point of the inductance element and a first end of the conductive column; removing the carrier plate; and forming a second conductive trace on one side of the plastic packaging layer close to the front surface of the first bare chip to be packaged, wherein the second conductive trace is connected with a second welding pad and a conductive column of the second bare chip to be packaged. In the embodiment of the application, the semiconductor packaging structure is small in size.

Description

Semiconductor packaging method and semiconductor packaging structure
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor packaging method and a semiconductor packaging structure.
Background
In the related art, in the packaging process, the inductors and the bare chips in the package assembly may be arranged together on the carrier to form a package body with a parallel arrangement structure. The package body with the structure has larger volume and is not compact.
With the miniaturization and light weight of electronic devices, chip packages having compact structures and small volumes are gaining more and more market favor.
However, how to reduce the volume of the chip package is a technical problem to be solved.
Disclosure of Invention
In view of this, embodiments of the present disclosure provide a semiconductor packaging method and a semiconductor packaging structure, so that the semiconductor packaging structure has a small volume and a compact structure.
Some embodiments of the present application provide a semiconductor packaging method, including:
fixing a first bare chip to be packaged, a second bare chip to be packaged and a conductive column on a carrier plate, wherein the front surface of the first bare chip to be packaged and the front surface of the second bare chip to be packaged face the carrier plate, the front surface of the first bare chip to be packaged is provided with a first welding pad, the front surface of the second bare chip to be packaged is provided with a second welding pad, the back surface of the first bare chip to be packaged is provided with an inductive element, the inductive element comprises a first electric connection point, the first electric connection point is positioned on one side, away from the first bare chip to be packaged, of the inductive element, and the conductive column is positioned between the first bare chip to be packaged and the second bare chip to be packaged; the conductive column comprises a first end and a second end, the first end is located at one end, close to the inductance element, of the conductive column, and the second end is located at one end, far away from the inductance element, of the conductive column;
forming a plastic package layer on the carrier plate, wherein the first die to be packaged, the second die to be packaged, the inductance element and the conductive posts are wrapped by the plastic package layer, and the first electrical connection points of the inductance element and the surfaces of the first ends of the conductive posts are respectively exposed out of the plastic package layer;
forming a first conductive trace on one side of the molding compound layer close to the back surface of the first bare chip to be packaged, wherein the first conductive trace connects the first electrical connection point of the inductance element and the first end of the conductive column;
removing the carrier plate;
and forming a second conductive trace on one side of the plastic packaging layer close to the front surface of the first die to be packaged, wherein the second conductive trace connects a second welding pad of the second die to be packaged with the second end of the conductive column.
In one embodiment, before the fixing the first die to be packaged, the second die to be packaged, and the conductive pillars on the carrier plate, the method further includes:
forming a first metal layer on the back of the silicon wafer through an electroplating process;
etching the first metal layer by an etching process to obtain the inductance element;
dividing the silicon wafer to obtain the first bare chip to be packaged; or,
before the first bare chip to be packaged, the second bare chip to be packaged and the conductive columns are fixed on the carrier plate, the method further comprises the following steps:
forming a seed layer on the back of the silicon wafer through a sputtering process;
forming a first metal layer on the seed layer through an electroplating process;
etching the first metal layer and the seed layer through an etching process to obtain the inductance element;
dividing the silicon wafer to obtain the first bare chip to be packaged;
the seed layer comprises a first seed layer and a second seed layer, the first seed layer is positioned on the silicon chip, the second seed layer is positioned on the first seed layer, the first seed layer is made of titanium, and the second seed layer is made of copper; or,
the seed layer comprises a second seed layer, and the second seed layer is made of copper.
In one embodiment, the front side of the first to-be-packaged die is also formed with a first protective layer;
a second protection layer is further formed on the front surface of the second die to be packaged; the distance between the surfaces of the first protective layer and the second protective layer, which are far away from the inductance element, and the surfaces of the inductance element, which are far away from the first protective layer, is smaller than the height of the conductive posts.
In one embodiment, the conductive posts are preformed; or,
forming a second metal layer on the carrier plate;
and etching the second metal layer by an etching process to obtain the conductive post.
In one embodiment, the forming a molding layer on the carrier plate includes:
forming an encapsulating layer on the carrier plate, wherein the encapsulating layer wraps the first bare chip to be packaged, the second bare chip to be packaged, the inductance element and the conductive columns, and the thickness of the encapsulating layer is greater than the heights of the conductive columns;
and thinning the encapsulating layer to obtain the plastic packaging layer, so that the first end of the conductive column is exposed out of the plastic packaging layer.
In one embodiment, the molding compound layer comprises a first opening to expose a first electrical connection point of the inductance element;
and forming the first opening on the plastic packaging layer through a laser hole-opening process.
In one embodiment, forming a first conductive trace on a side of the molding layer near the back side of the first die to be packaged includes:
filling a first conductive medium in the first opening to form a first conductive filling interface, and forming a first conductive layer on the plastic packaging layer; the first conductive filling interface is electrically connected with a first electrical connection point of the inductance element, and the first conductive layer is electrically connected with the first conductive filling interface;
patterning the first conductive layer to obtain the first conductive trace;
wherein the first conductive fill interface and the first conductive layer are formed in the same process step.
In one embodiment, after forming the first conductive trace on the side of the molding compound layer close to the back side of the first die to be packaged, the method further includes:
forming a first dielectric layer on the first conductive trace, the first dielectric layer encapsulating the first conductive trace.
In one embodiment, the semiconductor packaging method further includes:
forming a second opening on the first protection layer to expose the first bonding pad;
forming a third opening on the second protective layer to expose the second pad;
the step of forming the second opening on the first protective layer is located after the step of removing the carrier plate, or located after the step of forming the first protective layer on the front surface of the first die to be packaged and before the step of fixing the first die to be packaged, the second die to be packaged and the conductive pillar on the carrier plate;
the step of forming the third opening on the second protective layer is located after the step of removing the carrier plate, or located after the step of forming the second protective layer on the front side of the second die to be packaged and before the step of fixing the first die to be packaged, the second die to be packaged and the conductive pillar on the carrier plate;
when the first protection layer is made of a laser reaction type material, forming a second opening on the first protection layer through a laser hole forming process;
when the first protection layer is made of a photosensitive material, forming the second opening on the first protection layer through a photoetching process;
when the second protection layer is made of a laser reaction type material, forming the third opening on the second protection layer through a laser hole opening process;
and when the material of the second protective layer is a photosensitive material, forming the third opening on the second protective layer through a photoetching process.
In one embodiment, the forming of the second conductive trace on the side of the molding compound layer close to the front side of the first die to be packaged includes:
filling a second conductive medium into the second opening and the third opening to form a second conductive filling interface, and forming a second conductive layer on the plastic package layer, the first protective layer and the second protective layer; the second conductive filling interface is electrically connected with a first welding pad of the first bare chip to be packaged and a second welding pad of the second bare chip to be packaged respectively, and the second conductive layer is electrically connected with the second conductive filling interface;
patterning the second conductive layer to obtain the second conductive trace;
wherein the second conductive fill interface is formed in the same process step as the second conductive layer.
In one embodiment, the second conductive trace includes a second electrical connection point located on a side of the second conductive trace away from the first die to be packaged; after forming the second conductive traces on the side of the molding compound layer close to the front surface of the first die to be packaged, the method further comprises the following steps:
forming a conductive convex column on the second electric connection point;
forming a second dielectric layer on the second conductive trace and the conductive convex column to obtain a plastic package body; the second dielectric layer encasing the second conductive traces and the conductive posts, the conductive posts exposed from the second dielectric layer away from a surface of the first die to be packaged;
cutting the plastic package body to obtain a semiconductor package structure, wherein the semiconductor package structure comprises the first bare chip to be packaged, the second bare chip to be packaged, the inductance element, the conductive pillar, the plastic package layer, the first conductive trace and the second conductive trace, or,
after forming the second conductive traces on the side of the molding compound layer close to the front surface of the first die to be packaged, the method further comprises the following steps:
forming a conductive convex column on the second electric connection point;
forming a second dielectric layer on the second conductive trace and the conductive convex column to obtain a plastic package body; the second dielectric layer encasing the second conductive traces and the conductive posts, the conductive posts exposed from the second dielectric layer away from a surface of the first die to be packaged;
forming a surface treatment layer on the exposed surface of the conductive convex column;
and cutting the plastic package body to obtain a semiconductor package structure, wherein the semiconductor package structure comprises the first bare chip to be packaged, the second bare chip to be packaged, the inductance element, the conductive column, the plastic package layer, the first conductive trace and the second conductive trace.
Some embodiments of the present application further provide a semiconductor package structure, which is manufactured by the above semiconductor packaging method, and the semiconductor package structure includes:
the front surface of the first bare chip to be packaged is provided with a first welding pad, and the front surface of the second bare chip to be packaged is provided with a second welding pad;
the inductance element is positioned on the back surface of the first bare chip to be packaged; the inductance element comprises a first electric connection point, and the first electric connection point is positioned on one side of the inductance element, which is far away from the first bare chip to be packaged;
conductive pillars located between the first die to be packaged and the second die to be packaged; the conductive column comprises a first end and a second end, the first end is located at one end, close to the inductance element, of the conductive column, and the second end is located at one end, far away from the inductance element, of the conductive column;
the encapsulation layer wraps the first bare chip to be packaged, the second bare chip to be packaged, the inductance element and the conductive columns, and the first electric connection point of the inductance element, the surface of the first end of the conductive column and the surface of the second end of the conductive column are respectively exposed out of the encapsulation layer;
the first conductive trace is positioned on one side, close to the back surface of the first bare chip to be packaged, of the plastic packaging layer and is connected with the first electrical connection point of the inductance element and the first end of the conductive column;
and the second conductive trace is positioned on one side of the plastic packaging layer close to the front surface of the first bare chip to be packaged and is used for connecting a second welding pad of the second bare chip to be packaged with the second end of the conductive column.
In the embodiment of the application, the inductance element is arranged on the back face of the first bare chip to be packaged, so that the first bare chip to be packaged and the inductance element are arranged in a stacked mode in the thickness direction of the first bare chip to be packaged, the space in the thickness direction of the first bare chip to be packaged is reasonably utilized, the structure of the semiconductor packaging structure can be compact, and the size of the semiconductor packaging structure is further reduced. Therefore, the semiconductor packaging structure in the embodiment of the application has small volume and compact structure, and is suitable for small-sized and light-weight electronic equipment.
Drawings
Fig. 1 is a schematic structural diagram of a semiconductor package structure according to an embodiment of the present application.
Fig. 2 is a schematic flow chart diagram illustrating a semiconductor packaging method according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram illustrating an intermediate structure produced during the process of fabricating a semiconductor package structure according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram illustrating another intermediate structure produced during the process of fabricating a semiconductor package structure according to an embodiment of the present application.
Fig. 5 is a schematic structural diagram illustrating another intermediate structure produced during the process of fabricating a semiconductor package structure according to an embodiment of the present application.
Fig. 6 is a schematic structural diagram illustrating another intermediate structure produced during the process of fabricating a semiconductor package structure according to an embodiment of the present application.
Fig. 7 is a schematic structural diagram illustrating another intermediate structure produced during the process of fabricating a semiconductor package structure according to an embodiment of the present application.
Fig. 8 is a schematic structural diagram illustrating another intermediate structure produced during fabrication of a semiconductor package structure according to an embodiment of the present application.
Fig. 9 is a schematic structural diagram illustrating another intermediate structure produced during the fabrication of a semiconductor package structure according to an embodiment of the present application.
Fig. 10 is a schematic diagram illustrating another intermediate structure produced during the fabrication of a semiconductor package structure according to an embodiment of the present application.
Fig. 11 is a schematic diagram illustrating another intermediate structure produced during the fabrication of a semiconductor package structure according to an embodiment of the present application.
Fig. 12A is a schematic structural diagram illustrating another intermediate structure produced during fabrication of a semiconductor package structure according to an embodiment of the present application.
Fig. 12B is a schematic structural diagram illustrating another intermediate structure produced during fabrication of a semiconductor package structure according to an embodiment of the present application.
Fig. 13 is a schematic diagram illustrating another intermediate structure produced during the fabrication of a semiconductor package structure according to an embodiment of the present application.
Fig. 14 is a schematic structural diagram illustrating another intermediate structure produced during fabrication of a semiconductor package structure according to an embodiment of the present application.
Fig. 15 is a schematic structural diagram illustrating another intermediate structure produced during the fabrication of a semiconductor package structure according to an embodiment of the present application.
Fig. 16 is a schematic diagram illustrating another intermediate structure produced during the fabrication of a semiconductor package structure according to an embodiment of the present application.
Fig. 17 is a schematic diagram illustrating another intermediate structure produced during fabrication of a semiconductor package structure according to an embodiment of the present application.
Fig. 18 is a schematic structural diagram illustrating another intermediate structure produced during fabrication of a semiconductor package structure according to an embodiment of the present application.
Fig. 19 is a schematic diagram illustrating another intermediate structure produced during fabrication of a semiconductor package structure according to an embodiment of the present application.
Fig. 20 is a schematic diagram illustrating a cutting process performed on a plastic package according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
Embodiments of the present application provide a semiconductor package structure. The semiconductor package structure is a chip package. The semiconductor packaging structure is suitable for packaging an antenna chip. The conductor packaging structure can be applied to electronic equipment such as mobile phones, computers and the like. As shown in fig. 1, the semiconductor package structure includes a first die to be packaged 10, a second die to be packaged 11, an inductive element 12, a conductive pillar 13, a molding layer 14, a first conductive trace 15, a second conductive trace 16, a first protection layer 17, a second protection layer 18, a first conductive filling interface 19, a second conductive filling interface 110, a first dielectric layer 111, a conductive pillar 112, a second dielectric layer 113, and a surface treatment layer (not shown).
In the present embodiment, the first die to be packaged 10 includes a front surface and a back surface, and the front surface and the back surface are opposite. The front surface of the first die to be packaged 10 is an active surface, and the front surface of the first die to be packaged 10 is provided with first bonding pads (not shown) for making electrical connection with the outside.
In this embodiment, the second die to be packaged 11 includes a front side and a back side, the front side and the back side being opposite. The front surface of the second die 11 to be packaged is an active surface, and the front surface of the second die 11 to be packaged is provided with a second bonding pad (not shown), which is used for making an electrical connection with the outside.
In the present embodiment, as shown in fig. 1, the number of the second dies to be packaged 11 is two, but not limited thereto. The two second dies to be packaged 11 may or may not have the same function.
In the present embodiment, as shown in fig. 1, the first die to be packaged 10 is located between the two second dies to be packaged 11, but is not limited thereto.
In the present embodiment, as shown in fig. 1, the inductance element 12 is located on the back side of the first die to be packaged 10. The inductive element 12 is an electromagnetic conversion device. In the present embodiment, the material of the inductance element 12 is copper, but is not limited thereto.
In the present embodiment, the inductive element 12 includes a first electrical connection point (not shown) located on a side of the inductive element 12 away from the first die to be packaged 10. The first electric connection point is used for being electrically connected with the outside.
In the present embodiment, as shown in fig. 1, the conductive pillars 13 are located between the first die to be packaged 10 and the second die to be packaged 11. The material of the conductive post 13 may be copper, but is not limited thereto. The conductive pillar 13 includes a first end and a second end, the first end is located at an end of the conductive pillar 13 close to the inductive element 12, the second end is located at an end of the conductive pillar 13 far away from the inductive element 12, and the first end of the conductive pillar 13 is opposite to the second end of the conductive pillar 13. The surfaces of the first ends of the conductive posts 13 and the surfaces of the second ends of the conductive posts 13 are exposed from the molding layer 14.
In the present embodiment, as shown in fig. 1, the molding compound layer 14 encapsulates the first die to be packaged 10, the second die to be packaged 11, the inductance element 12, and the conductive pillars 13. The molding layer 14 may be a polymer, a resin composite material, or a polymer composite material. For example, the molding layer 14 may be a resin with a filler, wherein the filler is inorganic particles.
In the present embodiment, as shown in fig. 1, the molding layer 14 includes a first opening (not shown) to expose the first electrical connection point of the inductance element 12. Specifically, the first opening is located on a side of the molding layer 14 close to the inductive element 12, and a projection of the first opening on the inductive element 12 at least partially coincides with a projection of a first electrical connection point of the inductive element 12 on the inductive element 12, so that at least a part of the first electrical connection point is exposed from the molding layer 14. For example, a projection of the first opening on the inductive element 12 and a projection of the first electrical connection point (not shown) on the inductive element 12 may completely coincide, such that the first electrical connection point is exposed from the molding layer 14. For another example, the projection of the first opening on the inductive element 12 and the projection of the first electrical connection point on the inductive element 12 may partially coincide, so that a portion of the first electrical connection point is exposed from the molding layer 14.
In the present embodiment, as shown in fig. 1, the first conductive filling interface 19 is located in the first opening, the first conductive filling interface 19 is electrically connected to the first electrical connection point of the inductive element 12, and the first conductive trace 15 is electrically connected to the first conductive filling interface 19. The material of the first conductive filling interface 19 may be copper, but is not limited thereto.
In this embodiment, as shown in fig. 1, the first conductive trace 15 is located on a side of the molding compound layer 14 close to the back surface of the first die to be packaged 10, and connects the first electrical connection point and the first end of the conductive pillar 13. The material of the first conductive trace 15 is copper, but is not limited thereto.
In the present embodiment, as shown in fig. 1, the first dielectric layer 111 is located on the first conductive trace 15 and covers the first conductive trace 15. The material of the first dielectric layer 111 is one or more layers of insulating materials, and may be a plastic film, PI (polyimide), PBO (polybenzoxazole), an organic polymer film, an organic polymer composite material, or other materials with similar characteristics.
In the present embodiment, as shown in fig. 1, the first protection layer 17 is located on the front surface of the first die to be packaged 10, the second protection layer 18 is located on the front surface of the second die to be packaged 11, the thicknesses of the first die to be packaged 10 and the second die to be packaged 11 may be the same, and the thicknesses of the first protection layer 17 and the second protection layer 18 may be the same, but is not limited thereto. The distance between the surface of the first protection layer 17 away from the inductance element 12 and the surface of the inductance element 12 away from the first protection layer 17 is smaller than the height of the conductive pillar 13. The distance between the surface of the second passivation layer 18 away from the inductance element 12 and the surface of the inductance element 12 away from the first passivation layer 17 is smaller than the height of the conductive pillar 13. The distance between the surface of the second protective layer 18 away from the back surface of the second die 11 to be packaged and the back surface of the second die 11 to be packaged is less than the height of the conductive pillars 13.
In the present embodiment, as shown in fig. 1, the first protection layer 17 includes a second opening (not shown) to expose the first pad of the first die to be packaged 10. Specifically, the second opening is located on a side of the first protective layer 17 away from the inductance element 12, and a projection of the second opening on the first die to be packaged 10 at least partially coincides with a projection of the first pad on the first die to be packaged 10, so that at least a part of the first pad is exposed from the first protective layer 17. For example, a projection of the second opening on the first die to be packaged 10 and a projection of the first pad (not shown) on the first die to be packaged 10 may completely coincide, so that the first pad is exposed from the first protective layer 17. For another example, the projection of the second opening on the first die to be packaged 10 may partially coincide with the projection of the first pad on the first die to be packaged 10, so that a portion of the first pad is exposed from the molding layer 14.
In the present embodiment, as shown in fig. 1, the second protection layer 18 includes a third opening (not shown) to expose the second pad of the second die to be packaged 11. Specifically, the third opening is located on a side of the second protective layer 18 away from the inductive element 12, and a projection of the third opening on the second die to be packaged 11 at least partially coincides with a projection of the second pad on the second die to be packaged 11, so that at least a portion of the second pad is exposed from the second protective layer 18. For example, the projection of the third opening on the second die to be packaged 11 completely coincides with the projection of the second pad on the second die to be packaged 11, so that the second pad is exposed from the second protection layer 18. For another example, the projection of the third opening on the second die 11 to be packaged coincides with the projection of the second pad on the second die 11 to be packaged, so that part of the second pad is exposed from the second protection layer 18.
In this embodiment, as shown in fig. 1, the second conductive filling interface 110 is located in the second opening and the third opening, the second conductive filling interface 110 is electrically connected to the first pad of the first die to be packaged 10 and the second pad of the second die to be packaged 11, respectively, and the second conductive trace 16 is electrically connected to the second conductive filling interface 110. The material of the second conductive filling interface 110 is copper, but is not limited thereto.
In this embodiment, as shown in fig. 1, the second conductive trace 16 is located on a side of the molding compound layer 14 close to the front surface of the first die to be packaged 10, and connects the second pad of the second die to be packaged 11 and the second end of the conductive pillar 13. The second conductive traces 16 are also electrically connected with the first pads of the first die to be packaged 10.
In the present embodiment, as shown in fig. 1, the conductive post 112 is located on the second electrical connection point (not shown) of the second conductive trace 16. The conductive pillar 112 is made of copper, but not limited thereto.
In the present embodiment, as shown in fig. 1, the second dielectric layer 113 is disposed on the second conductive trace 16 and the conductive pillar 112, and covers the second conductive trace 16 and the conductive pillar 112, and the conductive pillar 112 is exposed from the second dielectric layer 113 away from the surface of the first to-be-packaged die 10. The material of the second dielectric layer 113 is one or more layers of insulating materials, and may be a plastic film, PI (polyimide), PBO (polybenzoxazole), organic polymer film, organic polymer composite, or other materials with similar characteristics.
In the present embodiment, a surface treatment layer (not shown) is located on the surface of the exposed conductive stud 112. The surface treatment layer serves to retard the oxidation rate of the conductive posts 112. The material of the surface treatment layer can be matte tin (fog tin) or a composite electroplated layer. For example, the composite plating layer may include a third metal layer and a fourth metal layer, the third metal layer is located on the surface of the conductive stud 112, the fourth metal layer is located on the third metal layer, the third metal layer is made of nickel (Ni), and the fourth metal layer is made of gold (Au). For another example, the composite plating layer may include a fifth metal layer on the surface of the conductive stud 112, a sixth metal layer on the fifth metal layer, and a seventh metal layer on the sixth metal layer, wherein the fifth metal layer is made of nickel (Ni), the sixth metal layer is made of palladium (Pd), and the seventh metal layer is made of gold (Au).
It should be noted that the semiconductor package structure may not include the surface treatment layer.
In the present embodiment, as shown in fig. 1, the inductance element 12 located on the back surface of the first die to be packaged 10 is electrically connected to the second die to be packaged 11 through the first conductive filling interface 19, the first conductive trace 15, the conductive pillar 13, the second conductive trace 16, and the second conductive filling interface 110.
In the embodiment of the application, the inductance element is arranged on the back face of the first bare chip to be packaged, so that the first bare chip to be packaged and the inductance element are arranged in a stacked mode in the thickness direction of the first bare chip to be packaged, the space in the thickness direction of the first bare chip to be packaged is reasonably utilized, the structure of the semiconductor packaging structure can be compact, and the size of the semiconductor packaging structure is further reduced. Therefore, the semiconductor packaging structure in the embodiment of the application has small volume and compact structure, and is suitable for small-sized and light-weight electronic equipment.
The embodiment of the application also provides a semiconductor packaging method for preparing the semiconductor packaging structure. As shown in FIG. 2, the semiconductor packaging method includes the following steps 201-211:
in step 201, a first die to be packaged, a second die to be packaged, and a conductive pillar are fixed on a carrier. The front surface of the first die 10 to be packaged and the front surface of the second die 11 to be packaged face the carrier 31, the front surface of the first die 10 to be packaged is provided with a first bonding pad, the front surface of the second die 11 to be packaged is provided with a second bonding pad, the back surface of the first die 10 to be packaged is provided with the inductive element 12, the inductive element 12 includes a first electrical connection point, the first electrical connection point is located on one side of the inductive element 12 away from the first die 10 to be packaged, the conductive pillar 13 is located between the first die 10 to be packaged and the second die 11 to be packaged, the conductive pillar 13 includes a first end and a second end, the first end is located at one end of the conductive pillar 13 close to the inductive element 12, and the second end is located at one end of the conductive pillar 13 away from the inductive element 12.
In the present embodiment, the first die to be packaged 10, the second die to be packaged 11 and the conductive pillars 13 are fixed on the carrier 31, so as to obtain the intermediate structure shown in fig. 3. Fig. 3 only shows one package unit, which is a unit that forms one semiconductor package structure (chip) after the package is completed, and actually, one or more package units on the carrier 31 may be provided, and the number of package units is not limited in this application.
In the present embodiment, the carrier 31 has an adhesive layer (not shown) thereon for fixing the first die to be packaged 10, the second die to be packaged 11 and the conductive pillars 13 arranged on the carrier 31. Preferably, the adhesive layer is a thermal release adhesive layer.
In one embodiment, step 201 may comprise: first, as shown in fig. 4, a second metal layer 41 is formed on carrier plate 31; then, as shown in fig. 5, the second metal layer 32 is etched by an etching process to obtain the conductive pillar 13; then, the first die to be packaged 10 and the second die to be packaged 11 are mounted on the carrier 31.
In another embodiment, the conductive posts are preformed. Step 201 may include: firstly, providing a first bare chip to be packaged 10, a second bare chip to be packaged 11 and a preformed conductive pillar 13; then, the first die to be packaged 10, the second die to be packaged 11 and the conductive pillars 13 are mounted on the carrier board 31.
In this embodiment, before step 201, the method further includes:
first, a seed layer is formed on the back surface of a silicon wafer through a sputtering process. In the present embodiment, the seed layer includes a first seed layer and a second seed layer. The first seed layer is positioned on the silicon chip, the second seed layer is positioned on the first seed layer, the material of the first seed layer is titanium, and the material of the second seed layer is copper. The method for forming the seed layer comprises the steps of forming a first seed layer on the back surface of the silicon wafer and forming a second seed layer on the first seed layer. The first seed layer is made of titanium, so that the interlayer adhesive force can be improved, and the second seed layer is made of copper, so that the mechanical property and the electric conductivity are good. Of course, in practical implementation, the seed layer may include only the second seed layer.
Next, a first metal layer is formed on the seed layer by an electroplating process. In this embodiment, the material of the first metal layer may be copper. After forming the first metal layer 61 on the seed layer, an intermediate structure is obtained as shown in fig. 6, wherein a seed layer (not shown) is included between the first metal layer 61 and the silicon wafer 62.
The seed layer may not be provided between the first metal layer and the back surface of the silicon wafer.
Then, the first metal layer 61 and the seed layer are etched by an etching process, so as to obtain the inductance element 12. In this embodiment, as shown in fig. 7, the first metal layer 61 is etched to obtain the inductance element 12. Specifically, an inductor (inductor/coil) may be formed on the back surface of the silicon wafer by spin coating (photoresist), exposure (exposing), development (developing), stripping (striping), and etching (etching).
Next, a first protective layer 17 is formed on the front surface of the silicon wafer. In the present embodiment, as shown in fig. 8, the first protective layer 17 is formed on the front surface of the silicon wafer 62. The first protective layer 17 may be formed by lamination, spin coating, printing, molding, or other suitable methods.
Then, the silicon wafer is divided to obtain the first bare chip to be packaged 10. In the present embodiment, as shown in fig. 9, the silicon wafer 62 is divided to obtain the first die to be packaged 10.
In this embodiment, as shown in fig. 10, a second protective layer 18 may be formed on the front surface of the silicon wafer 11a, and then, as shown in fig. 11, the silicon wafer 11a is divided to obtain a second die 11 to be packaged.
In step 202, a molding layer is formed on the carrier. The molding compound layer 14 encapsulates the first die to be packaged 10, the second die to be packaged 11, the inductance element 12 and the conductive pillars 13, and the first electrical connection points of the inductance element 12 and the surfaces of the first ends of the conductive pillars 13 are respectively exposed from the molding compound layer 14.
In this embodiment, as shown in fig. 12A, the molding compound layer 14 encapsulates the first die to be packaged 10, the second die to be packaged 11, the inductive element 12, and the conductive pillars 13, the surfaces of the first ends of the conductive pillars 13 are exposed from the molding compound layer 14, and the thickness of the molding compound layer 14 is the same as the height of the conductive pillars 13.
In this embodiment, step 202 may include the following steps: first, as shown in fig. 12B, an encapsulating layer 141 is formed on the carrier 31, the encapsulating layer 141 encapsulates the first die to be packaged 10, the second die to be packaged 11, the inductance element 12, and the conductive pillars 13, and a thickness of the encapsulating layer 141 is greater than a height of the conductive pillars 13; then, the encapsulating layer 141 is thinned to obtain the molding layer 14, so that the first ends of the conductive pillars 13 are exposed out of the molding layer 14. The thickness of the molding layer 14 is the same as the height of the conductive posts 13. When the encapsulating layer 141 is thinned, the encapsulating layer 141 may be thinned by mechanical grinding.
In step 203, a first conductive trace is formed on a side of the molding compound layer close to the back surface of the first die to be packaged, and the first conductive trace connects the first electrical connection point of the inductive element 12 and the first end of the conductive pillar.
In this embodiment, before step 203, as shown in fig. 13, an opening may be formed on the surface of the molding layer 14 away from the carrier plate 31 by a laser drilling process to obtain a first opening 131, for example, a first opening may be formed on the molding layer 14 by laser to expose the first electrical connection point of the inductance element 12.
In this embodiment, as shown in fig. 14, a first conductive filling interface 19 may be formed by first filling a first conductive medium in the first opening 131, and a first conductive layer (not shown) may be formed on the molding layer 14, wherein the first conductive filling interface 19 is electrically connected to the first electrical connection point of the inductance element 12, and the first conductive layer is electrically connected to the first conductive filling interface 19. In addition, the first conductive layer can be formed by metal sputtering, electrolytic plating, electroless plating, or the like. The first conductive fill interface 19 and the first conductive layer can be formed by the same process step. The first conductive layer is then patterned, resulting in a first conductive trace 15. In this way, the inductive element 12 may be electrically connected with the conductive post 13 through the first conductive fill interface 19, the first conductive trace 15.
In step 204, a first dielectric layer is formed over the first conductive trace, the first dielectric layer encapsulating the first conductive trace.
In the present embodiment, as shown in fig. 15, a first dielectric layer 111 is formed on the first conductive trace 15, and the first dielectric layer 111 covers the first conductive trace 15. Wherein the first dielectric layer 111 may be formed by lamination, spin coating, printing, molding, or other suitable means.
In step 205, the carrier plate is removed.
In step 206, a second opening is formed in the first passivation layer to expose the first pad of the first die to be packaged, and a third opening is formed in the second passivation layer to expose the second pad of the second die to be packaged. The projection of the second opening on the first to-be-packaged die is at least partially overlapped with the projection of the first welding pad on the first to-be-packaged die so as to expose at least part of the first welding pad; the projection of the third opening on the second die to be packaged is at least partially overlapped with the projection of the second welding pad on the second die to be packaged so as to expose at least part of the second welding pad.
In the present embodiment, as shown in fig. 16, a second opening 161 is formed on the first protection layer 17 to expose at least a portion of the first pad. When the first protection layer 17 is made of a laser-reactive material, the second opening may be formed by a laser drilling process, and when the first protection layer 17 is made of a photosensitive material, the second opening may be formed by a photolithography process.
It should be noted that the step of forming the second opening 161 on the first protection layer 17 may be located after the step 205, or may be located after the step of forming the first protection layer on the front surface of the first die to be packaged, and before the step of fixing the first die to be packaged, the second die to be packaged, and the conductive pillar on the carrier.
In the present embodiment, as shown in fig. 16, a third opening 162 is formed on the second passivation layer 18 to expose at least a portion of the second pad. When the second protection layer 18 is made of a laser-reactive material, the third opening may be formed by a laser drilling process, and when the second protection layer 18 is made of a photosensitive material, the third opening may be formed by a photolithography process.
It should be noted that, the third opening 162 formed on the second passivation layer 18 may be located after the step 205, or may be located after the step of forming the second passivation layer on the front side of the second die to be packaged, and before the step of fixing the first die to be packaged, the second die to be packaged, and the conductive pillars on the carrier.
In step 207, a second conductive trace is formed on a side of the molding compound layer close to the front surface of the first die to be packaged, and the second conductive trace connects a second pad of the second die to be packaged and a second end of the conductive pillar.
In this embodiment, as shown in fig. 17, a second conductive filling interface 110 may be formed by filling a second conductive medium in the second opening 161 and the third opening 162, and a second conductive layer (not shown) may be formed on the molding compound layer 14, the first protective layer 17 and the second protective layer 18; the second conductive filling interface 110 is electrically connected to the first pad of the first die to be packaged 10 and the second pad of the second die to be packaged 11, respectively, and the second conductive layer is electrically connected to the second conductive filling interface 110. The second conductive layer may be formed by metal sputtering, electrolytic plating, electroless plating, or the like. The second conductive fill interface 110 and the second conductive layer can be formed by the same process step. The second conductive layer is then patterned, resulting in a second conductive trace 16.
In step 208, a conductive post is formed on the second electrical connection point of the second conductive trace.
In the present embodiment, as shown in fig. 18, a conductive post 112 is formed on the second electrical connection point of the second conductive trace 16.
In step 209, a second dielectric layer is formed on the second conductive trace and the conductive pillar, thereby obtaining a plastic package. The second dielectric layer wraps the second conductive trace and the conductive post, and the conductive post is exposed out of the second dielectric layer away from the surface of the first to-be-packaged bare chip.
In this embodiment, as shown in fig. 19, a second dielectric layer 113 may be formed on the second conductive trace 16 and the conductive pillar 112, so as to obtain the plastic package 20. The second dielectric layer 113 encapsulates the second conductive trace 16 and the conductive pillar 112, and the surface of the conductive pillar 112 away from the first die to be packaged 10 is exposed from the second dielectric layer 113. The surface of the second dielectric layer 113 away from the first die to be packaged 10 is flush with the surface of the conductive post 112 away from the first die to be packaged 10.
In practical implementation, a distance between a surface of the second dielectric layer 113 away from the first die to be packaged 10 and a surface of the second dielectric layer 113 close to the first die to be packaged 10 may be greater than a distance between a surface of the conductive pillar 112 away from the first die to be packaged 10 and a surface of the conductive pillar 112 close to the first die to be packaged 10. After forming the second dielectric layer 113, the second dielectric layer 113 may be thinned until a surface of the second dielectric layer 113 away from the first die to be packaged 10 is flush with a surface of the conductive post 112 away from the first die to be packaged 10.
In step 210, a surface treatment layer is formed on the surfaces of the exposed conductive posts.
In the present embodiment, as shown in fig. 19, a surface treatment layer may be formed on the surface of the exposed conductive stud 112. Of course, in another embodiment, the surface treatment layer may not be formed on the surface of the conductive stud 112.
In step 211, the plastic package body is cut to obtain a semiconductor package structure.
In this embodiment, as shown in fig. 20, the plastic package body 20 is cut at the cutting line L, so as to obtain the semiconductor package structure shown in fig. 1. The semiconductor packaging structure comprises a first bare chip to be packaged 10, a second bare chip to be packaged 11, an inductance element 12, a conductive column 13, a plastic packaging layer 14, a first conductive trace 15 and a second conductive trace 16.
In the embodiment of the application, the inductance element is arranged on the back face of the first bare chip to be packaged, so that the first bare chip to be packaged and the inductance element are arranged in a stacked mode in the thickness direction of the first bare chip to be packaged, the space in the thickness direction of the first bare chip to be packaged is reasonably utilized, the structure of the semiconductor packaging structure can be compact, and the size of the semiconductor packaging structure is further reduced. Therefore, the semiconductor packaging structure in the embodiment of the application has small volume and compact structure, and is suitable for small-sized and light-weight electronic equipment.
In the present application, the apparatus embodiments and the method embodiments may complement each other without conflict. The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.
The present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

Claims (12)

1. A semiconductor packaging method, comprising:
fixing a first bare chip to be packaged, a second bare chip to be packaged and a conductive column on a carrier plate, wherein the front surface of the first bare chip to be packaged and the front surface of the second bare chip to be packaged face the carrier plate, the front surface of the first bare chip to be packaged is provided with a first welding pad, the front surface of the second bare chip to be packaged is provided with a second welding pad, the back surface of the first bare chip to be packaged is provided with an inductive element, the inductive element comprises a first electric connection point, the first electric connection point is positioned on one side, away from the first bare chip to be packaged, of the inductive element, and the conductive column is positioned between the first bare chip to be packaged and the second bare chip to be packaged; the conductive column comprises a first end and a second end, the first end is located at one end, close to the inductance element, of the conductive column, and the second end is located at one end, far away from the inductance element, of the conductive column;
forming a plastic package layer on the carrier plate, wherein the first die to be packaged, the second die to be packaged, the inductance element and the conductive posts are wrapped by the plastic package layer, and the first electrical connection points of the inductance element and the surfaces of the first ends of the conductive posts are respectively exposed out of the plastic package layer;
forming a first conductive trace on one side of the molding compound layer close to the back surface of the first bare chip to be packaged, wherein the first conductive trace connects the first electrical connection point of the inductance element and the first end of the conductive column;
removing the carrier plate;
and forming a second conductive trace on one side of the plastic packaging layer close to the front surface of the first die to be packaged, wherein the second conductive trace connects a second welding pad of the second die to be packaged with the second end of the conductive column.
2. The semiconductor packaging method according to claim 1, wherein before the fixing the first die to be packaged, the second die to be packaged, and the conductive pillars on the carrier, the method further comprises:
forming a first metal layer on the back of the silicon wafer through an electroplating process;
etching the first metal layer by an etching process to obtain the inductance element;
dividing the silicon wafer to obtain the first bare chip to be packaged; or,
before the first bare chip to be packaged, the second bare chip to be packaged and the conductive columns are fixed on the carrier plate, the method further comprises the following steps:
forming a seed layer on the back of the silicon wafer through a sputtering process;
forming a first metal layer on the seed layer through an electroplating process;
etching the first metal layer and the seed layer through an etching process to obtain the inductance element;
dividing the silicon wafer to obtain the first bare chip to be packaged;
the seed layer comprises a first seed layer and a second seed layer, the first seed layer is positioned on the silicon chip, the second seed layer is positioned on the first seed layer, the first seed layer is made of titanium, and the second seed layer is made of copper; or,
the seed layer comprises a second seed layer, and the second seed layer is made of copper.
3. The semiconductor packaging method according to claim 1, wherein a first protection layer is further formed on the front surface of the first die to be packaged;
a second protection layer is further formed on the front surface of the second die to be packaged; the distance between the surfaces of the first protective layer and the second protective layer, which are far away from the inductance element, and the surfaces of the inductance element, which are far away from the first protective layer, is smaller than the height of the conductive posts.
4. The semiconductor packaging method of claim 1, wherein the conductive posts are preformed; or,
forming a second metal layer on the carrier plate;
and etching the second metal layer by an etching process to obtain the conductive post.
5. The semiconductor packaging method of claim 1, wherein the forming of the molding layer on the carrier comprises:
forming an encapsulating layer on the carrier plate, wherein the encapsulating layer wraps the first bare chip to be packaged, the second bare chip to be packaged, the inductance element and the conductive columns, and the thickness of the encapsulating layer is greater than the heights of the conductive columns;
and thinning the encapsulating layer to obtain the plastic packaging layer, so that the first end of the conductive column is exposed out of the plastic packaging layer.
6. The semiconductor packaging method according to claim 1, wherein the molding layer includes a first opening thereon to expose the first electrical connection point of the inductance element;
and forming the first opening on the plastic packaging layer through a laser hole-opening process.
7. The semiconductor packaging method of claim 6, wherein forming a first conductive trace on a side of the molding compound layer near a back side of the first die to be packaged comprises:
filling a first conductive medium in the first opening to form a first conductive filling interface, and forming a first conductive layer on the plastic packaging layer; the first conductive filling interface is electrically connected with a first electrical connection point of the inductance element, and the first conductive layer is electrically connected with the first conductive filling interface;
patterning the first conductive layer to obtain the first conductive trace;
wherein the first conductive fill interface and the first conductive layer are formed in the same process step.
8. The semiconductor packaging method of claim 1, wherein after forming the first conductive traces on the molding layer on the side close to the back side of the first die to be packaged, further comprising:
forming a first dielectric layer on the first conductive trace, the first dielectric layer encapsulating the first conductive trace.
9. The semiconductor packaging method according to claim 3, further comprising:
forming a second opening on the first protection layer to expose the first bonding pad;
forming a third opening on the second protective layer to expose the second pad;
the step of forming the second opening on the first protective layer is located after the step of removing the carrier plate, or located after the step of forming the first protective layer on the front surface of the first die to be packaged and before the step of fixing the first die to be packaged, the second die to be packaged and the conductive pillar on the carrier plate;
the step of forming the third opening on the second protective layer is located after the step of removing the carrier plate, or located after the step of forming the second protective layer on the front side of the second die to be packaged and before the step of fixing the first die to be packaged, the second die to be packaged and the conductive pillar on the carrier plate;
when the first protection layer is made of a laser reaction type material, forming a second opening on the first protection layer through a laser hole forming process;
when the first protection layer is made of a photosensitive material, forming the second opening on the first protection layer through a photoetching process;
when the second protection layer is made of a laser reaction type material, forming the third opening on the second protection layer through a laser hole opening process;
and when the material of the second protective layer is a photosensitive material, forming the third opening on the second protective layer through a photoetching process.
10. The semiconductor packaging method according to claim 9, wherein the forming of the second conductive trace on the side of the molding compound layer close to the front side of the first die to be packaged comprises:
filling a second conductive medium into the second opening and the third opening to form a second conductive filling interface, and forming a second conductive layer on the plastic package layer, the first protective layer and the second protective layer; the second conductive filling interface is electrically connected with a first welding pad of the first bare chip to be packaged and a second welding pad of the second bare chip to be packaged respectively, and the second conductive layer is electrically connected with the second conductive filling interface;
patterning the second conductive layer to obtain the second conductive trace;
wherein the second conductive fill interface is formed in the same process step as the second conductive layer.
11. The semiconductor packaging method according to claim 1, wherein the second conductive trace comprises a second electrical connection point located on a side of the second conductive trace away from the first die to be packaged; after forming the second conductive traces on the side of the molding compound layer close to the front surface of the first die to be packaged, the method further comprises the following steps:
forming a conductive convex column on the second electric connection point;
forming a second dielectric layer on the second conductive trace and the conductive convex column to obtain a plastic package body; the second dielectric layer encasing the second conductive traces and the conductive posts, the conductive posts exposed from the second dielectric layer away from a surface of the first die to be packaged;
cutting the plastic package body to obtain a semiconductor package structure, wherein the semiconductor package structure comprises the first bare chip to be packaged, the second bare chip to be packaged, the inductance element, the conductive pillar, the plastic package layer, the first conductive trace and the second conductive trace, or,
after forming the second conductive traces on the side of the molding compound layer close to the front surface of the first die to be packaged, the method further comprises the following steps:
forming a conductive convex column on the second electric connection point;
forming a second dielectric layer on the second conductive trace and the conductive convex column to obtain a plastic package body; the second dielectric layer encasing the second conductive traces and the conductive posts, the conductive posts exposed from the second dielectric layer away from a surface of the first die to be packaged;
forming a surface treatment layer on the exposed surface of the conductive convex column;
and cutting the plastic package body to obtain a semiconductor package structure, wherein the semiconductor package structure comprises the first bare chip to be packaged, the second bare chip to be packaged, the inductance element, the conductive column, the plastic package layer, the first conductive trace and the second conductive trace.
12. A semiconductor package structure prepared by the semiconductor packaging method according to any one of claims 1 to 11, comprising:
the front surface of the first bare chip to be packaged is provided with a first welding pad, and the front surface of the second bare chip to be packaged is provided with a second welding pad;
the inductance element is positioned on the back surface of the first bare chip to be packaged; the inductance element comprises a first electric connection point, and the first electric connection point is positioned on one side of the inductance element, which is far away from the first bare chip to be packaged;
conductive pillars located between the first die to be packaged and the second die to be packaged; the conductive column comprises a first end and a second end, the first end is located at one end, close to the inductance element, of the conductive column, and the second end is located at one end, far away from the inductance element, of the conductive column;
the encapsulation layer wraps the first bare chip to be packaged, the second bare chip to be packaged, the inductance element and the conductive columns, and the first electric connection point of the inductance element, the surface of the first end of the conductive column and the surface of the second end of the conductive column are respectively exposed out of the encapsulation layer;
the first conductive trace is positioned on one side, close to the back surface of the first bare chip to be packaged, of the plastic packaging layer and is connected with the first electrical connection point of the inductance element and the first end of the conductive column;
and the second conductive trace is positioned on one side of the plastic packaging layer close to the front surface of the first bare chip to be packaged and is used for connecting a second welding pad of the second bare chip to be packaged with the second end of the conductive column.
CN202010669912.3A 2020-07-13 2020-07-13 Semiconductor packaging method and semiconductor packaging structure Pending CN113937013A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202010669912.3A CN113937013A (en) 2020-07-13 2020-07-13 Semiconductor packaging method and semiconductor packaging structure
PCT/CN2021/106011 WO2022012532A1 (en) 2020-07-13 2021-07-13 Semiconductor encapsulation method and semiconductor encapsulation structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010669912.3A CN113937013A (en) 2020-07-13 2020-07-13 Semiconductor packaging method and semiconductor packaging structure

Publications (1)

Publication Number Publication Date
CN113937013A true CN113937013A (en) 2022-01-14

Family

ID=79273664

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010669912.3A Pending CN113937013A (en) 2020-07-13 2020-07-13 Semiconductor packaging method and semiconductor packaging structure

Country Status (2)

Country Link
CN (1) CN113937013A (en)
WO (1) WO2022012532A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115064488A (en) * 2022-08-18 2022-09-16 成都复锦功率半导体技术发展有限公司 Chip interconnection packaging structure and preparation method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104617034B (en) * 2013-11-05 2018-05-01 中芯国际集成电路制造(上海)有限公司 Semiconductor package and forming method thereof
CN110854103B (en) * 2019-11-09 2021-04-16 北京工业大学 Embedded double-side interconnection power module packaging structure and manufacturing method
CN111029262A (en) * 2019-12-06 2020-04-17 上海先方半导体有限公司 Manufacturing method of chip packaging structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115064488A (en) * 2022-08-18 2022-09-16 成都复锦功率半导体技术发展有限公司 Chip interconnection packaging structure and preparation method thereof
CN115064488B (en) * 2022-08-18 2022-11-01 成都复锦功率半导体技术发展有限公司 Chip interconnection packaging structure and preparation method thereof

Also Published As

Publication number Publication date
WO2022012532A1 (en) 2022-01-20

Similar Documents

Publication Publication Date Title
US9196597B2 (en) Semiconductor package with single sided substrate design and manufacturing methods thereof
US6890829B2 (en) Fabrication of on-package and on-chip structure using build-up layer process
US9831219B2 (en) Manufacturing method of package structure
US20180166363A1 (en) Semiconductor package with electromagnetic interference shielding structures
CN108987380A (en) Conductive through hole in semiconductor package part and forming method thereof
KR20210134983A (en) Stacked Fully Molded Semiconductor Structure with Vertical Interconnects
KR102061342B1 (en) Package of electronic device with strengthened bump interconnection and method for manufacturing the same
TW201703212A (en) Chip package
TW201209991A (en) Stackable molded microelectronic packages with area array unit connectors
US20100314744A1 (en) Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof
US10986732B2 (en) Laminated circuit board, and electronic component
US20100078813A1 (en) Semiconductor module and method for manufacturing the semiconductor module
CN112713097A (en) Antenna packaging structure and packaging method
CN112713098A (en) Antenna packaging structure and packaging method
CN113937013A (en) Semiconductor packaging method and semiconductor packaging structure
US11398455B2 (en) Semiconductor devices and related methods
CN113937016A (en) Semiconductor packaging method and semiconductor packaging structure
CN109768032B (en) Antenna packaging structure and packaging method
CN114695316A (en) Three-dimensional package for semiconductor device and external component
CN113937015A (en) Semiconductor packaging method and semiconductor packaging structure
CN114420574B (en) Flexible packaging component and forming method thereof
CN113451161B (en) Semiconductor packaging method and semiconductor packaging structure
CN210692486U (en) Antenna packaging structure
CN109545691B (en) Manufacturing method of ultrathin fan-out type packaging structure
KR100548013B1 (en) Chip module for IC card and manufacturing method of the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination