CN113900843A

CN113900843A - Detection and repair method, device, equipment and readable storage medium

Info

Publication number: CN113900843A
Application number: CN202111049042.0A
Authority: CN
Inventors: 汪永鹏; 谭越
Original assignee: Lenovo Beijing Ltd
Current assignee: Lenovo Beijing Ltd
Priority date: 2021-09-08
Filing date: 2021-09-08
Publication date: 2022-01-07

Abstract

The application discloses a detection and repair method, a device, equipment and a readable storage medium, wherein the method comprises the following steps: and in response to the state that the memory of the local computer is not occupied, detecting the memory by adopting at least a first instruction to obtain a detection result, and repairing the memory by adopting at least a second instruction under the condition that the fault of the memory is determined according to the detection result. Through implementing this application, need not to disassemble electronic equipment, do not need extra test software and equipment just can detect and repair the memory fast, high-efficiently.

Description

Detection and repair method, device, equipment and readable storage medium

Technical Field

The present application relates to the field of fault repairing technologies, and in particular, to a method, an apparatus, a device, and a readable storage medium for detecting and repairing faults.

Background

At present, the memory needs to be disassembled from a computer for repairing the memory by a professional, and the memory is repaired by using specific test equipment and software, so that the efficiency is low.

Disclosure of Invention

In view of this, embodiments of the present application provide a method, an apparatus, a device, and a readable storage medium for detecting and repairing, so as to solve the problems that, in the prior art, when performing single-bit fault repair on a memory, the memory is disassembled from a computer, and a professional uses a specific test device and software to repair the memory, which is inefficient and affects the use experience for the memory.

In order to solve the above problem, in a first aspect, an embodiment of the present application provides a detection and repair method, including: responding to the state that the memory of the local computer is not occupied, and detecting the memory by adopting at least a first instruction to obtain a detection result; and under the condition that the fault of the memory is determined according to the detection result, repairing the memory by adopting at least a second instruction.

Optionally, the state that the local memory is not occupied includes that the memory is in an initialization proceeding stage and the local system process is in an ending stage.

Optionally, detecting memory with at least a first instruction comprises: a write operation and a read operation are performed on the memory with at least a first instruction.

Optionally, the method for detecting repair further includes: monitoring a third instruction for triggering the detection of the memory; and under the condition that the third instruction is monitored, detecting the memory by adopting at least the first instruction to obtain a detection result.

Optionally, in a case that it is determined that the memory has a fault according to the detection result, and between the time of repairing the memory by using at least the second instruction, the method for detecting and repairing further includes: generating a repair option according to the detection result; the user is presented with repair options.

Optionally, after presenting the repair option to the user, the method for detecting repair further includes: obtaining the confirmation operation of a user on the repair option; and repairing the memory by adopting at least a second instruction according to the confirmation operation.

Optionally, after the memory is repaired by using at least the second instruction, the method for detecting repair further includes: and displaying the repair result of the memory to a user.

Optionally, performing a write operation and a read operation on the memory with at least a first instruction, comprising: writing at least one detection paradigm into the memory; performing a first operation on a memory; reading the content in the memory; and comparing the content with the detection paradigm to obtain a detection result.

In a second aspect, an embodiment of the present application provides a device for detecting and repairing, including: the detection unit is used for responding to the unoccupied state of the local memory and detecting the local memory by adopting at least a first instruction to obtain a detection result; and the repair unit is used for repairing the memory by adopting at least a second instruction under the condition that the fault of the memory is determined according to the detection result.

In a third aspect, an embodiment of the present application provides an electronic device, including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the method of detecting repair as in the first aspect or any embodiment of the first aspect.

According to the detection and repair method, the device, the equipment and the readable storage medium, the memory is detected by adopting at least a first instruction in response to the state that the memory of the local computer is not occupied, the detection result is obtained, the memory is repaired by adopting at least a second instruction in the case that the memory is determined to have a fault according to the detection result, the electronic equipment is not required to be disassembled, extra test software and equipment are not required to detect and repair the fault of the memory of the electronic equipment, the memory fault can be quickly and efficiently detected and repaired on the local computer, the time cost and labor cost generated by disassembling, replacing and the like are saved, the maintenance cost of the memory is reduced, the memory fault can be timely detected and repaired, the loss of the memory fault to a user can be avoided, and the user experience is improved.

The foregoing description is only an overview of the technical solutions of the present application, and the present application can be implemented according to the content of the description in order to make the technical means of the present application more clearly understood, and the following detailed description of the present application is given in order to make the above and other objects, features, and advantages of the present application more clearly understandable.

Drawings

FIG. 1 is a schematic flow chart illustrating a method for detecting and repairing in an embodiment of the present application;

FIG. 2 is a schematic flow chart of another method for detecting repair in an embodiment of the present application;

FIG. 3 is a schematic flow chart of another detection and repair method in the embodiment of the present application

FIG. 4 is a flow chart showing the detection result and the repair result in the embodiment of the present application;

FIG. 5 is a schematic structural diagram of a device for testing and repairing in an embodiment of the present application;

fig. 6 is a schematic diagram of a hardware structure of an electronic device in an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The JESD79-4B DDR4 SDRAM standard of Joint Electron Device Engineering Council (JEDEC) requires DDR4 memory to support the PPR (post Package repair) feature, which all standard DDR4 dynamic random access memory (DDR4 DRAM) must comply with. This feature allows a user to repair single bit errors in memory cells that occur in memory with external software.

The memory cell in the memory is a 'small capacitor', 1 'small capacitor' stores 1bit of data, full charge represents '1', charge is discharged to represent '0', and 8G 'small capacitors' exist in 8Gb memory particles. The capacity of the memory particles is from 4Gb to 8Gb to 16Gb, and in the future, even more memories such as 24Gb and 32Gb exist. The larger capacity means that the number of the 'small capacitors' of the internal storage units is more, and for the same size of the internal storage, the smaller the volume of the 'small capacitors' is, the smaller the number of charges in the 'small capacitors' is, the poorer the anti-interference capability is, the unexpected change of the number of charges can change the stored 0 or 1 unexpectedly, and the unexpected change of the stored 0 or 1 is the 'single bit' fault.

Memory is one of the core components of an electronic device. At present, due to the continuous increase of the memory capacity of the electronic device, the probability of a single-bit failure occurring in a storage unit in the memory of the electronic device is increasing. When the single bit fault occurs in the memory, the memory needs to be dismounted from the electronic equipment, and a professional uses specific test equipment and software to repair the single bit fault of the memory, so that the efficiency is low.

In the single-bit repair process, the single-bit repair can be completed only by sending a corresponding control instruction to the memory. The inventor of the present application finds that the memory is completely controlled by the memory controller inside the CPU as a passive device. In the process of starting the electronic equipment, the memory controller initializes the memory, in the process of initializing the memory, the motion parameters of the memory can be changed, after the initialization is completed, the operation parameters of the memory are fixed and do not change in operation, and the controller does not allow to send instructions which can influence the normal operation of the memory and comprise PPR to the memory.

Therefore, the inventor of the present application thinks that the memory can be subjected to operations similar to parameter setting during the starting process of the electronic device, such as repairing the single-bit failure of the memory. Therefore, the single-bit fault of the memory can be directly repaired on the local computer without disassembling the local computer. Therefore, the embodiment of the application provides a detection and repair method, which can be applied to single-bit fault detection and repair of the memory of the electronic equipment.

As shown in fig. 1, the detection and repair method includes:

s101, in response to the state that the memory of the local computer is not occupied, detecting the memory by adopting at least a first instruction to obtain a detection result.

In particular, the local memory refers to the memory of the local computer, and does not include a removable memory. The state in which the local memory is unoccupied means a state in which any program is not running in the local memory. The state that the local memory is not occupied comprises that the memory is in an initialization proceeding stage and the local system process is in an ending stage. The memory is in the initialization stage, the local computer is in the starting up state, no program is run in the local computer, and the local computer memory is not occupied. The local machine system process is in the ending stage, the local machine is in the shutdown state, no program is run in the local machine memory, and the local machine memory is in the unoccupied state at this time.

In the state that the local memory is not occupied, the single-bit fault detection can be carried out on the storage units in the memory by 100 percent. In a state where the local memory is partially occupied, single-bit failure detection may be performed on the memory cells in the memory, but since part of the memory cells are occupied, 100% of the memory cells cannot be detected. Therefore, in the embodiment of the present application, in order to detect 100% of the memory cells in the memory, the memory is subjected to single-bit fault detection in a state where the local memory is not occupied.

The first instruction number is an instruction to perform single-bit failure detection on the memory. Currently, models dedicated to memory single bit fault detection are: 1) cell Dynamic Refresh Test (Cell Dynamic Refresh Test); 2) short period Test (Short tWR Test); 3) static Refresh Test (Static Refresh Test). Thus, the first instruction may be any one of the three models. Single bit failure detection of memory can be performed using any one or several of these three models.

When single-bit fault detection is performed on the memory by at least adopting the first instruction, the memory can enter an NEM (Non-even Mode) Mode of the CPU before initialization of the memory is completed, in the Mode, a core of the CPU can be directly called, and the concurrent and full-address detection can be performed on the memory by utilizing an L3Cache (L3Cache) and at least the first instruction cached in the L3 Cache.

In the embodiment of the application, the single-bit fault detection of the memory is carried out by utilizing the cache memory of the CPU, so that the speed is higher, and the single-bit fault detection of the memory can be completed in only a few minutes.

After single-bit fault detection is carried out on the memory, a detection result can be obtained. After the detection result is obtained, the detection result may be stored in a place where data is temporarily stored, for example, a Non-Volatile Random Access Memory (NVRAM) of a Basic Input Output System (BIOS), so as to perform single-bit fault repairing on the Memory in the following. NVRAM is a type of Random Access Memory (RAM) that retains data after power is removed. The detection result is stored in NVRAM and may be cached.

And S102, under the condition that the fault of the memory is determined according to the detection result, repairing the memory by adopting at least a second instruction.

Specifically, the second instruction is an instruction to perform single-bit fail-over on the memory. Currently, the model dedicated to memory single-bit fault repair is the PPR repair model. And judging whether the memory has single-bit faults or not according to the detection result, and if the memory has the single-bit faults, giving out not only prompt information but also fault addresses. If the memory has no single-bit fault, prompt information is also given. Therefore, when the memory is determined to have a single-bit fault according to the detection result, the memory cell at the fault address in the memory can be repaired by at least adopting the second instruction. When the memory is subjected to single-bit fault repair, a redundant row is used for replacing a damaged part of rows. And under the condition that the memory is determined to have no single-bit fault according to the detection result, the normal starting process and the normal shutdown starting process are carried out.

If the single-bit fault detection of the memory is carried out in the initialization stage of the memory, the single-bit fault repair of the memory is continuously carried out by at least adopting the second instruction before the initialization of the memory is completed. If the single-bit fault detection of the memory is carried out when the system process of the local computer is in the end stage, at the next starting-up, before the initialization of the memory is completed, at least a second instruction is adopted to carry out single-bit fault repair on the memory.

According to the detection and repair method provided by the embodiment of the application, the memory is detected by adopting at least a first instruction in response to the state that the memory of the local computer is not occupied, a detection result is obtained, the memory is repaired by adopting at least a second instruction in the case that the memory is determined to have a fault according to the detection result, the electronic equipment is not required to be disassembled, the memory of the electronic equipment is not required to be subjected to single-bit fault detection and repair by extra test software and equipment, the memory single-bit fault can be quickly and efficiently detected and repaired on the local computer, the time cost and labor cost generated by disassembling, replacing and the like are saved, the maintenance cost of the memory is reduced, the memory single-bit fault can be timely detected and repaired, the loss of the memory single-bit fault to a user can be avoided, and the user experience is improved.

In an optional embodiment, in step S101, detecting the memory by using at least a first instruction includes: a write operation and a read operation are performed on the memory with at least a first instruction.

Specifically, since the first instruction is an instruction for performing single-bit fault detection on the memory, at present, models specifically for performing single-bit fault detection on the memory include: 1) cell Dynamic Refresh Test (Cell Dynamic Refresh Test); 2) short period Test (Short tWR Test); 3) static Refresh Test (Static Refresh Test). The three models adopt a method of performing write operation and read operation on the memory to realize the detection of single-bit fault of the memory, so that the memory can be detected by performing write operation and read operation on the memory by adopting a model which is specially used for detecting the single-bit fault of the memory in the prior art.

In an alternative embodiment, performing a write operation and a read operation on a memory using at least a first instruction includes: writing at least one detection paradigm into the memory; performing a first operation on a memory; reading the content in the memory; and comparing the content with the detection paradigm to obtain a detection result.

Specifically, 010100101 can be written into the memory through Cell Dynamic Refresh Test, Short tWR Test and/or Static Refresh Test, after writing, the memory is repeatedly powered on or refreshed at longer intervals, and then the memory content is read. By comparing the written data with the read data, it can be determined whether there is a single bit failure in the memory.

For example, with Cell Dynamic Refresh Test writing 010100101 in memory, after writing, the read operation may be any of the following: 1. repeatedly powering up the memory, and reading the memory content to confirm whether the data is changed; 2. after writing, shortening the time to read, and judging whether the content is stored or not; 3. after the refreshing time is longer, the memory content is read again, because the memory can be refreshed dynamically to ensure that the content stored in the memory is not lost, the data can be lost when the memory is refreshed intentionally for a longer time than normal, a single-bit error occurs, and the lost data can be more when the memory with a single-bit fault is compared with the normal memory and the refreshing time is the same. By comparing the written data with the read data, it can be determined whether there is a single bit failure in the memory.

In this embodiment of the present application, since the single-bit failure detection model is optimally designed for detecting a single-bit failure, the detection accuracy is high, and therefore, the single-bit failure detection of the memory can be simply and accurately performed by performing the write operation and the read operation on the memory through the single-bit failure detection model.

In an optional embodiment, the method for detecting repair further includes: monitoring a third instruction for triggering the detection of the memory; and under the condition that the third instruction is monitored, detecting the memory by adopting at least the first instruction to obtain a detection result.

Specifically, the third instruction is a trigger instruction for performing single-bit failure detection on the memory. In the embodiment of the present application, the detection process of the memory may be automatically completed in the System starting process by designing a hot key triggering mode, setting the flag bit in the setting option of the BIOS, or giving a wmi (windows Management instrumentation) interface to the upper layer of the OS through a BIOS open interface, and then triggering the memory to perform single-bit fault detection in a mode of modifying the flag bit in a certain software of a computer Management control program (Operating System, OS). For example, a Ctrl + F5 hotkey is designed, when a system of the electronic device is started, the third instruction may be monitored in real time, and before the initialization of the memory is completed, if the user presses the hotkey Ctrl + F5, the electronic device obtains the third instruction, and if the third instruction is monitored, the memory may be detected by using at least the first instruction before the initialization of the memory is completed, so as to obtain a detection result. If the user presses the hotkey Ctrl + F5 after the initialization of the memory is completed, the electronic device obtains the third instruction, the computer may be restarted again, and before the initialization of the memory is completed, the memory is detected by using at least the first instruction, so as to obtain a detection result. If the user does not press the hot key Ctrl + F5, the electronic device does not obtain the third instruction, the system is normally started, and the memory single-bit fault detection is not performed.

In this embodiment of the application, the third instruction is designed to trigger the process of single-bit fault detection of the memory, so that a user can perform single-bit fault detection or not perform single-bit fault detection on the memory as required, and user experience is improved.

In an optional embodiment, in order to satisfy the user's right of selecting whether a single-bit failure is repaired or not, the method for detecting repair further includes, when it is determined that the memory has a failure according to the detection result, and between repairing the memory by using at least the second instruction: generating a repair option according to the detection result; the user is presented with repair options.

Generally, when the fault of the memory is determined according to the detection result, the memory is repaired by directly adopting at least the second instruction, so that the single-bit fault in the memory is repaired directly, and therefore, after the system is started, the memory can be used normally, the system can run stably, and system faults such as a blue screen, a dead halt and the like cannot occur. However, for some special situations, for example, when a user is in a hurry to start the system and the repair will necessarily require a certain time, the user can select the repair or the next repair according to his or her needs by showing the repair options to the user. The repair options may include options of repair, next repair, no repair, and the like, and may further include a failure address, content that needs to be repaired, and the like.

After the repair option is displayed to the user, if the user selects the repair, the confirmation operation of the user on the repair option can be obtained, and the memory is repaired by adopting at least a second instruction according to the confirmation operation. If the user selects the next repair, the memory can be repaired by adopting at least a second instruction in the process of starting up the computer next time. If the user chooses not to repair, the detection results in the cache may be deleted.

In the embodiment of the application, the repair options are generated according to the detection result, and are displayed to the user, so that the user can select whether to repair or not, the requirements of different users on single-bit fault repair can be met, and the user experience is improved.

In an optional embodiment, after the repairing the memory by using at least the second instruction, the method for detecting repair further includes: and displaying the repair result of the memory to a user.

Specifically, after a single bit failure is repaired, the repair result may be stored in NVRAM of the BIOS. After the BIOS has completed initialization of the memory and other input and output devices, such as a keyboard and a display, the detection and repair results are automatically displayed on the screen before starting the boot OS process.

The booting process of the OS is a process of entering an operating system of the electronic device after the electronic device initializes all hardware devices. The detection and repair result displayed at the stage is selected to be 1) because the use habit of the user is relatively met, the first interface displayed after the detection is started is the detection and repair result but not other pictures; 2) technically realizable and much simpler than entering the OS and then displaying the results.

In the embodiment of the application, the repair result of the memory is displayed to the user, so that the user can accurately know the single-bit fault repair result of the memory, and the user is prevented from using the electronic equipment to cause loss to the user when the single-bit fault repair is incomplete or not repaired.

In order to further explain the detection and repair method in the embodiment of the present application, the following description will be made by taking personal computing as an example.

Aiming at the memory characteristics of a PC system, a detection model aiming at single-bit faults can be added in a verification file (MRC) of a BIOS, and the detection model comprises 1) Cell Dynamic Refresh Test; 2) short tWR Test, 3) Static Refresh Test. Therefore, the BIOS detects not only the key specifications (model, frequency, capacity, etc.) of the memory, but also the internal quality (single bit failure) of the memory during the initialization process of the memory. When the internal quality of the memory is detected, before the initialization of the memory is completed, the memory enters an NEM (Non-Evict Mode) Mode of the CPU, in the Mode, the core of the CPU can be directly called, and the L3Cache is utilized to detect the concurrent and full address of the memory.

The conventional memory single-bit fault detection time is from ten minutes to several hours, in the embodiment of the application, the memory single-bit fault detection is performed by using the cache of the CPU, the speed is higher, and the memory single-bit fault detection can be completed in only a few minutes.

The flow of single bit failure detection and repair is shown in FIG. 2:

1. and adding a RAMPPR identification bit in the BIOS to identify whether the memory detection and repair process is triggered or not, and adding an identification bit of the PPRdone to identify whether the memory detection and repair process is finished or not. Rampr ═ 1 is triggered and rampr ═ 0 is not triggered. The RAMPR default is 0. PPRdone ═ 1 is complete, PPRdone ═ 0 is incomplete, and PPRdone has a default value of 0. During the system boot process, if the user presses Ctrl + F5 hot key, the rampr is marked as 1 in the BIOS code.

2. Before the initialization of the memory is completed, the RAMPR is detected to be 1, and a single-bit fault detection flow and a repair flow of the memory are automatically entered. As shown in fig. 3, when it is determined that single-bit failure detection needs to be performed on the memory, that is, when the rampr is 1, test models for Cell Dynamic Refresh, Short tWR, and Static Refresh are sequentially run, and address information of the single-bit failure is recorded when it is determined that the single-bit failure exists in the memory. For example BG-BA-CA-RA, then aiming at the address information of single bit failure, the PPR repair flow is operated to carry out single bit failure repair on the memory. And after the repair is finished, storing the detection result and the repair result into an NVRAM of the BIOS. And under the condition that the memory is judged to have no single-bit fault, directly storing the detection result into the NVRAM of the BIOS. The rampr is then set to 0 and the PPRdone to 1. When it is confirmed that the single-bit failure detection of the memory is not required, the single-bit failure detection is not performed.

3. After the initialization of the devices such as the memory, the display device, the keyboard and the mouse is completed, that is, the stage of the starting point is entered, at this stage, the BIOS may start to detect the operation action of the keyboard and control the display to output the display content, if at this stage, it may also detect whether the user has pressed the hot key Ctrl + F5, if it is detected that the user has pressed the hot key Ctrl + F5, the rampr may be marked as 1, the computer system is restarted, the value of the rampr is identified, at this time, the rampr is equal to 1, and then the process of detecting the single-bit fault in the memory is automatically entered. Single bit failure detection is again performed as per step 2.

4. And if the fact that the user presses the hot key Ctrl + F5 is not detected after the starting point stage is entered, detecting the value of the PPRdone, and if the PPRdone is detected to be 1, displaying the detection result and the repair result to the user, and setting the value of the PPRdone to be 0. If the user pressing the hot key Ctrl + F5 is not detected, and PPRdone is detected to be 0, the boot OS procedure is directly entered.

The process of presenting the detection result and the repair result to the user is shown in fig. 4, when it is detected that PPRdone is 1, an interface between the user and the UEFI system is entered, and the computer system can be configured by entering the interface. And then reading the detection result and the repair result from the NVRAM of the BIOS, displaying the detection result and the repair result to a user, and then setting the value of PPRdone to 0. And if the PPRdone is detected to be 1, directly ending.

In the embodiment of the application, the tool for detecting and repairing the memory is integrated in the BIOS code, and when the computer is started, the single-bit fault of the memory is detected and repaired in the memory initialization process, so that the computer does not need to be disassembled, and extra test software and equipment are not needed; the memory detection process is completed by using the NEM mode of the CPU, so that the speed is high and the efficiency is high; the detection model is designed for detecting single-bit faults, and the detection accuracy is high; and memory faults can be quickly repaired, loss brought to users is avoided, and user experience can be improved.

An embodiment of the present application provides a device for detecting and repairing, as shown in fig. 5, including:

the detection unit 21 is configured to detect the memory by using at least a first instruction in response to an unoccupied state of the local memory, and obtain a detection result; the detailed description of the specific implementation manner is given in step S101 of the above method embodiment, and is not repeated herein.

And the repair unit 22 is configured to repair the memory by using at least the second instruction when it is determined that the memory has a fault according to the detection result. The detailed description of the specific implementation manner is given in step S102 of the above method embodiment, and is not repeated herein.

The detection and repair device provided by the embodiment of the application adopts at least a first instruction to detect the memory by responding to the state that the memory of the local machine is not occupied, a detection result is obtained, the memory is repaired by adopting at least a second instruction under the condition that the memory is determined to have a fault according to the detection result, the electronic equipment is not required to be disassembled, the memory of the electronic equipment is not required to be subjected to single-bit fault detection and repair by extra test software and equipment, the memory single-bit fault can be quickly and efficiently detected and repaired on the local machine, the time cost and labor cost generated by disassembling, replacing and the like are saved, the maintenance cost of the memory is reduced, the memory single-bit fault can be timely detected and repaired, the loss of the memory single-bit fault to a user can be avoided, and the user experience is improved.

Based on the same inventive concept as the detection and repair method in the foregoing embodiment, an embodiment of the present application further provides an electronic device, as shown in fig. 6, including: a processor 31 and a memory 32, wherein the processor 31 and the memory 32 may be connected by a bus or other means, and the connection by the bus is illustrated in fig. 6 as an example.

The processor 31 may be a Central Processing Unit (CPU). The Processor 31 may also be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, or combinations thereof.

The memory 32, which is a non-transitory computer readable storage medium, may be used to store non-transitory software programs, non-transitory computer executable programs, and modules, such as program instructions/modules corresponding to the detection and repair method in the embodiments of the present application. The processor 31 executes various functional applications and data processing of the processor by executing non-transitory software programs, instructions and modules stored in the memory 32, that is, implements the detection and repair method in the above method embodiment.

The memory 32 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created by the processor 31, and the like. Further, the memory 32 may include high speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory 32 may optionally include memory located remotely from the processor 31, and these remote memories may be connected to the processor 31 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

One or more of the modules described above are stored in the memory 32 and, when executed by the processor 31, perform the detection repair method as in the embodiment shown in fig. 1.

The details of the electronic device may be understood with reference to the corresponding related description and effects in the embodiment shown in fig. 1, and are not described herein again.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a Hard Disk (Hard Disk Drive, abbreviated as HDD), a Solid State Drive (SSD), or the like; the storage medium may also comprise a combination of memories of the kind described above.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable information processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable information processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable information processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable information processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A method of detection repair comprising:

responding to the state that the memory of the local computer is not occupied, and detecting the memory by adopting at least a first instruction to obtain a detection result;

and under the condition that the memory is determined to have the fault according to the detection result, repairing the memory by adopting at least a second instruction.

2. The method of claim 1, wherein the state of unoccupied local memory comprises that the memory is in an initialization proceeding stage and the local system process is in an ending stage.

3. The method for detecting and repairing according to claim 1, wherein the detecting the memory by using the at least first instruction comprises:

and performing writing operation and reading operation on the memory by adopting at least a first instruction.

4. The inspection repair method according to claim 1, further comprising:

monitoring a third instruction for triggering the detection of the memory;

and under the condition that the third instruction is monitored, detecting the memory by adopting at least the first instruction to obtain a detection result.

5. The method according to claim 1, further comprising, in a case where it is determined that the memory has a failure according to the detection result, and between repairing the memory by using at least a second instruction:

generating a repair option according to the detection result;

and displaying the repair options to a user.

6. The method for detection repair of claim 5, after presenting the repair options to a user, further comprising:

obtaining the confirmation operation of the user on the repair option;

and repairing the memory by adopting at least a second instruction according to the confirmation operation.

7. The method according to claim 1, further comprising, after repairing the memory using at least a second instruction:

and displaying the repair result of the memory to a user.

8. The method for detecting and repairing according to claim 3, wherein the performing the write operation and the read operation on the memory by using at least the first instruction comprises:

writing at least one detection paradigm into the memory;

performing a first operation on the memory;

reading the content in the memory;

and comparing the content with the detection paradigm to obtain a detection result.

9. An inspection repair device comprising:

the detection unit is used for responding to the unoccupied state of the memory of the local computer and detecting the memory by adopting at least a first instruction to obtain a detection result;

and the repair unit is used for repairing the memory by adopting at least a second instruction under the condition that the fault of the memory is determined according to the detection result.

10. An electronic device, comprising:

at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the method of detecting repair of any of claims 1-8.