CN113900311A

CN113900311A - Pixel structure

Info

Publication number: CN113900311A
Application number: CN202111191248.7A
Authority: CN
Inventors: 罗谚桦; 蔡孟杰; 黄士杰; 黄馨谆
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2021-02-26
Filing date: 2021-10-13
Publication date: 2022-01-07
Anticipated expiration: 2041-10-13
Also published as: CN113900311B; TWI753788B; TW202234132A

Abstract

The invention discloses a pixel structure which comprises a substrate and sub-pixels. The sub-pixel is located on the substrate and has a first to a third penetration area and a first to a third reflection area. The sub-pixel comprises a first active element, a second active element, a first transparent electrode, a second transparent electrode and a first to a third reflection electrodes. The first transparent electrode is electrically connected to the first active device and extends from the first transmission region to the third transmission region. The second transparent electrode is electrically connected to the second active device and overlaps the second transmission region. The first reflective electrode is overlapped with the first reflective area and is electrically connected to the first transparent electrode. The second reflecting electrode is overlapped with the second reflecting area and is electrically connected to the second transparent electrode. The third reflective electrode is overlapped with the third reflective area and is electrically connected to the first transparent electrode.

Description

Pixel structure

Technical Field

The present invention relates to a pixel structure, and more particularly, to a pixel structure suitable for a transflective display.

Background

With the development of science and technology, portable electronic products, such as smart phones, tablet computers, watches, and the like, have become popular in human life. Generally, in order to make electronic products more portable, many manufacturers strive to reduce the size of the electronic products, which also limits the size and capacity of the batteries of portable electronic products. Therefore, in order to provide the electronic product with a sufficiently high endurance, it is very important to reduce the power consumed by the electronic product. In some electronic products with display functions, the transflective display technology emphasizing the power saving function and outdoor visibility is very competitive.

Disclosure of Invention

The invention provides a pixel structure, which has the advantages of high reflection area and high penetration area.

At least one embodiment of the present invention provides a pixel structure. The pixel structure comprises a first substrate and a first sub-pixel. The first sub-pixel is located on the first substrate and has a first transmissive region, a second transmissive region, a third transmissive region, a first reflective region, a second reflective region and a third reflective region. The first sub-pixel comprises a first active element, a second active element, a first transparent electrode, a second transparent electrode, a first reflective electrode, a second reflective electrode and a third reflective electrode. The first transparent electrode is electrically connected to the first active device and extends from the first transmission region to the third transmission region. The second transparent electrode is electrically connected to the second active device and overlaps the second transmission region. The first reflective electrode is overlapped with the first reflective area and is electrically connected to the first transparent electrode. The second reflecting electrode is overlapped with the second reflecting area and is electrically connected to the second transparent electrode. The third reflective electrode is overlapped with the third reflective area and is electrically connected to the first transparent electrode.

Drawings

Fig. 1A to 1I are schematic top views illustrating a manufacturing process of a pixel structure according to an embodiment of the invention;

fig. 2A to fig. 2I are schematic cross-sectional views illustrating a manufacturing process of a pixel structure according to an embodiment of the invention;

FIG. 3 is a schematic cross-sectional view of a pixel structure according to an embodiment of the invention;

fig. 4 is a schematic cross-sectional view of a pixel structure according to an embodiment of the invention.

Description of the symbols

100 first substrate

110a first semiconductor layer

112a, 118a, 112b, 118b source region

115a, 115b drain regions

113a, 117a, 113b, 117b channel region

110b second semiconductor layer

120. 140, 160 insulating layer

132a, 134a, 132b, 134b, the gate

152a, 158a, 152b, 158b source

155a, 155b drain electrode

170a first transparent electrode

172a, 176a, 172b block-shaped parts

176a, 176b connecting parts

170b second transparent electrode

180 flat layer

190a first reflective electrode

190b second reflective electrode

190c first reflective electrode

192a first connecting structure

192b second connecting structure

192c third connecting Structure

200 second substrate

210 light-shielding layer

220 color conversion element

230 coating

240 common electrode

LS light-shielding area

O, H opening

OP1 first opening

OP2 second opening

OP3 third opening

PX, PXa, PXb pixel structure

R1, R2, R3 regions

RF1 first reflection area

RF2 second reflection area

RF3 third reflection area

SP1 first sub-pixel

SP2 second sub-pixel

SP3 third sub-pixel

T1 first active element

T2 second active element

TH1 first through hole

TH2 second through hole

TH3 third through hole

TP1 first penetration zone

TP2 second penetration zone

TP3 third penetration zone

w1, w2, w3, w4, w5, w6 width

Detailed Description

Fig. 1A to 1I are schematic top views illustrating a manufacturing process of a pixel structure according to an embodiment of the invention. Fig. 2A to 2I are schematic cross-sectional views illustrating a manufacturing process of a pixel structure according to an embodiment of the invention, wherein fig. 2A to 2I correspond to portions of lines a-a ', B-B ' and C-C ' in fig. 1A to 1I.

Referring to fig. 1A and fig. 2A, a first semiconductor layer 110a and a second semiconductor layer 110b are formed on a first substrate 100. In the present embodiment, the pixel structure PX (shown in fig. 1I) includes a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 (shown in fig. 1I), and each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 includes a first semiconductor layer 110a and a second semiconductor layer 110 b.

The material of the first substrate 100 may be glass, quartz, organic polymer, or opaque/reflective material (e.g., conductive material, metal, wafer, ceramic or other suitable material) or other suitable material. If a conductive material or metal is used, an insulating layer (not shown) is formed on the first substrate 100 to prevent short circuit.

The first semiconductor layer 110a and the second semiconductor layer 110b are single-layer or multi-layer structures, and include amorphous silicon, polysilicon, microcrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials (such as indium zinc oxide, indium gallium zinc oxide, or other suitable materials or combinations thereof), or other suitable materials or combinations thereof.

In the present embodiment, the first semiconductor layer 110a includes a drain region 115a, a source region 112a, a source region 118a, a channel region 113a, and a channel region 117 a. The drain region 115a is located between the channel region 113a and the channel region 117a, the channel region 113a is located between the drain region 115a and the source region 112a, and the channel region 117a is located between the drain region 115a and the source region 118 a. The width w2 of the drain region 115a, the source region 112a, and the source region 118a is greater than the width w1 of the channel region 113a and the channel region 117a, making it easier to align/contact the drain region 115a, the source region 112a, and the source region 118a with other conductive elements.

In the present embodiment, the second semiconductor layer 110b includes a drain region 115b, a source region 112b, a source region 118b, a channel region 113b, and a channel region 117 b. The drain region 115b is located between the channel region 113b and the channel region 117b, the channel region 113b is located between the drain region 115b and the source region 112b, and the channel region 117b is located between the drain region 115b and the source region 118 b. The width w2 of the drain region 115b, the source region 112b, and the source region 118b is greater than the width w1 of the channel region 113b and the channel region 117b, making it easier to align/contact the drain region 115b, the source region 112b, and the source region 118b with other conductive elements.

In some embodiments, the first semiconductor layer 110a and the second semiconductor layer 110b of the same sub-pixel are aligned along the first direction DR1, but the invention is not limited thereto. In some embodiments, the first semiconductor layers 110a of the adjacent sub-pixels are aligned along the second direction DR2, and the second semiconductor layers 110b of the adjacent sub-pixels are aligned along the second direction DR2, but the invention is not limited thereto. The first direction DR1 is substantially perpendicular to the second direction DR 2.

Referring to fig. 1B and fig. 2B, an insulating layer 120 is formed on the first semiconductor layer 110a and the second semiconductor layer 110 a.

Gates

132a, 134a, 132b, 134b are formed on the insulating layer 120.

The gate 132a and the gate 134a overlap the channel region 113a and the channel region 117a of the first semiconductor layer 110a, respectively. The gate electrode 132b and the gate electrode 134b overlap the channel region 113b and the channel region 117b of the second semiconductor layer 110b, respectively.

In the present embodiment, the gate 132a and the gate 134a are electrically connected to a same scan line (not shown), and the scan line is, for example, directly or indirectly connected to the gate 132a and the gate 134 a. The gate 132b and the gate 134b are electrically connected to another scan line (not shown), which is directly or indirectly connected to the gate 132b and the gate 134b, for example.

In some embodiments, in the same pixel structure PX (shown in fig. 1I), the

gates

132a and 134a of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 (shown in fig. 1I) of different colors are electrically connected to the same scan line, and the

gates

132b and 134b of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 (shown in fig. 1I) of different colors are electrically connected to another scan line. In other words, each pixel structure PX includes two scan lines, wherein the two scan lines of adjacent pixel structures PX (e.g., the same column of pixel structures PX) are connected to each other.

Referring to fig. 1C and fig. 2C, an insulating layer 140 is formed on the

gates

132a, 134a, 132b, 134b and the insulating layer 120. The insulating layer 140 has a plurality of openings O, which overlap the drain region 115a, the source region 112a, and the source region 118a of the first semiconductor layer 110a and the drain region 115b, the source region 112ba, and the source region 118b of the second semiconductor layer 110b, respectively.

Referring to fig. 1C, fig. 1D and fig. 2D, a source 152a, a source 158a and a drain 155a are formed on the first semiconductor layer 110 a. The source 152a and the source 158a are respectively located at two sides of the drain 155 a. The source 152a and the source 158a are electrically connected to the source region 112a and the source region 118a of the first semiconductor layer 110a through the opening O, respectively, and the drain 155a is electrically connected to the drain region 115a of the first semiconductor layer 110a through the opening O. In other words, the first semiconductor layer 110a is electrically connected to the drain 155a, the source 152a and the source 158 a.

A source electrode 152b, a source electrode 158b, and a drain electrode 155b are formed on the second semiconductor layer 110 b. The source 152b and the source 158b are respectively located at two sides of the drain 155 b. The source 152b and the source 158b are electrically connected to the source region 112b and the source region 118b of the second semiconductor layer 110b through the opening O, respectively, and the drain 155b is electrically connected to the drain region 115b of the second semiconductor layer 110b through the opening O. In other words, the second semiconductor layer 110b is electrically connected to the drain electrode 155b, the source electrode 152b, and the source electrode 158 b.

In the present embodiment, the source 152a and the source 152b are directly connected, and the source 158a and the source 158b are directly connected. In the present embodiment, the source 152a, the source 152b, the source 158a and the source 158b are electrically connected to a same data line (not shown), for example, the data line is directly or indirectly connected to the source 152a, the source 152b, the source 158a and the source 158 b.

In the present embodiment, the first active device T1 includes a first semiconductor layer 110a, a gate 132a, a gate 134a, a source 152a, a source 158a, and a drain 155a, and the second active device T2 includes a second semiconductor layer 110b, a gate 132b, a gate 134b, a source 152b, a source 158b, and a drain 155 b. In the present embodiment, the first active device T1 and the second active device T2 are electrically connected to different scan lines, respectively. For example, the gate 132a and the gate 134a of the first active device T1 are electrically connected to the same first scan line, and the gate 132b and the gate 134b of the second active device T2 are electrically connected to the same second scan line.

In the present embodiment, in the same pixel structure PX (shown in fig. 1I), the source 152a and the source 158a of the first active device T1 of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 (shown in fig. 1I) and the source 152b and the source 158b of the second active device T2 are electrically connected to the same data line, and the first active device T1 and the second active device T2 of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 (shown in fig. 1I) of different colors are electrically connected to different data lines. For example, in one pixel structure PX, the source 152a and the source 158a of the first active device T1 of the first sub-pixel SP1 and the source 152b and the source 158b of the second active device T2 are electrically connected to the same first data line. In the second sub-pixel SP2, the source 152a and the source 158a of the first active device T1 and the source 152b and the source 158b of the second active device T2 are electrically connected to the same second data line. In the third sub-pixel SP3, the source 152a and the source 158a of the first active device T1 and the source 152b and the source 158b of the second active device T2 are electrically connected to the same third data line. In other words, each pixel structure PX includes three data lines, wherein the three data lines of adjacent pixel structures PX (e.g., the same row of pixel structures PX) are connected to each other.

In the embodiment, the first active device T1 and the second active device T2 are top gate thin film transistors, but the invention is not limited thereto. In other embodiments, the first active device T1 and the second active device T2 are bottom gate tfts, dual gate tfts, or other types of tfts.

Referring to fig. 1E and fig. 2E, an insulating layer 160 is formed on the insulating layer 140, the source 152a, the source 158a, the drain 155a, the source 152b, the source 158b, and the drain 155 b. The insulating layer 160 has a plurality of openings H overlapping the

drain electrodes

155a and 155b, respectively.

Referring to fig. 1E, fig. 1F and fig. 2F, a first transparent electrode 170a and a second transparent electrode 170b are formed on the insulating layer 160. The first transparent electrode 170a is electrically connected to the drain 155a of the first active device T1 through the opening H, and the second transparent electrode 170b is electrically connected to the drain 155b of the second active device T2 through the opening H.

In some embodiments, the material of the first transparent electrode 170a and the second transparent electrode 170b includes a metal oxide, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, or a stacked layer of at least two of the foregoing. In some embodiments, the thickness of the first and second

transparent electrodes

170a and 170b is 0.03 to 0.08 micrometers.

In the present embodiment, the first transparent electrode 170a includes a block portion 172a, a block portion 174a, and a connection portion 176 a. The width w4 of the block 172a and the block 174a is greater than the width w3 of the connecting portion 176a, and the connecting portion 176a connects the block 172a and the block 174 a. In the present embodiment, the block 172a and the block 174a are located at two ends of the connection portion 176a, and the connection portion 176a fills the opening H and is connected to the drain 155 a.

In the present embodiment, the second transparent electrode 170b includes a block portion 172b and a connection portion 176 b. The width w6 of the block 172b is greater than the width w5 of the connection portion 176b, the connection portion 176b connects the block 172b, and the connection portion 176b fills the opening H and is connected to the drain 155 b. In the present embodiment, the block 172b of the second transparent electrode 170b is located between the block 172a and the block 174a of the first transparent electrode 170a in the first direction DR 1.

Referring to fig. 1G and fig. 2G, a planarization layer 180 is formed on the first transparent electrode 170a, the second transparent electrode 170b and the insulating layer 160. The planarization layer 180 has a first opening OP1 overlapping the first transparent electrode 170a, a third opening OP3 overlapping the first transparent electrode 170a, and a second opening OP2 overlapping the second transparent electrode 170 b. In the present embodiment, the first opening OP1 overlaps the block 172a of the first transparent electrode 170a, the third opening OP3 overlaps the block 174a of the first transparent electrode 170a, and the second opening OP2 overlaps the block 172b of the second transparent electrode 170 b.

Referring to fig. 1H and fig. 2H, a first reflective electrode 190a, a second reflective electrode 190b and a third reflective electrode 190c are formed on the planarization layer 180. The first and third

reflective electrodes

190a and 190c are electrically connected to the first transparent electrode 170a, and the second reflective electrode 190b is electrically connected to the second transparent electrode 170 b. In some embodiments, the first reflective electrode 190a, the second reflective electrode 190b, and the third reflective electrode 190c include silver, aluminum, or an alloy thereof, or other conductive and reflective materials. In some embodiments, the thickness of the first, second, and third

reflective electrodes

190a, 190b, and 190c is 0.1 to 0.2 microns.

In the present embodiment, the first reflective electrode 190a is electrically connected to the first transparent electrode 170a through the first connection structure 192a in the first opening OP1, the third reflective electrode 190c is electrically connected to the first transparent electrode 170a through the third connection structure 192c in the third opening OP3, and the second reflective electrode 190b is electrically connected to the second transparent electrode 170b through the second connection structure 192b in the second opening OP 2.

In the present embodiment, the first connection structure 192a is integrally formed with the first reflective electrode 190a, and the first connection structure 192a has a first through hole TH1 overlapping the first opening OP 1. The second connection structure 192b is integrally formed with the second reflective electrode 190b, the second connection structure 192b has a second through hole TH2 overlapping the second opening OP2, the third connection structure 192c is integrally formed with the third reflective electrode 190c, and the third connection structure 192c has a third through hole TH3 overlapping the third opening OP 3.

In the present embodiment, the pixel structure PX includes a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 (shown in fig. 1I), and the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 each include a first reflective electrode 190a, a second reflective electrode 190b, and a third reflective electrode 190 c. In other words, the pixel structure PX includes three first reflective electrodes 190a, three second reflective electrodes 190b, and three third reflective electrodes 190 c. The three first reflective electrodes 190a, the three second reflective electrodes 190b, and the three third reflective electrodes 190c are structurally separated from each other.

Referring to fig. 1I and fig. 2I, a second substrate 200, a light-shielding layer 210, a color conversion element 220, a covering layer 230 and a common electrode 240 are provided, wherein the second substrate 200, the color conversion element 220, the covering layer 230 and the common electrode 240 are omitted from fig. 1I. The light-shielding layer 210 is disposed on the second substrate 200. The color conversion element 220 is disposed on the light-shielding layer 210 and the second substrate 200, and the color conversion element 220 is, for example, a filter element and/or a quantum dot material. The overcoat layer 230 is positioned on the color conversion element 220. The common electrode 240 is positioned on the capping layer 230. The liquid crystal layer (not shown) is disposed between the first substrate 100 and the second substrate 200.

In the present embodiment, the pixel structure PX includes a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3, and the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 correspond to sub-pixels of different colors, respectively. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 have color conversion elements 220 of different colors, respectively.

In the present embodiment, the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 are disposed on the first substrate 100, and the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 respectively have a first transmissive region TP1, a second transmissive region TP2, a third transmissive region TP3, a first reflective region RF1, a second reflective region RF2 and a third reflective region RF 3. In the present embodiment, each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 further has a light-shielding region LS.

The light blocking region LS is located between the first reflective region RF1 and the second reflective region RF2 and between the third reflective region RF3 and the second reflective region RF 2. In the present embodiment, the light-shielding region LS is defined by the light-shielding layer 210. The light shielding layer 210 overlaps the slit between the first and second

reflective electrodes

190a and 190b and the slit between the second and third

reflective electrodes

190b and 190c, thereby dividing a single sub-pixel (the first sub-pixel SP1, the second sub-pixel SP2, or the third sub-pixel SP3) into three regions R1, R2, R3. In the present embodiment, the region R1 includes a first reflection region RF1 and a first transmission region TP1, the region R2 includes a second reflection region RF2 and a second transmission region TP2, and the region R3 includes a third reflection region RF3 and a third transmission region TP 3. In the present embodiment, the first reflection region RF1, the second reflection region RF2 and the third reflection region RF3 respectively surround the first transmission region TP1, the second transmission region TP2 and the third transmission region TP 3. The second reflection region RF2 is located between the first reflection region RF1 and the third reflection region RF3, and the second transmission region TP2 is located between the first transmission region TP1 and the third transmission region TP 3.

Referring to fig. 1G, fig. 1I and fig. 2I, the first transparent electrode 170a extends from the first transmission region TP1 to the third transmission region TP 3. The second transparent electrode 170b overlaps the second penetration region TP 2. The first opening OP1 and the third opening OP3 of the planarization layer 180 are respectively located in the first penetration region TP1 and the third penetration region TP3, and the second opening OP2 of the planarization layer 180 is located in the second penetration region TP 2. The first reflective electrode 190a, the second reflective electrode 190b and the third reflective electrode 190c overlap the first reflective region RF1, the second reflective region RF2 and the third reflective region RF3, respectively.

The first through region TP1, the second through region TP2, and the third through region TP3 are respectively defined by the first through hole TH1 of the first connection structure 192a, the second through hole TH2 of the second connection structure 192b, and the third through hole TH2 of the third connection structure 192 c.

In the embodiment, light emitted from the backlight module (not shown) can pass through the pixel structure PX through the first transmissive region TP1, the second transmissive region TP2 and the third transmissive region TP3, and light externally irradiated into the pixel structure PX is reflected by the first reflective electrode 190a, the second reflective electrode 190b and the third reflective electrode 190c in the first reflective region RF1, the second reflective region RF2 and the third reflective region RF 3. In the embodiment, the light-shielding layer 210 does not overlap the first opening OP1, the second opening OP2 and the third opening OP3 of the planarization layer 180, so that the light-shielding layer 210 can be prevented from reducing the reflection area and the transmission area of the pixel structure PX, and thus the pixel structure PX has a high reflection area and a high transmission area.

Referring to fig. 1F, 1I and 2I, in the present embodiment, each of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 includes a region R1, a region R2 and a region R3, wherein the liquid crystal layer in the region R1 and the region R3 is controlled by the first active device T1, and the liquid crystal layer in the region R2 is controlled by the second active device T2. For example, when a black screen is required, the first active device T1 and the second active device T2 are controlled such that light cannot pass through the region R1, the region R2 and the region R3. When less brightness is required, the second active device T2 is controlled to allow light to pass through the region R2, and the first active device T1 is controlled to prevent light from passing through the region R1 and the region R3. When the larger brightness is needed, the second active device T2 is controlled not to let the light pass through the region R2, and the first active device T1 is controlled to let the light pass through the region R1 and the region R3. When the maximum brightness is required, the first active device T1 and the second active device T2 are controlled to allow light to pass through the region R1, the region R2 and the region R3.

In the present embodiment, the first active device T1 and the second active device T2 overlap the second reflection region RF2, thereby better utilizing the layout space. In the present embodiment, the drain 155a, the source 152a and the source 158a of the first active device T1 and the drain 155b, the source 152b and the source 158b of the second active device T2 overlap the second reflective region RF 2. In addition, the overlap of the drain 155a of the first active device T1 with the second reflective region RF2 can increase the aperture ratio design. Compared with the design of the first active device T1 in the first reflective region RF1, the displacement of the first active device T1 from the second reflective region RF2 increases the adjustable space of the pixel circuit layout, thereby providing a larger light transmission area.

In some embodiments, conductive lines (e.g., scan lines and data lines) electrically connected to the first active device T1 and the second active device T2 overlap the first reflective region RF1, the second reflective region RF2, the third reflective region RF3, and the light shielding region LS, so as to reduce the influence of the conductive lines on the transmittance of the pixel structure PX.

Fig. 3 is a schematic cross-sectional view of a pixel structure according to an embodiment of the invention.

It should be noted that the embodiment of fig. 3 follows the element numbers and partial contents of the embodiment of fig. 2A to 2I, wherein the same or similar elements are denoted by the same or similar reference numbers, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.

The difference between the pixel structure PXa of fig. 3 and the pixel structure PX of fig. 2I is: the materials of the first, second, and

third connection structures

192a, 192b, and 192c of the pixel structure PXa of fig. 3 are different from the materials of the first, second, and first

reflective electrodes

190a, 190b, and 190 c.

In the present embodiment, the first connection structure 192a, the second connection structure 192b and the third connection structure 192c are transparent conductive materials, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, or a stacked layer of at least two of the foregoing materials. In some embodiments, the materials of the first, second, and

third connection structures

192a, 192b, and 192c are the same as the materials of the first and second

transparent electrodes

170a and 170 b.

In the present embodiment, the first connection structure 192a covers a portion of the top surface of the first reflective electrode 190a, and the first connection structure 192a covers the top surface of the first transparent electrode 170a overlapping the first opening OP 1. The first reflective electrode 190a is electrically connected to the first transparent electrode 170a through the first connection structure 192a in the first opening OP 1. In the present embodiment, the width X1 of the portion of the top surface of the first connecting structure 192a covering the first reflective electrode 190a is less than or equal to 1.5 micrometers and greater than 0 micrometer, thereby preventing the first connecting structure 192a from reducing the reflectivity of the first reflective region RF 1. In addition, the first connection structure 192a covers a portion of the top surface of the first reflective electrode 190a, which can reduce the probability that the first reflective electrode 190a is not electrically connected to the first transparent electrode 170a due to the manufacturing process shift.

In the present embodiment, the second connection structure 192b covers a portion of the top surface of the second reflective electrode 190b, and the second connection structure 192b covers the top surface of the second transparent electrode 170b overlapping the second opening OP 2. The second reflective electrode 190b is electrically connected to the second transparent electrode 170b through the second connection structure 192b in the second opening OP 2. In the present embodiment, the width X1 of the portion of the top surface of the second connection structure 192b covering the second reflective electrode 190b is less than or equal to 1.5 micrometers and greater than 0 micrometer, thereby preventing the second connection structure 192b from reducing the reflectivity of the second reflective region RF 2. In addition, the second connection structure 192b covers a portion of the top surface of the second reflective electrode 190b to reduce the probability that the second reflective electrode 190b is not electrically connected to the second transparent electrode 170b due to the manufacturing process shift.

In the present embodiment, the third connecting structure 192c covers a portion of the top surface of the third reflective electrode 190c, and the third connecting structure 192c covers the top surface of the first transparent electrode 170a overlapping the third opening OP 3. The third reflective electrode 190c is electrically connected to the first transparent electrode 170a through the third connection structure 192c in the third opening OP 3. In the present embodiment, the width X1 of the portion of the top surface of the third connecting structure 192c covering the third reflective electrode 190c is less than or equal to 1.5 micrometers and greater than 0 micrometer, thereby preventing the third connecting structure 192c from reducing the reflectivity of the third reflective region RF 3. In addition, the third connection structure 192c covers a portion of the top surface of the third reflective electrode 190c, which can reduce the probability that the third reflective electrode 190c is not electrically connected to the first transparent electrode 170a due to the manufacturing process shift.

In some embodiments, the thickness of the transparent conductive material affects the transmittance, and the thickness with the highest transmittance depends on the properties of the material. In some embodiments, the thicknesses of the first connection structure 192a, the second connection structure 192b and the third connection structure 192c and the thicknesses of the first transparent electrode 170a and the second transparent electrode 170b are adjusted to optimize the transmittance of the first transmission region TP1, the second transmission region TP2 and the third transmission region TP 3. In some embodiments, the thicknesses of the first, second, and

third connection structures

192a, 192b, and 192c are the same or different from the thicknesses of the first and second

transparent electrodes

170a and 170 b.

In some embodiments, the material of the first transparent electrode 170a and the second transparent electrode 170b is indium tin oxide, and the thickness is 0.11 to 0.16 μm. In some embodiments, the material of the first connection structure 192a, the second connection structure 192b and the third connection structure 192c is ito, and the thickness is 0.11 to 0.16 μm.

It should be noted that the embodiment of fig. 4 follows the element numbers and partial contents of the embodiment of fig. 3, wherein the same or similar element numbers are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, which are not repeated herein.

The difference between the pixel structure PXb of fig. 4 and the pixel structure PXa of fig. 3 is: the first connection structure 192a of the pixel structure PXb of fig. 4 has a first through hole TH1 overlapping the first opening OP1, the second connection structure 192b has a second through hole TH2 overlapping the second opening OP2, and the third connection structure 192c has a third through hole TH3 overlapping the third opening OP 3.

In the present embodiment, the first through hole TH1, the second through hole TH2, and the third through hole TH3 are disposed to reduce the influence of the first connection structure 192a, the second connection structure 192b, and the third connection structure 192c on the transmittance of the first through region TP1, the second through region TP2, and the third through region TP 3.

In summary, the pixel structure of the present invention has the advantages of both the high reflection area and the high transmission area.

Claims

1. A pixel structure, comprising:

a first substrate; and

a first sub-pixel located on the first substrate and having a first transmissive region, a second transmissive region, a third transmissive region, a first reflective region, a second reflective region, and a third reflective region, wherein the first sub-pixel comprises:

a first active device and a second active device;

a first transparent electrode electrically connected to the first active device and extending from the first transmissive region to the third transmissive region;

a second transparent electrode electrically connected to the second active device and overlapping the second transmission region;

a first reflective electrode overlapping the first reflective region and electrically connected to the first transparent electrode;

a second reflective electrode overlapping the second reflective region and electrically connected to the second transparent electrode; and

and a third reflective electrode overlapping the third reflective region and electrically connected to the first transparent electrode.

2. The pixel structure of claim 1, wherein the second reflective region is located between the first reflective region and the third reflective region, the second transmissive region is located between the first transmissive region and the third transmissive region, and the first active device and the second active device overlap the second reflective region.

3. The pixel structure of claim 1, further comprising:

a flat layer located on the first transparent electrode and the second transparent electrode and having a first opening and a third opening overlapped with the first transparent electrode and a second opening overlapped with the second transparent electrode, wherein:

the first opening and the third opening are respectively positioned in the first penetrating region and the third penetrating region, the first reflective electrode is electrically connected with the first transparent electrode through a first connecting structure in the first opening, and the third reflective electrode is electrically connected with the first transparent electrode through a third connecting structure in the third opening; and is

The second opening is located in the second penetration region, and the second reflective electrode is electrically connected to the second transparent electrode through a second connection structure in the second opening.

4. The pixel structure of claim 3, wherein the first, second and third connecting structures are transparent conductive materials.

5. The pixel structure of claim 4, wherein the first connecting structure covers a portion of the top surface of the first reflective electrode, wherein a width of the portion of the top surface of the first connecting structure covering the first reflective electrode is less than or equal to 1.5 microns and greater than 0 micron, and the first connecting structure covers a top surface of the first transparent electrode overlapping the first opening.

6. The pixel structure of claim 4, wherein the first connection structure has a first via overlapping the first opening, the second connection structure has a second via overlapping the second opening, and the third connection structure has a third via overlapping the third opening.

7. The pixel structure of claim 3, wherein the first connecting structure is integrally formed with the first reflective electrode and has a first via overlapping the first opening, the second connecting structure is integrally formed with the second reflective electrode and has a second via overlapping the second opening, the third connecting structure is integrally formed with the third reflective electrode and has a third via overlapping the third opening.

8. The pixel structure of claim 1, wherein the first active device and the second active device each comprise:

a drain electrode overlapping the second reflective electrode;

the first source electrode and the second source electrode are respectively positioned at two sides of the drain electrode and are overlapped with the second reflecting electrode;

a semiconductor layer electrically connected to the drain electrode, the first source electrode and the second source electrode; and

the first grid and the second grid are overlapped with the semiconductor layer.

9. The pixel structure of claim 8, wherein the first source of the first active device and the second source of the first active device and the first source of the second active device and the second source of the second active device are electrically connected to a same data line.

10. The pixel structure of claim 8, wherein the first gate of the first active device and the second gate of the first active device are electrically connected to a same first scan line, and the first gate of the second active device and the second gate of the second active device are electrically connected to a same second scan line.

11. The pixel structure of claim 1, further comprising:

a second substrate overlapping the first substrate; and

and a light shielding layer on the second substrate and overlapping the slit between the first reflective electrode and the second reflective electrode and the slit between the second reflective electrode and the third reflective electrode, wherein the light shielding layer does not overlap the first opening, the second opening and the third opening.