CN113889969A - Circuit applied to multiple power domains - Google Patents
Circuit applied to multiple power domains Download PDFInfo
- Publication number
- CN113889969A CN113889969A CN202010628001.6A CN202010628001A CN113889969A CN 113889969 A CN113889969 A CN 113889969A CN 202010628001 A CN202010628001 A CN 202010628001A CN 113889969 A CN113889969 A CN 113889969A
- Authority
- CN
- China
- Prior art keywords
- circuit
- switch
- input signal
- circuit block
- feedback
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 18
- 238000010586 diagram Methods 0.000 description 8
- 230000003321 amplification Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000005236 sound signal Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/26—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to difference between voltages or between currents; responsive to phase angle between voltages or between currents
- H02H3/32—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to difference between voltages or between currents; responsive to phase angle between voltages or between currents involving comparison of the voltage or current values at corresponding points in different conductors of a single system, e.g. of currents in go and return conductors
Landscapes
- Amplifiers (AREA)
Abstract
The present disclosure relates to circuits applied in multiple power domains. The invention discloses a circuit applied to a plurality of power domains, which comprises a first circuit block and a second circuit block, wherein the first circuit block receives a first supply voltage from a first power domain, and the second circuit block receives a second supply voltage from a second power domain. The first circuit block comprises a first amplifier and a switch circuit, the first amplifier receives an input signal to generate a processed input signal, and the switch circuit transmits the processed input signal to the second circuit block when the second circuit block is powered by the second supply voltage; and the switch circuit disconnects a path between the first amplifier and the second circuit block when the second circuit block is not powered by the second supply voltage.
Description
Technical Field
The present invention relates to circuits for use in multiple power domains.
Background
In the cross-domain analog circuit, when a circuit block corresponding to one of the power domains does not need to operate or enters a sleep state, the power domain stops generating a supply voltage to save power consumption, however, a circuit block corresponding to the other power domains and still operating may have a leakage current flowing into the circuit block entering the sleep state, causing additional power consumption.
Disclosure of Invention
Therefore, one objective of the present invention is to provide a circuit applied in multiple power domains, which can effectively avoid leakage current between different circuit blocks to solve the problems in the prior art.
In one embodiment of the present invention, a circuit applied to a plurality of power domains is disclosed, which includes a first circuit block and a second circuit block, wherein the first circuit block receives a first supply voltage from a first power domain, and the second circuit block receives a second supply voltage from a second power domain. The first circuit block comprises a first amplifier and a switch circuit, the first amplifier receives an input signal to generate a processed input signal, and the switch circuit transmits the processed input signal to the second circuit block when the second circuit block is powered by the second supply voltage; and the switch circuit disconnects a path between the first amplifier and the second circuit block when the second circuit block is not powered by the second supply voltage.
In another embodiment of the present invention, a circuit is disclosed, which includes a first amplifier, a first switch, a second switch, a first feedback circuit, and a first circuit, wherein the first amplifier is configured to receive an input signal to generate a processed input signal, the first switch is used for selectively connecting an output terminal of the first amplifier to a first terminal, the second switch is used for selectively connecting the output terminal of the first amplifier to a second terminal, the first feedback circuit is used for receiving the processed input signal from the first switch to generate a first feedback signal to an input terminal of the first amplifier, and the second feedback circuit is used for receiving the processed input signal from the second switch to generate a second feedback signal to the input end of the first amplifier, wherein the first switch and the second switch are not simultaneously turned on.
Drawings
FIG. 1 is a diagram illustrating a circuit applied to multiple power domains according to an embodiment of the present invention.
Fig. 2 is a schematic diagram illustrating the operation of the circuit in a state where the first power domain and the second power domain are both normally powered.
FIG. 3 is a schematic diagram illustrating the operation of the circuit in a state where the first power domain is normally powered but the second power domain is not normally powered.
FIG. 4 is a diagram of a detection circuit according to an embodiment of the invention.
FIG. 5 is a schematic diagram of a circuit applied to a programmable amplifier.
FIG. 6 is a schematic diagram of a circuit applied to a programmable amplifier.
Detailed Description
FIG. 1 is a diagram of a circuit 100 for multiple power domains according to an embodiment of the invention. As shown in fig. 1, the circuit 100 includes a first circuit block 110 and a second circuit block 120, wherein the first circuit block 110 receives a first supply voltage AVDD1 from a first power domain, and the second circuit block 120 receives a second supply voltage AVDD2 from a second power domain. In the embodiment, the first circuit block 110 includes a first amplifier 112, a switch circuit, a first buffer 114_1, a second buffer 114_2, a first feedback circuit 116_1, a second feedback circuit 116_2 and an input resistor Rs1, wherein the switch circuit includes a first switch SW1 and a second switch SW2, the first switch SW1 is used to selectively connect the output terminal of the first amplifier 112 to the second circuit block 120 and the first feedback circuit 116_1, the second switch SW2 is used to selectively connect the output terminal of the first amplifier 112 to the second feedback circuit 116_2, the first feedback circuit 116_1 includes a resistor R1 and a third switch SW3, and the second feedback circuit 116_2 includes a resistor R2 and a fourth switch SW 4. In addition, the second circuit block 120 includes a second amplifier 122, an input resistor Rs2, and a feedback resistor RFB.
The operation of the circuit 100 can have two modes, in the first mode, the first circuit block 110 and the second circuit block 120 are respectively powered by the first supply voltage AVDD1 and the second supply voltage AVDD2, and the first amplifier 112 receives an input signal Vin from an input node Nin through the input resistor Rs1 and further receives a reference signal VCM1 to generate a processed input signal Vin'. At this time, under the normal power supplying state of the first power domain and the second power domain, the first switch SW1 and the third switch SW3 are turned on, and the second switch SW2 and the fourth switch SW4 are turned off, so that the first buffer 114_1 can receive the processed input signal Vin' from the first switch SW1 to generate a buffered processed input signal Vin "to the terminal N1, and the second amplifier 122 can receive the buffered processed input signal Vin" from the terminal N1 through the input resistor Rs2, and further receive a reference signal VCM2 to generate an output signal Vout at an output terminal Nout. Simultaneously, the first feedback circuit 116_1 receives the buffered processed input signal Vin ″ from the node N1 to generate a first feedback signal VFB1 to the negative input node of the first amplifier 112. In addition, since the second switch SW2 and the fourth switch SW4 are not turned on, the second feedback circuit 116_2 does not generate any feedback signal. Fig. 2 illustrates the operation of the circuit 100 in a state where both the first power domain and the second power domain are normally powered (elements without substantial operation are shown in dashed lines).
In the second mode, the first circuit block 110 is powered by the first supply voltage AVDD1 such that the input node Nin has a fixed dc voltage level, the second circuit block 120 is not powered by the second supply voltage VDD2 (e.g., the second circuit block 120 enters a sleep state), and the first amplifier 112 receives the input signal Vin from the input node Nin through the input resistor Rs1 and additionally receives the reference signal VCM1 to generate the processed input signal Vin'. At this time, in a state where the first power domain is normally powered but the second power domain is not powered, the first switch SW1 and the third switch SW3 are in a non-conducting state, and the second switch SW2 and the fourth switch SW4 are in a conducting state, so that the second buffer 114_2 can receive the signal Vin' to generate another buffered processed input signal to the terminal N2, and the second feedback circuit 116_2 receives the buffered processed input signal to generate a second feedback signal VFB2 to the negative input terminal of the first amplifier 112. In addition, since the first switch SW1 and the third switch SW3 are in the off state, the first switch SW1 and the third switch SW3 break the path between the first amplifier 112 and the second circuit block 120, so that no leakage current flows into the second circuit block 120 from the first circuit block 110; in addition, the first feedback circuit 116_1 does not generate any feedback signal. Fig. 3 illustrates the operation of the circuit 100 in a state where the first power domain is normally powered but the second power domain is not powered (elements without substantial operation are shown in dashed lines).
It should be noted that the amplifier 112 shown in fig. 1 is shown as an inverting type amplifier, however, this feature is not a limitation of the present invention. In other embodiments, the amplifier 112 may also be designed in a non-inverting type or a unity gain buffer type.
In one embodiment, the first circuit block 110 may further include a detection circuit for detecting whether the second supply voltage AVDD2 provided to the second amplifier 120 exists to generate a detection result to control the on and off of the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW 4. Specifically, fig. 4 is a schematic diagram of a detection circuit 400 according to an embodiment of the invention. As shown in fig. 4, the detection circuit 400 can be a comparator powered by the first supply voltage AVDD1 and used for comparing whether the second supply voltage AVDD2 is higher than a reference voltage VCM to generate the detection result DET. In this embodiment, when the detection result DET indicates that the second supply voltage is present, the detection result DET and the inverted signal thereof
The first switch SW1 and the third switch SW3 are controlled to be in a conducting state, and the second switch SW2 and the fourth switch SW4 are controlled to be in a non-conducting state, so that the second circuit block 120 can normally receiveTo the post-buffered input signal Vin "from node N1; and the detection result DET and its inverse signal
The first switch SW1 and the third switch SW3 are controlled to be in a non-conducting state, and the second switch SW2 and the fourth switch SW4 are controlled to be in a conducting state, so that the path between the first amplifier 122 and the second circuit block 120 is disconnected, and the first circuit block 110 can normally operate.
In one embodiment, the circuit 100 may be applied in an audio processing circuit in a desktop computer, a notebook computer, or a mobile device, and the input signal Vin may be an audio signal from a microphone. In an example, the input node Nin is also connected to a circuit node of the audio playing apparatus, so that, to avoid the pop sound caused by too large variation of the voltage level of the input node Nin, the first amplifier 110 will operate continuously to make the input node Nin have a fixed dc voltage level, so as to avoid the excessive variation of the voltage level of the input node Nin caused by the switching process between the sleep state and the normal state of the second circuit block 120 of the second power domain, and the circuit architecture provided by the present invention can effectively solve the problem of the leakage current of the second circuit block 120.
In one embodiment, the circuit 100 can be applied to a Programmable Amplifier (PGA) having a variable resistor, and is mainly configured to change the resistance of the input resistor Rs2 and the feedback resistor RFB of the second circuit block 120 to achieve amplification with different gains. Referring to the embodiments of fig. 5 and 6, the manner of adjusting the resistance value can be referred to, in which fig. 5 implements the input resistor Rs2 by using a plurality of resistors Rs 21-Rs 24 and a plurality of switches SWR 1-SWR 4, and implements the feedback resistor RFB by using a plurality of resistors RFB 1-RFB 4 and a plurality of switches SWF 1-SWF 4, and the resistance ratio can be determined by turning on/off the switches SWR 1-SWR 4 and SWR 1-SWR 4 in this embodiment. In the embodiment of fig. 5, although the switches SWR 1-SWR 4 and SWF 1-SWF 4 can be used to avoid the leakage under the above conditions, the Total Harmonic Distortion (THD) is increased due to the transistor switches in the signal path. Therefore, in consideration of the total harmonic distortion, the switches SWR 1-SWR 4 and SWF 1-SWF 4 are not placed, but in this way, the switches SWR 1-SWR 4 and SWF 1-SWF 4 cannot be closed to avoid the leakage current. In the embodiment shown in fig. 6, the input resistor Rs2 and the feedback resistor RFB are implemented by using a plurality of resistors R11-R15 and a plurality of switches SW 11-SW 14, in this embodiment, the sum of the input resistor Rs2 and the feedback resistor RFB is a fixed value, and the ratio of the resistance values can be adjusted and controlled by selecting a switch to connect to the negative terminal of the amplifier 122. The embodiment of fig. 6 can avoid the disadvantage of bad total harmonic distortion caused by the serial switches on the signal path in the embodiment of fig. 5, but since there is no switch in the second circuit block 120 of the embodiment of fig. 6 to disconnect the node N1 from the output terminal, the leakage current problem of the programmable amplifier with variable resistance can be effectively solved without reducing the total harmonic distortion performance by matching with the first circuit block 110 in the first power domain proposed by the present invention.
Briefly summarized, in the circuit applied to multiple power domains of the present invention, the leakage current problem of the leakage current between different circuit blocks can be effectively avoided by detecting whether the second supply voltage disappears to determine whether to disconnect the path between the first circuit block and the second circuit block.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should be covered by the present invention.
[ notation ] to show
100 circuit
110 first circuit block
112 first amplifier
114_1 first buffer
114_2 second buffer
116_1 first feedback circuit
116_2 second feedback circuit
120 second circuit block
122 second amplifier
400 detection circuit
AVDD1 first supply voltage
AVDD2 second supply voltage
DET, detection result
N1 endpoint
N2 endpoint
Nin, input terminal
Nout output terminal
R1 resistance
R2 resistance
RFB feedback resistor
Rs1 input resistor
Rs2 input resistor
SW1 first switch
SW2 second switch
SW3 third switch
SW4 fourth switch
VCM reference voltage
VCM1 reference signal
VCM2 reference signal
VFB1 first feedback signal
VFB2 second feedback signal
Vin is the input signal
Vin' is the processed input signal
Vin ″, which is the input signal after buffering and post-processing
Vout output signal
Claims (10)
1. A circuit for use in multiple power domains, comprising:
a first circuit block, wherein the first circuit block receives a first supply voltage from a first power domain;
a second circuit block, wherein the second circuit block receives a second supply voltage from a second power domain;
wherein the first circuit block comprises:
a first amplifier for receiving an input signal to generate a processed input signal; and
a switch circuit, wherein when the second circuit block is powered by the second supply voltage, the switch circuit transmits the processed input signal to the second circuit block; and when the second circuit block is not powered by the second supply voltage, the switch circuit disconnects a path between the second circuit block and the switch circuit.
2. The circuit of claim 1, wherein the first circuit block further comprises:
a detection circuit for detecting whether the second supply voltage provided to the second circuit block exists to generate a detection result;
the switch circuit selectively transmits the processed input signal to the second circuit block or disconnects a path between the switch circuit and the second circuit block according to the detection result.
3. The circuit of claim 1, further comprising:
a first feedback circuit, wherein when the second circuit block is powered by the second supply voltage, the first feedback circuit generates a first feedback signal to an input terminal of the first amplifier according to the processed input signal; and
a second feedback circuit, wherein when the second circuit block is not powered by the second supply voltage, the second feedback circuit generates a second feedback signal to the input terminal of the first amplifier according to the processed input signal.
4. The circuit of claim 3, wherein the switching circuit comprises:
a first switch for selectively connecting an output terminal of the first amplifier to the second circuit block and the first feedback circuit; and
a second switch for selectively connecting the output terminal of the first amplifier to the second feedback circuit.
5. The circuit of claim 4, wherein when the second circuit block is powered by the second supply voltage, the first switch is turned on so that the second circuit block and the first feedback circuit receive the processed input signal, and the second switch is turned off so that the second feedback circuit cannot receive the processed input signal; and when the second circuit block is not powered by the second supply voltage, the first switch is not turned on so that the second circuit block and the first feedback circuit cannot receive the processed input signal, and the second switch is turned on so that the second feedback circuit generates the second feedback signal according to the processed input signal.
6. The circuit of claim 4, further comprising:
a first buffer coupled to the first switch for receiving the processed input signal from the first switch to generate a buffered processed input signal to the second circuit block and the first feedback circuit; and
a second buffer, coupled to the second switch, for receiving the processed input signal from the first switch to generate another buffered processed input signal to the second feedback circuit.
7. The circuit of any of claims 3, 4, 5 or 6, wherein the first feedback circuit comprises a third switch for selectively transmitting the first feedback signal to the input of the first amplifier.
8. The circuit of claim 1, wherein the second circuit block comprises a second amplifier for receiving the processed input signal to generate an output signal.
9. A circuit, comprising:
a first amplifier for receiving an input signal to generate a processed input signal;
a first switch for selectively connecting an output terminal of the first amplifier to a first terminal;
a second switch for selectively connecting the output terminal of the first amplifier to a second terminal;
a first feedback circuit coupled to the first terminal for receiving the processed input signal from the first switch to generate a first feedback signal to an input of the first amplifier; and
a second feedback circuit, coupled to the second terminal, for receiving the processed input signal from the second switch to generate a second feedback signal to the input terminal of the first amplifier;
wherein the first switch and the second switch are not turned on simultaneously.
10. The circuit of claim 9, further comprising:
a detection circuit for detecting whether a supply voltage of a circuit block connected to the first terminal exists to generate a detection result;
when the detection result indicates that the supply voltage of the circuit block exists, the first switch is turned on so that the first feedback circuit receives the processed input signal from the first switch to generate the first feedback signal, and the second switch is turned off so that the second feedback circuit cannot receive the processed input signal; and when the detection result indicates that the supply voltage of the circuit block does not exist, the first switch is not turned on so that the first feedback circuit cannot receive the processed input signal, and the second switch is turned on so that the second feedback circuit receives the processed input signal to generate the second feedback signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010628001.6A CN113889969A (en) | 2020-07-02 | 2020-07-02 | Circuit applied to multiple power domains |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010628001.6A CN113889969A (en) | 2020-07-02 | 2020-07-02 | Circuit applied to multiple power domains |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113889969A true CN113889969A (en) | 2022-01-04 |
Family
ID=79012421
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010628001.6A Pending CN113889969A (en) | 2020-07-02 | 2020-07-02 | Circuit applied to multiple power domains |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113889969A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6476678B1 (en) * | 2000-08-04 | 2002-11-05 | Maxim Integrated Products, Inc. | High performance amplifier circuits using separate power supplies |
| KR20070089439A (en) * | 2006-02-28 | 2007-08-31 | 삼성전자주식회사 | Semiconductor integrated cirtuit having plularity of power domains |
| JP2013093666A (en) * | 2011-10-24 | 2013-05-16 | Rohm Co Ltd | Audio signal processing circuit and electronic apparatus using the same |
| US8587374B2 (en) * | 2009-10-30 | 2013-11-19 | St-Ericsson Sa | Amplifier activation |
| CN107017848A (en) * | 2016-01-27 | 2017-08-04 | 络达科技股份有限公司 | Power amplifying circuit and operation method thereof |
| CN108231113A (en) * | 2016-12-15 | 2018-06-29 | 台湾积体电路制造股份有限公司 | Double track device and its operating method with Power supply detector |
| CN111244890A (en) * | 2020-02-24 | 2020-06-05 | 成都世纪天知科技有限公司 | Anti-creeping circuit for communication between chips |
-
2020
- 2020-07-02 CN CN202010628001.6A patent/CN113889969A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6476678B1 (en) * | 2000-08-04 | 2002-11-05 | Maxim Integrated Products, Inc. | High performance amplifier circuits using separate power supplies |
| KR20070089439A (en) * | 2006-02-28 | 2007-08-31 | 삼성전자주식회사 | Semiconductor integrated cirtuit having plularity of power domains |
| US8587374B2 (en) * | 2009-10-30 | 2013-11-19 | St-Ericsson Sa | Amplifier activation |
| JP2013093666A (en) * | 2011-10-24 | 2013-05-16 | Rohm Co Ltd | Audio signal processing circuit and electronic apparatus using the same |
| CN107017848A (en) * | 2016-01-27 | 2017-08-04 | 络达科技股份有限公司 | Power amplifying circuit and operation method thereof |
| CN108231113A (en) * | 2016-12-15 | 2018-06-29 | 台湾积体电路制造股份有限公司 | Double track device and its operating method with Power supply detector |
| CN111244890A (en) * | 2020-02-24 | 2020-06-05 | 成都世纪天知科技有限公司 | Anti-creeping circuit for communication between chips |
Non-Patent Citations (1)
| Title |
|---|
| 瓦西琴柯等: "《模拟电路的ESD设计》", 31 January 2014, 国防工业出版社, pages: 226 - 227 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106549644B (en) | Amplifier system | |
| US20170207755A1 (en) | Switched mode converter with variable common mode voltage buffer | |
| US20060093153A1 (en) | Speaker driving device and audio output system | |
| US8072266B1 (en) | Class G amplifier with improved supply rail transition control | |
| US10333473B1 (en) | Stabilizing high performance audio amplifiers | |
| CA2016001C (en) | Low impedance buffer circuitry | |
| US9301046B1 (en) | Systems and methods for minimizing distortion in an audio output stage | |
| WO2017160556A1 (en) | Generation of voltage reference signals in a hybrid switched mode amplifier | |
| JP4294721B2 (en) | Video signal output circuit and semiconductor integrated circuit having the same | |
| US20120093340A1 (en) | Variable directional microphone unit and variable directional microphone | |
| CN113889969A (en) | Circuit applied to multiple power domains | |
| US11719728B2 (en) | Apparatus and system for wide-range current sensing | |
| US20090102551A1 (en) | Operational amplifier with improved current monitoring and scalable output | |
| US11611317B2 (en) | Circuitry applied to multiple power domains | |
| US7583144B1 (en) | Power efficient programmable amplifier | |
| JP4027981B2 (en) | Bridge amplifier with load feedback | |
| US7471151B2 (en) | Circuits for quiescent current control | |
| CN114003079B (en) | Circuit applied to multiple power domains | |
| CN111900941A (en) | Amplifier with a high-frequency amplifier | |
| CN115298945B (en) | Detection and protection of short circuits between power supplies in Y-bridge driver | |
| US11693474B2 (en) | Circuitry applied to multiple power domains | |
| JP3830534B2 (en) | Line driver with adaptive output impedance | |
| US6137361A (en) | Low power class A amplifier circuit | |
| JP3830535B2 (en) | Line driver with adaptive output impedance | |
| CN115987272A (en) | Signal receiver |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |