CN111244890A

CN111244890A - Anti-creeping circuit for communication between chips

Info

Publication number: CN111244890A
Application number: CN202010112712.8A
Authority: CN
Inventors: 肖建辉
Original assignee: Chengdu Century Tianzhi Technology Co Ltd
Current assignee: Chengdu Century Tianzhi Technology Co Ltd
Priority date: 2020-02-24
Filing date: 2020-02-24
Publication date: 2020-06-05
Anticipated expiration: 2040-02-24
Also published as: CN111244890B

Abstract

The invention discloses an anti-leakage circuit for communication between chips, which is applied to the field of integrated circuits and aims at the leakage phenomenon caused by output mismatching in a multi-chip communication system; the invention provides an anti-leakage circuit topological structure which can cut off a current loop between a power supply chip and a non-power supply chip, thereby avoiding the generation of a leakage phenomenon.

Description

Anti-creeping circuit for communication between chips

Technical Field

The invention belongs to the field of integrated circuit structures, and particularly relates to a technology for preventing chip electric leakage during communication between a master chip and a slave chip.

Background

In a multi-chip communication system, in order to save power consumption, there is often an application scenario where part of the chips are powered and part of the chips are not powered. In such an application scenario, a leakage phenomenon caused by output mismatch is often encountered, so that the purpose of saving power consumption is not achieved.

Disclosure of Invention

In order to solve the above technical problems, the present invention provides an anti-creeping circuit for communication between chips.

The technical scheme adopted by the invention is as follows: an anti-creeping circuit topology, comprising: the system comprises a power supply, an LDO/DC-DC, an abnormal power supply domain chip, a normal power supply domain chip, an SLAVE chip and a long power supply VDDS, wherein the SLAVE chip outputs a WAKE signal to the normal power supply domain chip; after the communication is finished, the WAKE is invalid;

further comprising: and the anti-creeping circuit is arranged between the MCU0 chip and the non-power supply domain chip.

The anticreep circuit is arranged in the SLAVE chip.

The invention also provides an anti-creeping circuit based on the topological structure, which comprises: the power supply system comprises a constant power supply domain chip circuit, a constant power supply domain chip interface circuit and an abnormal power supply domain chip circuit; the output of the chip circuit of the constant power supply domain is used as the input of the chip interface circuit of the constant power supply domain, and the output of the chip interface circuit of the constant power supply domain is used as the input of the chip circuit of the abnormal power supply domain;

the power supply domain chip interface circuit frequently includes: the power supply comprises a PMOS (P-channel metal oxide semiconductor), an NMOS (N-channel metal oxide semiconductor), an AND gate, a PESDMOS (bipolar-emitter-transistor MOS), an NESDMOS, a first inverter and a second inverter, wherein the first inverter and the second inverter are connected in series, a voltage VDD0 is used as the input of the first inverter, and the output of the first inverter is connected with the input of the second inverter;

the output of the first reverser is also connected with the grid electrode of the PMOS, the drain electrode of the PMOS is connected with the input end of the chip interface circuit of the normal power supply domain through a resistor R0, the source electrode of the PMOS is connected with the grid electrode of the PESDMOS, the grid electrode and the source electrode of the PESDMOS are in short circuit, and the drain electrode of the PESDMOS is connected with the output end of the chip interface circuit of the normal power supply domain;

the output of the second inverter is connected with the grid electrode of the NMOS, the drain electrode of the NMOS is connected with the input end of the interface circuit of the chip in the normal power supply domain through a resistor R1, the source electrode of the NMOS is connected with the grid electrode of the NESDMOS, the grid electrode of the NESDMOS is in short circuit with the source electrode, and the drain electrode of the NESDMOS is connected with the output end of the interface circuit of the chip in the normal power supply domain;

the input end of the interface circuit of the chip in the normal power supply domain is used as the first input end of the AND gate, the second input end of the AND gate is connected with VDD0, and the output end of the AND gate is used as the output end of the interface circuit of the chip in the normal power supply domain.

R0:R1>1:3。

The invention has the beneficial effects that: the invention provides two anti-creeping circuit topologies by improving the existing anti-creeping circuit topology structure for inter-chip communication, wherein one anti-creeping circuit is arranged between a normal power supply domain chip MCU0 and an abnormal power supply domain MASTER chip, and the other anti-creeping circuit is arranged in a normal power supply SLAVE chip, and the normal power supply domain chip interface circuit comprises: the PMOS, the NMOS, the AND gate, the PESDMOS, the NESDMOS, the first reverser and the second reverser do not generate electric leakage no matter whether VDD0 is electrified or not by forming a high-resistance branch; the anticreeping circuit of the invention can be realized on a PCB printed circuit board and also can be realized in an integrated circuit IC chip.

Drawings

FIG. 1 illustrates a conventional multi-chip communication application;

FIG. 2 is a schematic diagram of leakage in a conventional multi-chip communication;

FIG. 3 is a first topology of a leakage protection circuit according to the present invention;

FIG. 4 is a second topology of the anti-creeping circuit according to the present invention;

FIG. 5 is a circuit diagram of the present invention for preventing current leakage;

reference numerals: a power supply VSUP is 10, LDO/DC-DC is 11, MCU0 is 12, MASTER is 13, and SLAVE chip is 14; 20 is a long power supply domain chip, 21 is an abnormal power supply domain chip, 22 is PMOS drain open circuit output, 23 is Push-Pull output, 24 is NMOS drain open circuit output, 25 is PESDMOS, 26 is input buffer BUF of the abnormal power supply domain, 27 is NESDMOS, 28 is a first leakage current path, and 29 is a second leakage current path; 31 denotes an anti-leakage circuit, 41 denotes an anti-leakage circuit, 50 denotes a normally-powered domain chip, 51 denotes a normally-powered domain chip interface section, 52 denotes a non-powered domain chip, 510 denotes a PMOS1, 511 denotes an NMOS1, 512 denotes an R0, 513 denotes an R1, 514 denotes an and gate, 515 denotes a first inverter, 516 denotes a second inverter, 517 denotes a PESDMOS, 518 denotes a NESDMOS, 520 denotes an output of the and

gate

514, 521 denotes a PESDMOS2, 522 denotes a NESDMOS1, 523 denotes an output of 520, and 524 denotes a BUF.

Detailed Description

FIG. 1 is a typical multi-chip communication application scheme where VSUP is the power supply for the entire system, LDO/DC-DC is a voltage generation or control circuit, and VDDM is generated by the LDO/DC-DC to power the MASTER chip. But only when PD is active, VDDM has a voltage output, i.e., the condition that triggers VDDM to be powered is that the SLAVE chip outputs the WAKE signal; when the WAKE signal is active, the MCU0 outputs the PD signal to LDO/DC-DC, which supplies VDDM to the MASTER chip, and then TX0/RX0, TX1/RX1 in FIG. 1 starts communication; after the communication is completed, the WAKE signal is disabled, and the PD turns off the LDO/DCtoDC circuit. In the whole work flow, in order to save power, the supply VDDM of the MASTER works only after the WAKE signal WAKEs up the PD, so that the situation that VDDM is not powered for a long time, and VSUP and VDDS are powered exists. The actual circuit configuration in this case is shown in fig. 2.

VDDS in fig. 1 is the long power supply that supplies the SLAVE chip.

Fig. 2 is a schematic diagram of leakage of multi-chip communication in the prior art. Wherein 20 is a long power domain chip, and the power supply of the normal power domain chip is VDD 1. The output of VDD1 is generally divided into three types: PMOS drain open output, Push-Pull output, NMOS drain open output.

PMOS2 shows a PMOS open drain output in fig. 2 with its input at VIN0 and its output at OUT 0.

BUF1 represents a Push-Pull output, with the input being VIN1 and the output being OUT 1.

NMOS2 represents an NMOS open drain output with its input at VIN2 and its output at OUT 2.

The three paths of outputs cannot appear at one IO output port, and the general IO output port is only one condition. Denoted 21 is a very power domain chip. Conventional IO devices have ESD protection circuits, consisting of PESDMOS and NESDMOS. The gate and source of the PESDMOS are shorted, and the gate and source of the NESDMOS are shorted. 26 is the input buffer BUF of the very power supply domain. And finally outputting the OUT signal to the inside of the power supply domain chip. When PMOS2 VIN0 is low and VDD0 is unpowered (i.e., VDD0 is floating), a leakage path is formed from VDD1 to VDD0, and VDD0 carries a voltage, which results in chip leakage in the very power domain. There is also a case where VDD0 is grounded, a path to ground is formed from VDD1 to VDD0, and leakage is also formed, and 28 denotes a current path for such leakage; when the BUF default output is high, the same situation as when the PMOS2 open drain output is high results in a leakage path 29. Therefore, an isolation circuit needs to be added between the power domain chips to prevent the leakage.

The anti-creeping circuit is arranged in a TX0 output path from a normal power supply domain chip to an abnormal power supply domain chip; the present embodiment provides the following two implementations:

fig. 3 is a topological structure implementation example of an anti-creeping circuit proposed by the present invention. The anticreeping circuit can be independent of other chips in the system, as shown in fig. 3, 31 being the anticreeping circuit, identifying the position of the anticreeping circuit on the topology. The anti-creeping circuit is arranged on a PCB between the MCU0 chip of the constant power supply domain and the MASTER chip of the non-constant power supply domain.

Fig. 4 is a topological structure implementation example of another anti-creeping circuit proposed by the present invention. As shown in fig. 4, where 41 is the anticreeping circuit, it is placed inside the SLAVE chip, which can be integrated into the chip because it is always powered, and then reconnected to the MASTER chip through the SLAVE chip.

Fig. 5 is a specific embodiment of the anti-creeping circuit according to the present invention. 51 is a constant supply domain chip. Reference numeral 52 denotes a power domain chip 2 interface circuit portion, which is a core circuit portion of an embodiment of the present invention. 53 are very power domain chips. When VDD0 is not powered, the output of the first inverter 515 is high, the signal output is connected to PMOS1, PMOS1 is turned off, the path formed by PMOS1 and pull-up resistor R0 forms a high-impedance path, meanwhile, the output of the second inverter 516 is connected to the grid of NMOS1, when VDD0 is not powered, namely 0, the output of the second inverter 516 is low, the path formed by NMOS1 and pull-down resistor R1 forms a high-impedance path, so that in the path from the power supply to the ground formed by PMOS1, R0, R1 and NMOS1, the whole branch is a high-impedance branch. No leakage occurs whether the signal received by IN is high or ground. When VDD0 is dead, AND gate 514 is logically ANDed with VDD0 (which is now low, i.e., 0), so the output 520 of AND gate 514 is always low. Even if VDD0 on PESDMOS2 of the ESD protection circuit of the internal circuit of the power supply domain chip has no electricity, no electricity leakage occurs. Since VDD0 is unpowered, the output OUT of the output 520 of and gate 514 is also 0, and the high level is only connected to three devices, BUF, PESDMOS2 and NESDMOS1, which are all power-tight, so there is no leakage when there is no power inside the very power domain chip.

When VDD0 is powered, PMOS1 and NMOS1 are turned on, and R0 pull-up resistor and R1 pull-down resistor are connected into the circuit. R0 corresponds to the pull-down input case of NMOS2 and pulls the output high, and R1 corresponds to the pull-up mode of PMOS2 and pulls the signal low. Since R0 and R1 form a resistance voltage-dividing branch, the ratio R0: R1 of R0 and R1 is required to be greater than 1:3 in practical implementation, and the output high level is ensured to be normal.

It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. An anti-creeping circuit topology, comprising: the system comprises a power supply, an LDO/DC-DC, an abnormal power supply domain chip, a normal power supply domain chip, an SLAVE chip and a long power supply VDDS, wherein the SLAVE chip outputs a WAKE signal to the normal power supply domain chip; after the communication is finished, the WAKE is invalid;

it is characterized by also comprising: and the anti-leakage circuit is arranged between the MCU0 chip and the TX0 output path of the non-power supply domain chip.

2. The topology of claim 1, wherein the anti-creeping circuit is disposed on a PCB.

3. The topology of claim 1, wherein the anti-creeping circuit is disposed inside a SLAVE chip.

4. An anti-creeping circuit based on the anti-creeping circuit topology of any one of claims 1-3, comprising: the power supply system comprises a constant power supply domain chip circuit, a constant power supply domain chip interface circuit and an abnormal power supply domain chip circuit; the output of the chip circuit of the constant power supply domain is used as the input of the chip interface circuit of the constant power supply domain, and the output of the chip interface circuit of the constant power supply domain is used as the input of the chip circuit of the abnormal power supply domain;

5. The anti-creeping circuit of claim 4, wherein R0: R1>1: 3.