CN113884857B - Chip, chip pressure testing method and device, electronic equipment and storage medium - Google Patents
Chip, chip pressure testing method and device, electronic equipment and storage medium Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
Abstract
The present disclosure provides a chip, a chip pressure testing method, a device, an electronic apparatus, and a storage medium, the method comprising: acquiring an image to be detected and a convolution kernel; based on the image to be detected and the convolution kernel, controlling a thread module in the chip to be detected to continuously execute convolution operation for a plurality of times, so as to obtain an operation result corresponding to each convolution operation; and comparing each obtained operation result with a corresponding correct result to determine the operation performance of the chip to be tested.
Description
Technical Field
The disclosure relates to the technical field of integrated circuits, and in particular relates to a chip, a chip pressure testing method, a device, electronic equipment and a storage medium.
Background
With the development of artificial intelligence technology, the development of artificial intelligence (Artificial Intelligence, AI) chips is becoming more mature. The AI chip refers to a chip which is specially designed for an artificial intelligence algorithm, for example, the artificial intelligence algorithm can be a deep learning algorithm.
Generally, due to rapid development of advanced processes, the concentration of transistors of an AI chip is higher and higher, so that tiny problems on the AI chip are difficult to find under a common test, and the performance of the AI chip is difficult to evaluate accurately.
Disclosure of Invention
In view of this, the present disclosure provides at least a chip, a chip pressure testing method, a device, an electronic apparatus, and a storage medium.
In a first aspect, the present disclosure provides a chip pressure testing method, including:
acquiring an image to be detected and a convolution kernel;
based on the image to be detected and the convolution kernel, controlling a thread module in the chip to be detected to continuously execute convolution operation for a plurality of times, so as to obtain an operation result corresponding to each convolution operation;
and comparing each obtained operation result with a corresponding correct result to determine the operation performance of the chip to be tested.
According to the method, the thread module in the chip to be tested is controlled to continuously execute convolution operation for a plurality of times based on the acquired image to be tested and the convolution kernel, so that operation results corresponding to each convolution operation are obtained, and the operation performance of the chip to be tested is determined by comparing each operation result with the correct result. Meanwhile, the operation performance of the chip to be tested is tested by utilizing the image to be tested and the convolution kernel, a hardware module related to pressure test is not required to be additionally designed on the chip to be tested, unnecessary hardware development is reduced, and resource waste is relieved on the basis of ensuring the operation function of the chip to be tested.
In a possible implementation manner, the controlling the thread module in the chip to be tested to continuously perform multiple convolution operations based on the image to be tested and the convolution kernel to obtain an operation result corresponding to each convolution operation includes:
and based on the image to be detected and the convolution kernel, controlling a thread module in the chip to be detected to continuously execute multiple convolution operations until the duration of the multiple convolution operations is longer than or equal to the set target operation duration, or until the execution times of the multiple convolution operations are equal to the set target times, so as to obtain an operation result corresponding to each convolution operation.
Here, the chip to be tested can be controlled to continuously execute the target convolution operation, or the chip to be tested can be controlled to continuously execute the target convolution operation with the target operation time, and the operation performance of the chip to be tested after continuously executing the convolution operation for a plurality of times is tested, so that the chip to be tested is tested more accurately.
In a possible implementation manner, the controlling the thread module in the chip to be tested to continuously perform multiple convolution operations based on the image to be tested and the convolution kernel to obtain an operation result corresponding to each convolution operation includes:
determining a plurality of temperatures to be measured based on the working temperature range corresponding to the chip to be measured; wherein the temperature to be measured comprises a boundary temperature indicated by the working temperature range;
And based on the image to be measured and the convolution kernel, controlling a thread module in the chip to be measured to continuously execute convolution operation for a plurality of times at each temperature to be measured in the plurality of temperatures to be measured, so as to obtain an operation result corresponding to each convolution operation.
Here, a plurality of temperatures to be measured may be set, where the temperatures to be measured include boundary temperatures indicated by the working temperature ranges, and the computing performance of the chip to be measured at each temperature to be measured may be tested, for example, the computing performance of the chip to be measured at the boundary temperatures may be tested, so as to implement the test of the computing performance of the chip to be measured at different working temperatures.
In a possible implementation manner, the controlling the thread module in the chip to be tested to continuously perform multiple convolution operations based on the image to be tested and the convolution kernel to obtain an operation result corresponding to each convolution operation includes:
and based on the image to be detected and the convolution kernel, controlling a plurality of thread modules in the chip to be detected to continuously execute convolution operation for a plurality of times in parallel, and obtaining an operation result corresponding to the convolution operation of each thread module.
Here, the multiple thread modules in the chip to be tested are controlled to perform convolution operation for multiple times in parallel, and the more the thread modules run in parallel, the greater the power consumption of the chip to be tested is, namely, the computing performance of the chip to be tested under different power consumption can be tested, and a more comprehensive and more accurate test result of the chip to be tested is obtained.
In a possible implementation manner, after obtaining the image to be measured and the convolution kernel, before controlling the thread module in the chip to be measured to continuously perform multiple convolution operations based on the image to be measured and the convolution kernel to obtain an operation result corresponding to each convolution operation, the method further includes:
converting each pixel characteristic value included in the image to be detected into a value under a target data type to obtain a converted image to be detected; and/or converting each convolution characteristic value included in the convolution kernel into a value under the target data type to obtain a converted convolution kernel.
The pixel characteristic value in the image to be tested is converted into a value under the target data type, and/or the convolution characteristic value in the convolution kernel is converted into a value under the target data type, so that the thread module in the chip to be tested can be controlled to execute convolution operation based on the converted image to be tested and/or the converted convolution kernel, and the operation performance of the chip to be tested in processing the convolution operation of different data types is realized.
In a possible implementation manner, the determining the operation performance of the chip to be tested by comparing each obtained operation result with a corresponding correct result includes:
Comparing each obtained operation result with a corresponding correct result to determine the error rate of continuously executing convolution operation for a plurality of times by a thread module in the chip to be tested; the error rate is used for evaluating the operation performance of the chip to be tested.
Here, the error rate of the chip to be tested can be determined, and the operation performance of the chip to be tested can be accurately evaluated through the determined error rate.
In a possible implementation manner, the determining the operation performance of the chip to be tested by comparing each obtained operation result with a corresponding correct result includes:
comparing each obtained operation result with a corresponding correct result to determine a first error rate of continuously executing multiple convolution operations in each of a plurality of time periods by a thread module in the chip to be tested;
generating a first relationship curve characterizing a relationship between an execution time period and a first error rate based on the first error rate; the first relation curve is used for evaluating the operation performance of the chip to be tested.
By generating a first relation curve representing the relation between the execution time period and the first error rate, the operation performance of the chip to be tested can be evaluated more accurately and more clearly by using the first relation curve.
In a possible implementation manner, in a case that a plurality of thread modules in the chip to be tested execute convolution operation in parallel, the determining the operation performance of the chip to be tested by comparing each obtained operation result with a corresponding correct result includes:
determining the average error rate of the convolution operation executed by the plurality of thread modules in each time period by comparing the obtained operation results with the corresponding correct results;
generating a second relationship curve characterizing a relationship between execution time periods of the plurality of thread modules and the average error rate based on the average error rate; the second relation curve is used for evaluating the operation performance of the chip to be tested.
When the plurality of thread modules execute convolution operation in parallel, determining the average error rate of the convolution operation executed by the plurality of thread modules in each time period, generating a second relation curve representing the relation between the execution time periods of the plurality of thread modules and the average error rate based on the average error rate, and accurately and clearly evaluating the operation performance of the chip to be tested by using the second relation curve.
In a possible implementation manner, after determining the operation performance of the chip to be tested, the method further includes:
And determining a target chip for executing neural network training and/or neural network reasoning from the plurality of chips to be tested according to the operation performance of each chip to be tested in the plurality of chips to be tested generated in the same batch.
Here, according to the operation performance of each chip to be tested, a target chip is selected from a plurality of chips to be tested, for example, a chip with the best operation performance can be selected as the target chip, so that the target chip can better perform neural network training and/or neural network reasoning.
The following description of the effects of the apparatus, the electronic device, etc. refers to the description of the above method, and will not be repeated here.
In a second aspect, the present disclosure provides a chip comprising: and the thread module is used for executing convolution operation based on the image to be detected and the convolution kernel to obtain an operation result corresponding to the convolution operation.
In a third aspect, the present disclosure provides a chip pressure testing apparatus, comprising:
the acquisition module is used for acquiring the image to be detected and the convolution kernel;
the control module is used for controlling a thread module in the chip to be tested to continuously execute convolution operation for a plurality of times based on the image to be tested and the convolution kernel to obtain an operation result corresponding to each convolution operation;
And the determining module is used for determining the operation performance of the chip to be tested by comparing each obtained operation result with a corresponding correct result.
In a possible implementation manner, the control module is configured to, when controlling the thread module in the chip to be tested to continuously perform multiple convolution operations based on the image to be tested and the convolution kernel to obtain an operation result corresponding to each convolution operation,:
and based on the image to be detected and the convolution kernel, controlling a thread module in the chip to be detected to continuously execute multiple convolution operations until the duration of the multiple convolution operations is longer than or equal to the set target operation duration, or until the execution times of the multiple convolution operations are equal to the set target times, so as to obtain an operation result corresponding to each convolution operation.
In a possible implementation manner, the control module is configured to, when controlling the thread module in the chip to be tested to continuously perform multiple convolution operations based on the image to be tested and the convolution kernel to obtain an operation result corresponding to each convolution operation,:
determining a plurality of temperatures to be measured based on the working temperature range corresponding to the chip to be measured; wherein the temperature to be measured comprises a boundary temperature indicated by the working temperature range;
And based on the image to be measured and the convolution kernel, controlling a thread module in the chip to be measured to continuously execute convolution operation for a plurality of times at each temperature to be measured in the plurality of temperatures to be measured, so as to obtain an operation result corresponding to each convolution operation.
In a possible implementation manner, the control module is configured to, when controlling the thread module in the chip to be tested to continuously perform multiple convolution operations based on the image to be tested and the convolution kernel to obtain an operation result corresponding to each convolution operation,:
and based on the image to be detected and the convolution kernel, controlling a plurality of thread modules in the chip to be detected to continuously execute convolution operation for a plurality of times in parallel, and obtaining an operation result corresponding to the convolution operation of each thread module.
In one possible implementation manner, after obtaining the image to be measured and the convolution kernel, before controlling the thread module in the chip to be measured to continuously perform multiple convolution operations based on the image to be measured and the convolution kernel to obtain an operation result corresponding to each convolution operation, the apparatus further includes: a conversion module for:
converting each pixel characteristic value included in the image to be detected into a value under a target data type to obtain a converted image to be detected; and/or converting each convolution characteristic value included in the convolution kernel into a value under the target data type to obtain a converted convolution kernel.
In a possible implementation manner, the determining module is configured to, when determining the operation performance of the chip to be tested by comparing each obtained operation result with a corresponding correct result:
comparing each obtained operation result with a corresponding correct result to determine the error rate of continuously executing convolution operation for a plurality of times by a thread module in the chip to be tested; the error rate is used for evaluating the operation performance of the chip to be tested.
In a possible implementation manner, the determining module is configured to, when determining the operation performance of the chip to be tested by comparing each obtained operation result with a corresponding correct result:
comparing each obtained operation result with a corresponding correct result to determine a first error rate of continuously executing multiple convolution operations in each of a plurality of time periods by a thread module in the chip to be tested;
generating a first relationship curve characterizing a relationship between an execution time period and a first error rate based on the first error rate; the first relation curve is used for evaluating the operation performance of the chip to be tested.
In a possible implementation manner, in a case that a plurality of thread modules in the chip to be tested execute convolution operation in parallel, the determining module is configured to, when determining the operation performance of the chip to be tested by comparing each obtained operation result with a corresponding correct result:
Determining the average error rate of the convolution operation executed by the plurality of thread modules in each time period by comparing the obtained operation results with the corresponding correct results;
generating a second relationship curve characterizing a relationship between execution time periods of the plurality of thread modules and the average error rate based on the average error rate; the second relation curve is used for evaluating the operation performance of the chip to be tested.
In one possible implementation manner, after determining the operation performance of the chip to be tested, the apparatus further includes: the selecting module is used for:
and determining a target chip for executing neural network training and/or neural network reasoning from the plurality of chips to be tested according to the operation performance of each chip to be tested in the plurality of chips to be tested generated in the same batch.
In a fourth aspect, the present disclosure provides an electronic device comprising: a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, the processor and the memory in communication over the bus when the electronic device is running, the machine-readable instructions when executed by the processor performing the steps of the chip pressure test method as described in the first aspect or any of the embodiments above.
In a fifth aspect, the present disclosure provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the chip pressure testing method according to the first aspect or any of the embodiments described above.
The foregoing objects, features and advantages of the disclosure will be more readily apparent from the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the embodiments are briefly described below, which are incorporated in and constitute a part of the specification, these drawings showing embodiments consistent with the present disclosure and together with the description serve to illustrate the technical solutions of the present disclosure. It is to be understood that the following drawings illustrate only certain embodiments of the present disclosure and are therefore not to be considered limiting of its scope, for the person of ordinary skill in the art may admit to other equally relevant drawings without inventive effort.
Fig. 1 is a schematic flow chart of a chip pressure testing method according to an embodiment of the disclosure;
Fig. 2a is a schematic diagram illustrating a first relationship curve in a chip pressure testing method according to an embodiment of the disclosure;
fig. 2b is a schematic diagram illustrating a first relationship curve in a chip pressure testing method according to an embodiment of the disclosure;
FIG. 3 is a schematic diagram of a second relationship curve in a method for testing chip pressure according to an embodiment of the disclosure;
FIG. 4 is a schematic diagram of a chip pressure testing apparatus according to an embodiment of the disclosure;
fig. 5 shows a schematic structural diagram of an electronic device according to an embodiment of the disclosure.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments. The components of the embodiments of the present disclosure, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present disclosure provided in the accompanying drawings is not intended to limit the scope of the disclosure, as claimed, but is merely representative of selected embodiments of the disclosure. All other embodiments, which can be made by those skilled in the art based on the embodiments of this disclosure without making any inventive effort, are intended to be within the scope of this disclosure.
Generally, due to rapid development of advanced processes, the transistor density of an artificial intelligence (Artificial Intelligence, AI) chip is higher and higher, so that tiny problems on the AI chip are difficult to find under a common test, and the performance of the AI chip is difficult to evaluate more accurately. Accordingly, embodiments of the present disclosure provide a chip, a chip pressure testing method, a device, an electronic apparatus, and a storage medium.
The present invention is directed to a method for manufacturing a semiconductor device, and a semiconductor device manufactured by the method.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
For ease of understanding the embodiments of the present disclosure, a method for testing chip pressure disclosed in the embodiments of the present disclosure will be described in detail first. The execution subject of the chip pressure test method provided by the embodiment of the disclosure may be a server, a terminal device, etc., where the terminal device may be a computer, a tablet, a mobile phone, etc., and the server may be a cloud server, a local server, etc.
Referring to fig. 1, a flow chart of a chip pressure testing method according to an embodiment of the disclosure is shown, where the method includes S101-S103, where:
s101, acquiring an image to be detected and a convolution kernel;
s102, based on the image to be detected and the convolution kernel, controlling a thread module in a chip to be detected to continuously execute convolution operation for a plurality of times, and obtaining an operation result corresponding to each convolution operation;
s103, comparing each obtained operation result with a corresponding correct result to determine the operation performance of the chip to be tested.
According to the method, the thread module in the chip to be tested is controlled to continuously execute convolution operation for a plurality of times based on the acquired image to be tested and the convolution kernel, so that operation results corresponding to each convolution operation are obtained, and the operation performance of the chip to be tested is determined by comparing each operation result with the correct result. Meanwhile, the operation performance of the chip to be tested is tested by utilizing the image to be tested and the convolution kernel, a hardware module related to pressure test is not required to be additionally designed on the chip to be tested, unnecessary hardware development is reduced, and resource waste is relieved on the basis of ensuring the operation function of the chip to be tested.
S101 to S103 are specifically described below.
For S101:
the image to be measured may be any one of the acquired images, for example, the image to be measured may be a Red-Green-Blue (RGB) image. The convolution kernel can be set according to the requirement, wherein the number of channels of the convolution kernel is consistent with the number of channels of the image to be detected. For example, where the image to be measured is 3 channels, the convolution kernel may be 3 x 3 in size, i.e. the convolution kernel has a length of 3, a width of 3, and a number of channels of 3.
In implementation, the data type of the pixel characteristic value of each pixel included in the image to be measured is related to the image type of the image to be measured, for example, the data type of the pixel characteristic value may be an integer. And the convolution eigenvalue of each eigenvalue on the convolution kernel may be set as desired, for example, the convolution eigenvalue of the eigenvalue may be set to a constant.
In an alternative embodiment, after obtaining the image to be measured and the convolution kernel, before controlling the thread module in the chip to be measured to continuously perform multiple convolution operations based on the image to be measured and the convolution kernel to obtain an operation result corresponding to each convolution operation, the method further includes: converting each pixel characteristic value included in the image to be detected into a value under a target data type to obtain a converted image to be detected; and/or converting each convolution characteristic value included in the convolution kernel into a value under the target data type to obtain a converted convolution kernel.
The target data type may be set as required, for example, the target data type may be any of the following data types: single precision floating point number FP32, half precision floating point number FP16, integer INT8, TF32 (data type in machine learning system Tensorflow), etc.
For example, when the target data type is FP32, the initial data type of the pixel characteristic value of the pixel point in the image to be measured is INT, and the initial data type of the convolution characteristic value of the characteristic point in the convolution kernel is INT, after the image to be measured and the convolution kernel are obtained, the pixel characteristic value of the pixel point included in the image to be measured may be converted into the FP32 type value, so as to obtain the converted image to be measured. And/or converting the characteristic convolution value of the characteristic points included in the convolution kernel into a value of the FP32 type, thereby obtaining a converted convolution kernel.
And further, the converted image to be detected and/or the converted convolution kernel can be utilized to control a thread module in the chip to be detected to continuously execute convolution operation for a plurality of times, so as to obtain an operation result corresponding to each convolution operation. For example, when the image to be measured and the convolution kernel are converted to obtain the converted image to be measured and the converted convolution kernel, the thread module of the chip to be measured can be controlled to multiply and add the pixel characteristic value included in the converted image to be measured and the convolution characteristic value included in the converted convolution kernel to obtain the operation result of the convolution operation.
The pixel characteristic value in the image to be tested is converted into a value under the target data type, and/or the convolution characteristic value in the convolution kernel is converted into a value under the target data type, so that the thread module in the chip to be tested can be controlled to execute convolution operation based on the converted image to be tested and/or the converted convolution kernel, and the operation performance of the chip to be tested in processing the convolution operation of different data types is realized.
For S102:
the chip to be tested may be an AI chip. The thread module in the chip to be tested can be controlled, and convolution operation is carried out on the convolution kernel and the pixel characteristic values included in the image to be tested according to the set moving step length, so that an operation result corresponding to each convolution operation is obtained. When the convolution kernel is three-channel, the obtained operation result can be a three-channel characteristic diagram.
In an optional implementation manner, the controlling the thread module in the chip to be tested to continuously perform multiple convolution operations based on the image to be tested and the convolution kernel to obtain an operation result corresponding to each convolution operation includes: and based on the image to be detected and the convolution kernel, controlling a thread module in the chip to be detected to continuously execute multiple convolution operations until the duration of the multiple convolution operations is longer than or equal to the set target operation duration, or until the execution times of the multiple convolution operations are equal to the set target times, so as to obtain an operation result corresponding to each convolution operation.
Here, the target number of times may be set, for example, the target number of times may be ten million times, and the thread module in the chip to be tested is controlled to perform convolution operation on the convolution kernel and the image to be tested until the thread module continuously performs the convolution operation for ten million times, so as to obtain an operation result corresponding to the convolution operation for ten million times.
Or, the target operation duration may be set, for example, the target operation duration may be 36 hours, and the thread module in the chip to be tested is controlled to perform convolution operation on the convolution kernel and the image to be tested until the duration of continuous execution of the convolution operation by the thread module is longer than or equal to 36 hours, so as to obtain an operation result corresponding to each convolution operation executed within 36 hours.
Here, the chip to be tested can be controlled to continuously execute the target convolution operation, or the chip to be tested can be controlled to continuously execute the target convolution operation with the target operation time, and the operation performance of the chip to be tested after continuously executing the convolution operation for a plurality of times is tested, so that the chip to be tested is tested more accurately.
In an optional implementation manner, the controlling the thread module in the chip to be tested to continuously perform multiple convolution operations based on the image to be tested and the convolution kernel to obtain an operation result corresponding to each convolution operation may include step A1 and step A2, where:
A1, determining a plurality of temperatures to be measured based on the working temperature range corresponding to the chip to be measured; wherein the temperature to be measured comprises a boundary temperature indicated by the working temperature range;
and A2, based on the image to be measured and the convolution kernel, controlling a thread module in the chip to be measured to continuously execute convolution operation for a plurality of times at each temperature to be measured in the plurality of temperatures to be measured, so as to obtain an operation result corresponding to each convolution operation.
The working temperature range corresponding to the chip to be tested can be the working temperature range determined by the manufacturer according to the chip performance. The plurality of temperatures to be measured can be determined based on the working temperature range corresponding to the chip to be measured, and the number of the temperatures to be measured can be set according to the needs. When the temperature to be measured is selected, the boundary temperature indicated by the working temperature range is the temperature to be measured. The temperature to be measured can be selected according to the need, for example, more temperatures to be measured can be selected near the boundary temperature, and less temperatures to be measured can be selected when the boundary temperature is far away.
By way of example, the operating temperature range may be [20 ℃ to 80 ℃ ], with a number of temperatures to be measured of 2, then the determined temperatures to be measured are 20 ℃ and 80 ℃; when the number of temperatures to be measured is 5, the determined temperatures to be measured are 20 ℃, 22 ℃, 50 ℃, 78 ℃, and 80 ℃.
And then, at each temperature to be measured, controlling a thread module in the chip to be measured to continuously perform convolution operation on the convolution kernel and the image to be measured for a plurality of times, so as to obtain an operation result corresponding to each convolution operation. And then the operation result corresponding to each convolution operation at each temperature to be measured can be obtained.
When the method is implemented, the thread module in the chip to be tested can be controlled to continuously perform convolution operation on the convolution kernel and the image to be tested for multiple times at each temperature to be tested until the duration of the convolution operation for multiple times is longer than or equal to the set target operation duration, so that the operation result corresponding to each convolution operation is obtained. Or, the thread module in the chip to be tested can be controlled to continuously perform convolution operation on the convolution kernel and the image to be tested for multiple times at each temperature to be tested until the execution times of the convolution operation for multiple times are equal to the set target times, and an operation result corresponding to each convolution operation is obtained.
Here, a plurality of temperatures to be measured may be set, where the temperatures to be measured include boundary temperatures indicated by the working temperature ranges, and the computing performance of the chip to be measured at each temperature to be measured may be tested, for example, the computing performance of the chip to be measured at the boundary temperatures may be tested, so as to implement the test of the computing performance of the chip to be measured at different working temperatures.
In an optional implementation manner, the controlling the thread module in the chip to be tested to continuously perform multiple convolution operations based on the image to be tested and the convolution kernel to obtain an operation result corresponding to each convolution operation includes: and based on the image to be detected and the convolution kernel, controlling a plurality of thread modules in the chip to be detected to continuously execute convolution operation for a plurality of times in parallel, and obtaining an operation result corresponding to the convolution operation of each thread module.
The chip to be tested may include a target number of thread modules therein. For example, if the target number is 1000, the plurality of thread modules may be all thread modules in the 1000 thread modules, that is, all thread modules in the chip to be tested are controlled to continuously execute convolution operation for multiple times in parallel, so as to obtain an operation result corresponding to each convolution operation of each thread module; the plurality of thread modules can also be part of the 1000 thread modules (such as 500 thread modules, 800 thread modules and the like), namely, the part of the thread modules in the chip to be tested are controlled to continuously execute convolution operation for a plurality of times in parallel, so as to obtain an operation result corresponding to each convolution operation of each thread module. The number of thread modules for performing convolution operation in parallel can be set according to practical situations.
When the method is implemented, based on the image to be tested and the convolution kernel, a plurality of thread modules in the chip to be tested can be controlled to continuously execute convolution operation for a plurality of times in parallel at the temperature to be tested, so that an operation result corresponding to each convolution operation of each thread module at the temperature to be tested is obtained.
The method can also control a plurality of thread modules in the chip to be tested to continuously execute convolution operation for a plurality of times in parallel at the temperature to be tested based on the image to be tested and the convolution kernel to be tested until the duration of the convolution operation for a plurality of times is longer than or equal to the set target operation duration, or until the execution times of the convolution operation for a plurality of times is equal to the set target times; and obtaining an operation result corresponding to each convolution operation of each thread module at the temperature to be measured.
Here, the multiple thread modules in the chip to be tested are controlled to perform convolution operation for multiple times in parallel, and the more the thread modules run in parallel, the greater the power consumption of the chip to be tested is, namely, the computing performance of the chip to be tested under different power consumption can be tested, and a more comprehensive and more accurate test result of the chip to be tested is obtained.
When the pixel characteristic values in the image to be measured are converted to obtain the converted image to be measured, the thread module in the chip to be measured can be controlled to continuously execute convolution operation for a plurality of times based on the converted image to be measured and the convolution kernel, so that an operation result corresponding to each convolution operation is obtained. When the convolution characteristic value in the convolution kernel is converted to obtain a converted convolution kernel, a thread module in the chip to be tested can be controlled to continuously execute convolution operation for a plurality of times based on the image to be tested and the converted convolution kernel, so that an operation result corresponding to each convolution operation is obtained. When the image to be measured and the convolution kernel are converted to obtain a converted image to be measured and a converted convolution kernel, a thread module in the chip to be measured can be controlled to continuously execute convolution operation for a plurality of times based on the converted image to be measured and the converted convolution kernel, so that an operation result corresponding to each convolution operation is obtained.
For S103:
when in implementation, the correct result of the convolution operation of the image to be detected and the convolution kernel can be predetermined; or determining the correct result of convolution operation of the converted image to be detected and the convolution kernel; or determining the correct result of the convolution operation of the image to be detected and the converted convolution kernel; or determining the correct result of the convolution operation of the converted image to be detected and the converted convolution kernel. And comparing each obtained operation result with a corresponding correct result to determine the operation performance of the chip to be tested. For example, each operation result may be compared with a correct result, if correct, the operation result may be marked as 1, if incorrect, the operation result may be marked as 0, and further, the accuracy of the chip to be tested may be determined according to the number of times of convolution operations marked as 1 and the total number of times of execution, and the operation performance of the chip to be tested may be evaluated using the accuracy. For example, if the accuracy is high, the operation performance of the chip to be tested is good.
In an optional implementation manner, the determining the operation performance of the chip to be tested by comparing each obtained operation result with a corresponding correct result includes: comparing each obtained operation result with a corresponding correct result to determine the error rate of continuously executing convolution operation for a plurality of times by a thread module in the chip to be tested; the error rate is used for evaluating the operation performance of the chip to be tested.
For example, each operation result may be compared with the correct result, if the operation result is correct, the operation result may be marked as 1, if the operation result is incorrect, the operation result may be marked as 0, and further, the error rate of the chip to be tested may be determined according to the number of times of convolution operations marked as 0 and the total number of times of execution, and the operation performance of the chip to be tested may be evaluated using the error rate. For example, the higher the error rate, the poorer the operation performance of the chip to be tested.
When the method is implemented, if the number of inconsistent operation results and correct results of the first chip to be tested is 50 after 1000 times of convolution operation is carried out at the temperature of 20 ℃ to be tested, the error rate of the first chip to be tested is 50/1000=1/20; after the second chip to be tested executes 1000 times of convolution operation at the temperature of 20 ℃ to be tested, the number of inconsistent operation results and correct results is 20, and the error rate of the second chip to be tested is 20/1000=1/50; and determining that the operation performance of the first chip to be tested is worse than that of the second chip to be tested.
Here, the error rate of the chip to be tested can be determined, and the operation performance of the chip to be tested can be accurately evaluated through the determined error rate.
In an optional implementation manner, the determining the operation performance of the chip to be tested by comparing each obtained operation result with a corresponding correct result may include a step B1 and a step B2, where:
Step B1, determining a first error rate of continuously executing multiple convolution operations in each of a plurality of time periods by a line module in the chip to be tested by comparing each obtained operation result with a corresponding correct result;
step B2, generating a first relation curve representing the relation between the execution time period and the first error rate based on the first error rate; the first relation curve is used for evaluating the operation performance of the chip to be tested.
In implementation, the obtained operation results can be compared with the corresponding correct results, and the first error rate of continuously executing multiple convolution operations by the thread module in the chip to be tested in each of multiple time periods is determined. For example, the execution duration of the convolution operation performed by the chip to be tested is 24 hours, and then the first error rate of the convolution operation performed by the chip to be tested in the 1 st hour, the first error rate of the convolution operation performed by the chip to be tested in the 2 nd hour, the first error rate of the convolution operation performed by the chip to be tested in the … … th hour, and the first error rate of the convolution operation performed by the chip to be tested in the 24 th hour can be determined. Further, a first relationship curve may be generated based on the obtained first error rates corresponding to the respective time periods, and the calculation performance of the chip to be measured may be evaluated using the first relationship curve. Wherein the first relationship is used to characterize a relationship between the execution time period and the first error rate.
Referring to the schematic diagram of the first relationship curve corresponding to the chip to be tested a shown in fig. 2a, the first relationship curve includes the first error rate of the chip to be tested a in each time period, and it can be seen that the error rate of the chip to be tested a shown in fig. 2a increases with time, and the operation performance of the chip to be tested a is poor.
Referring to the schematic diagram of the first relationship curve corresponding to the chip b to be tested shown in fig. 2b, it can be seen that the time of the error occurrence of the chip b to be tested shown in fig. 2b is later than that of the chip a to be tested, and the error rate of the chip b to be tested is smaller than that of the chip a to be tested in the same time period, so that the operation performance of the chip b to be tested is better than that of the chip a to be tested. Of which fig. 2a and 2b are only exemplary illustrations.
By generating a first relation curve representing the relation between the execution time period and the first error rate, the operation performance of the chip to be tested can be evaluated more accurately and more clearly by using the first relation curve.
In an optional implementation manner, in a case that a plurality of thread modules in the chip to be tested execute convolution operation in parallel, the determining the operation performance of the chip to be tested by comparing each obtained operation result with a corresponding correct result may include a step C1 and a step C2, where:
Step C1, determining the average error rate of convolution operation executed by the plurality of thread modules in each time period by comparing each obtained operation result with a corresponding correct result;
step C2, generating a second relation curve representing the relation between the execution time periods of the plurality of thread modules and the average error rate based on the average error rate; the second relation curve is used for evaluating the operation performance of the chip to be tested.
When a plurality of field modules in the chip to be tested execute convolution operation in parallel, a second error rate of continuously executing convolution operation for a plurality of times in each time period by each thread module can be determined; the average error rate at which the plurality of thread modules perform convolution operations during each time period may then be determined based on the second error rate. For example, the execution duration of the convolution operation performed by the chip to be tested is 24 hours, then the average error rate of the convolution operation performed by the plurality of thread modules of the chip to be tested in the 1 st hour, the average error rate of the convolution operation performed in the 2 nd hour, … …, and the average error rate of the convolution operation performed in the 24 th hour can be determined. Further, a second relationship curve may be generated based on the obtained average error rates corresponding to the respective time periods, and the calculation performance of the chip to be measured may be evaluated using the second relationship curve. Wherein the second relationship is used to characterize the relationship between the execution time period and the average error rate.
Referring to the schematic of the second relationship shown in FIG. 3, the average error rate of a plurality of thread modules during each time period may be included in FIG. 3. And in the same time period, if the average error rate is larger, the operation performance of the chip to be tested is poorer.
When the plurality of thread modules execute convolution operation in parallel, determining the average error rate of the convolution operation executed by the plurality of thread modules in each time period, generating a second relation curve representing the relation between the execution time periods of the plurality of thread modules and the average error rate based on the average error rate, and accurately and clearly evaluating the operation performance of the chip to be tested by using the second relation curve.
In an alternative embodiment, after determining the operational performance of the chip under test, the method further includes: and determining a target chip for executing neural network training and/or neural network reasoning from the plurality of chips to be tested according to the operation performance of each chip to be tested in the plurality of chips to be tested generated in the same batch.
In the implementation, the pressure test can be performed on each chip to be tested in the plurality of chips to be tested generated in the same batch, the operation performance of each chip to be tested is determined, and then the target chip for executing the neural network training and/or the neural network reasoning can be determined based on the operation performance of each chip to be tested. For example, if the operation performance of the chip a to be tested is optimal, the chip a to be tested may be selected as the target chip, and the target chip may be used to perform the neural network training process and/or perform the neural network reasoning process.
Here, according to the operation performance of each chip to be tested, a target chip is selected from a plurality of chips to be tested, for example, a chip with the best operation performance can be selected as the target chip, so that the target chip can better perform neural network training and/or neural network reasoning.
In implementation, the production condition of the batch can be evaluated according to the operation performance of each chip to be tested in the plurality of chips to be tested generated in the same batch, for example, if the operation performance of each chip to be tested generated in the first batch is better, the production condition of the first batch is determined to be better.
In specific implementation, the test code corresponding to the chip pressure test method can be implemented by using a high-level language such as a C language, for example, the test code can comprise a test case, test initial parameter setting, a test flow and the like, the compiled test code is sent to the chip to be tested, and the chip to be tested executes the test code to implement pressure test on the chip to be tested. The method can send the generated test code to any AI chip to be tested, so that the pressure test of the AI chip is realized, and meanwhile, the test of AI chips of different manufacturers and different batches is realized.
Or writing the generated test code into the SoC program of the chip to be tested, packaging the test code with a function, and calling the function by the upper computer. The pressure test of the AI chip is realized by transmitting a set initial value; the method is simple to use, the compiling and issuing step is omitted, and the test efficiency of the AI chip is improved.
It will be appreciated by those skilled in the art that in the above-described method of the specific embodiments, the written order of steps is not meant to imply a strict order of execution but rather should be construed according to the function and possibly inherent logic of the steps.
Based on the same conception, the disclosed embodiments also provide a chip comprising: and the thread module is used for executing convolution operation based on the image to be detected and the convolution kernel to obtain an operation result corresponding to the convolution operation.
When the method is implemented, the thread module can carry out convolution operation on the image to be detected and the convolution kernel to obtain an operation result corresponding to the convolution operation. The thread module may be implemented as an arithmetic logic unit in a chip, such as an operator.
Based on the same concept, the embodiment of the disclosure further provides a chip pressure testing device, which is shown in fig. 4, and is an architecture schematic diagram of the chip pressure testing device provided by the embodiment of the disclosure, and includes an obtaining module 401, a control module 402, and a determining module 403, and is specifically:
An acquisition module 401, configured to acquire an image to be measured and a convolution kernel;
the control module 402 is configured to control, based on the image to be tested and the convolution kernel, a thread module in the chip to be tested to continuously perform multiple convolution operations, so as to obtain an operation result corresponding to each convolution operation;
and the determining module 403 is configured to determine the operation performance of the chip to be tested by comparing each obtained operation result with a corresponding correct result.
In a possible implementation manner, the control module 402 is configured to, when controlling the thread module in the chip to be tested to continuously perform a plurality of convolution operations based on the image to be tested and the convolution kernel, obtain an operation result corresponding to each convolution operation, perform:
and based on the image to be detected and the convolution kernel, controlling a thread module in the chip to be detected to continuously execute multiple convolution operations until the duration of the multiple convolution operations is longer than or equal to the set target operation duration, or until the execution times of the multiple convolution operations are equal to the set target times, so as to obtain an operation result corresponding to each convolution operation.
In a possible implementation manner, the control module 402 is configured to, when controlling the thread module in the chip to be tested to continuously perform a plurality of convolution operations based on the image to be tested and the convolution kernel, obtain an operation result corresponding to each convolution operation, perform:
Determining a plurality of temperatures to be measured based on the working temperature range corresponding to the chip to be measured; wherein the temperature to be measured comprises a boundary temperature indicated by the working temperature range;
and based on the image to be measured and the convolution kernel, controlling a thread module in the chip to be measured to continuously execute convolution operation for a plurality of times at each temperature to be measured in the plurality of temperatures to be measured, so as to obtain an operation result corresponding to each convolution operation.
In a possible implementation manner, the control module 402 is configured to, when controlling the thread module in the chip to be tested to continuously perform a plurality of convolution operations based on the image to be tested and the convolution kernel, obtain an operation result corresponding to each convolution operation, perform:
and based on the image to be detected and the convolution kernel, controlling a plurality of thread modules in the chip to be detected to continuously execute convolution operation for a plurality of times in parallel, and obtaining an operation result corresponding to the convolution operation of each thread module.
In one possible implementation manner, after obtaining the image to be measured and the convolution kernel, before controlling the thread module in the chip to be measured to continuously perform multiple convolution operations based on the image to be measured and the convolution kernel to obtain an operation result corresponding to each convolution operation, the apparatus further includes: a conversion module 404, configured to:
Converting each pixel characteristic value included in the image to be detected into a value under a target data type to obtain a converted image to be detected; and/or converting each convolution characteristic value included in the convolution kernel into a value under the target data type to obtain a converted convolution kernel.
In a possible implementation manner, the determining module 403 is configured to, when determining the operation performance of the chip to be tested by comparing each obtained operation result with a corresponding correct result:
comparing each obtained operation result with a corresponding correct result to determine the error rate of continuously executing convolution operation for a plurality of times by a thread module in the chip to be tested; the error rate is used for evaluating the operation performance of the chip to be tested.
In a possible implementation manner, the determining module 403 is configured to, when determining the operation performance of the chip to be tested by comparing each obtained operation result with a corresponding correct result:
comparing each obtained operation result with a corresponding correct result to determine a first error rate of continuously executing multiple convolution operations in each of a plurality of time periods by a thread module in the chip to be tested;
Generating a first relationship curve characterizing a relationship between an execution time period and a first error rate based on the first error rate; the first relation curve is used for evaluating the operation performance of the chip to be tested.
In a possible implementation manner, in a case that a plurality of thread modules in the chip to be tested execute convolution operations in parallel, the determining module 403 is configured to, when determining the operation performance of the chip to be tested by comparing each obtained operation result with a corresponding correct result:
determining the average error rate of the convolution operation executed by the plurality of thread modules in each time period by comparing the obtained operation results with the corresponding correct results;
generating a second relationship curve characterizing a relationship between execution time periods of the plurality of thread modules and the average error rate based on the average error rate; the second relation curve is used for evaluating the operation performance of the chip to be tested.
In one possible implementation manner, after determining the operation performance of the chip to be tested, the apparatus further includes: a selecting module 405, configured to:
and determining a target chip for executing neural network training and/or neural network reasoning from the plurality of chips to be tested according to the operation performance of each chip to be tested in the plurality of chips to be tested generated in the same batch.
In some embodiments, the functions or templates included in the apparatus provided by the embodiments of the present disclosure may be used to perform the methods described in the foregoing method embodiments, and specific implementations thereof may refer to descriptions of the foregoing method embodiments, which are not repeated herein for brevity.
Based on the same technical concept, the embodiment of the disclosure also provides electronic equipment. Referring to fig. 5, a schematic structural diagram of an electronic device according to an embodiment of the disclosure includes a processor 501, a memory 502, and a bus 503. The memory 502 is configured to store execution instructions, including a memory 5021 and an external memory 5022; the memory 5021 is also referred to as an internal memory, and is used for temporarily storing operation data in the processor 501 and data exchanged with an external memory 5022 such as a hard disk, the processor 501 exchanges data with the external memory 5022 through the memory 5021, and when the electronic device 500 is running, the processor 501 and the memory 502 communicate with each other through the bus 503, so that the processor 501 executes the following instructions:
acquiring an image to be detected and a convolution kernel;
based on the image to be detected and the convolution kernel, controlling a thread module in the chip to be detected to continuously execute convolution operation for a plurality of times, so as to obtain an operation result corresponding to each convolution operation;
And comparing each obtained operation result with a corresponding correct result to determine the operation performance of the chip to be tested.
The specific processing flow of the processor 501 may refer to the description of the above method embodiments, and will not be repeated here.
Furthermore, the embodiments of the present disclosure also provide a computer readable storage medium, on which a computer program is stored, which when executed by a processor performs the steps of the chip pressure testing method described in the above method embodiments. Wherein the storage medium may be a volatile or nonvolatile computer readable storage medium.
The embodiments of the present disclosure further provide a computer program product, where the computer program product carries program code, and instructions included in the program code may be used to perform the steps of the method for testing chip pressure described in the foregoing method embodiments, and specifically reference may be made to the foregoing method embodiments, which are not described herein.
Wherein the above-mentioned computer program product may be realized in particular by means of hardware, software or a combination thereof. In an alternative embodiment, the computer program product is embodied as a computer storage medium, and in another alternative embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK), or the like.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system and apparatus may refer to corresponding procedures in the foregoing method embodiments, which are not described herein again. In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer readable storage medium executable by a processor. Based on such understanding, the technical solution of the present disclosure may be embodied in essence or a part contributing to the prior art or a part of the technical solution, or in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the embodiments of the present disclosure. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (10)
1. A method for testing chip pressure, comprising:
acquiring an image to be detected and a convolution kernel;
based on the image to be detected and the convolution kernel, controlling a thread module in the chip to be detected to continuously execute convolution operation for a plurality of times, so as to obtain an operation result corresponding to each convolution operation;
comparing each obtained operation result with a corresponding correct result to determine the operation performance of the chip to be tested;
the controlling the thread module in the chip to be tested to continuously execute the convolution operation for a plurality of times based on the image to be tested and the convolution kernel to obtain the operation result corresponding to each convolution operation comprises the following steps: based on the image to be detected and the convolution kernel, a plurality of thread modules in the chip to be detected are controlled to continuously execute convolution operation for a plurality of times in parallel, and an operation result corresponding to the convolution operation of each thread module is obtained;
after obtaining the image to be measured and the convolution kernel, before controlling the thread module in the chip to be measured to continuously execute convolution operation for a plurality of times based on the image to be measured and the convolution kernel to obtain an operation result corresponding to each convolution operation, the method further comprises:
converting each pixel characteristic value included in the image to be detected into a value under a target data type to obtain a converted image to be detected; and/or converting each convolution characteristic value included in the convolution kernel into a value under the target data type to obtain a converted convolution kernel.
2. The method according to claim 1, wherein the controlling the thread module in the chip to be tested to continuously perform a plurality of convolution operations based on the image to be tested and the convolution kernel to obtain an operation result corresponding to each convolution operation includes:
and based on the image to be detected and the convolution kernel, controlling a thread module in the chip to be detected to continuously execute multiple convolution operations until the duration of the multiple convolution operations is longer than or equal to the set target operation duration, or until the execution times of the multiple convolution operations are equal to the set target times, so as to obtain an operation result corresponding to each convolution operation.
3. The method according to claim 1 or 2, wherein the controlling the thread module in the chip to be tested to continuously perform a plurality of convolution operations based on the image to be tested and the convolution kernel to obtain an operation result corresponding to each convolution operation includes:
determining a plurality of temperatures to be measured based on the working temperature range corresponding to the chip to be measured; wherein the temperature to be measured comprises a boundary temperature indicated by the working temperature range;
and based on the image to be measured and the convolution kernel, controlling a thread module in the chip to be measured to continuously execute convolution operation for a plurality of times at each temperature to be measured in the plurality of temperatures to be measured, so as to obtain an operation result corresponding to each convolution operation.
4. The method according to claim 1 or 2, wherein determining the operational performance of the chip under test by comparing each obtained operational result with a corresponding correct result comprises:
comparing each obtained operation result with a corresponding correct result to determine the error rate of continuously executing convolution operation for a plurality of times by a thread module in the chip to be tested; the error rate is used for evaluating the operation performance of the chip to be tested.
5. The method according to claim 1 or 2, wherein determining the operational performance of the chip under test by comparing each obtained operational result with a corresponding correct result comprises:
comparing each obtained operation result with a corresponding correct result to determine a first error rate of continuously executing multiple convolution operations in each of a plurality of time periods by a thread module in the chip to be tested;
generating a first relationship curve characterizing a relationship between an execution time period and a first error rate based on the first error rate; the first relation curve is used for evaluating the operation performance of the chip to be tested.
6. The method according to claim 1 or 2, wherein in the case that a plurality of thread modules in the chip to be tested execute convolution operation in parallel, the determining the operation performance of the chip to be tested by comparing each obtained operation result with a corresponding correct result includes:
determining the average error rate of the convolution operation executed by the plurality of thread modules in each time period by comparing the obtained operation results with the corresponding correct results;
generating a second relationship curve characterizing a relationship between execution time periods of the plurality of thread modules and the average error rate based on the average error rate; the second relation curve is used for evaluating the operation performance of the chip to be tested.
7. The method according to claim 1 or 2, wherein after determining the operational performance of the chip under test, the method further comprises:
and determining a target chip for executing neural network training and/or neural network reasoning from the plurality of chips to be tested according to the operation performance of each chip to be tested in the plurality of chips to be tested generated in the same batch.
8. A die pressure testing apparatus, comprising:
The acquisition module is used for acquiring the image to be detected and the convolution kernel;
the control module is used for controlling a thread module in the chip to be tested to continuously execute convolution operation for a plurality of times based on the image to be tested and the convolution kernel to obtain an operation result corresponding to each convolution operation;
the determining module is used for determining the operation performance of the chip to be tested by comparing each obtained operation result with a corresponding correct result;
the control module is used for controlling a thread module in the chip to be tested to continuously execute convolution operation for a plurality of times based on the image to be tested and the convolution kernel to obtain an operation result corresponding to each convolution operation, and is used for: based on the image to be detected and the convolution kernel, a plurality of thread modules in the chip to be detected are controlled to continuously execute convolution operation for a plurality of times in parallel, and an operation result corresponding to the convolution operation of each thread module is obtained;
after obtaining the image to be measured and the convolution kernel, before controlling the thread module in the chip to be measured to continuously execute convolution operation for a plurality of times based on the image to be measured and the convolution kernel to obtain an operation result corresponding to each convolution operation, the method further comprises the steps of:
the conversion module is used for converting each pixel characteristic value included in the image to be detected into a value under the target data type to obtain a converted image to be detected; and/or converting each convolution characteristic value included in the convolution kernel into a value under the target data type to obtain a converted convolution kernel.
9. An electronic device, comprising: a processor, a memory and a bus, said memory storing machine readable instructions executable by said processor, said processor and said memory communicating over the bus when the electronic device is running, said machine readable instructions when executed by said processor performing the steps of the chip stress test method according to any of claims 1 to 7.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when run by a processor, performs the steps of the chip pressure test method according to any of claims 1 to 7.
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