CN110008076A - Processor reliability estimation method, device, electronic equipment and storage medium - Google Patents
Processor reliability estimation method, device, electronic equipment and storage medium Download PDFInfo
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- CN110008076A CN110008076A CN201910231298.XA CN201910231298A CN110008076A CN 110008076 A CN110008076 A CN 110008076A CN 201910231298 A CN201910231298 A CN 201910231298A CN 110008076 A CN110008076 A CN 110008076A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
Abstract
A kind of processor reliability estimation method, applied to technical field of integrated circuits, it include: that failure instruction data is input in preset emulator, generate fault simulation result, judge whether fault simulation result is consistent with correct simulation result, if the fault simulation result is consistent with the correct simulation result, then update the failure instruction data, and according to the new failure instruction data, it executes this failure instruction data is input in preset emulator, the step of generating fault simulation result, if the fault simulation result and the correct simulation result are inconsistent, then it is recorded as single treatment device failure event, repeat abovementioned steps, until the number of processing failure event reaches preset times, then count the number for the failure instruction data accumulated in each processor failure event, the reliability of computation processor.The invention also discloses a kind of processor reliability assessment device, electronic equipment and storage mediums, can carry out reliability assessment in the design phase, calculate the reliability of processor.
Description
Technical field
The present invention relates to technical field of integrated circuits more particularly to a kind of processor reliability estimation methods, device, electronics
Equipment and storage medium.
Background technique
Processor is widely used in industrial automation, security monitoring, the fields such as machine vision.However, the α in encapsulating material
Charged particle, ray in particle or environment etc. interact with semiconductor material may cause processor generation transient state or permanent
Property failure.This phenomenon is known as single particle effect.With the continuous diminution of integrated circuit feature size, the raising of working frequency,
Single event upset effecf becomes the principal element for influencing vision processor reliability, and wherein reliability is finger processor given
In time interval, under rated condition, the probability that persistently works normally.
Failure generation method is widely used in the reliability of assessment circuit, wherein existing software fault generation method can be with
Transient fault and permanent fault are generated, and there is high flexibility and high controlling, but these methods are not carried out generation accumulation
Permanent fault and assessment processing device reliability.
Summary of the invention
The main purpose of the present invention is to provide a kind of processor reliability estimation method, device, electronic equipment and storages
Medium produces cumulative failure, and according to generation cumulative failure as a result, calculating the reliability of processor.
To achieve the above object, first aspect of the embodiment of the present invention provides a kind of processor reliability estimation method, comprising:
S1, failure instruction data is input in preset emulator, generates fault simulation result；
S2, judge whether the fault simulation result and correct simulation result are consistent, and the correct simulation result is by correct
Director data is input to the preset emulator and generates；
If S3, the fault simulation result are consistent with the correct simulation result, the failure instruction data is updated, it is raw
The failure instruction data of Cheng Xin, and according to the new failure instruction data, execute it is described failure instruction data is input to it is pre-
The step of setting in emulator, generating fault simulation result；
If S4, the fault simulation result and the correct simulation result are inconsistent, it is recorded as the failure of single treatment device
Event；
S5, step S1 to S4 is repeated, until the number of the processing failure event reaches preset times, then counts each described
The failure instruction data accumulated in processor failure event, the number of the failure instruction data based on each accumulation, at calculating
Manage the reliability of device.
Further, the failure instruction data is by randomly choosing and overturning the one digit number in the right instructions data
According to generation；
Described to update the failure instruction data, obtaining new failure instruction data includes:
The a data in the failure instruction data is randomly choosed and overturn, new failure instruction data is generated.
The further number of the failure instruction data based on each accumulation, the reliability packet of computation processor
It includes:
According to the failure instruction data of each accumulation, the probability of happening of the processor failure event is calculated；
According to the probability of happening of the processor failure event, and, the probability distribution of the failure instruction data of accumulation, meter
Calculate the reliability of the processor.
Further, the probability of happening for enabling the processor failure event after generating failure instruction data for the first time is p, the
The probability of happening of the processor failure event is a after k generation failure instruction datak, then akMeet geometry distribution:
ak=p (1-p)(k-1), k=1,2,3 ... ...
Further, enabling kth time generate the probability of failure instruction data is pk(t), then:
Wherein, t indicates the working time of the processor, and λ indicates the failure instruction data of average accumulated in the unit time
Number.
Further, the reliability for enabling the processor is R (t), then:
Further, the failure instruction data by by failure generate parameter and the right instructions data be input to by
It is generated in the failure generator of perl script design.
Second aspect of the embodiment of the present invention provides a kind of processor reliability assessment device, comprising:
Input module generates fault simulation result for failure instruction data to be input in preset emulator；
Judgment module, for judging whether the fault simulation result and correct simulation result are consistent, the correct emulation
As a result the preset emulator is input to by right instructions data to generate；
Update module updates the failure if consistent with the correct simulation result for the fault simulation result
Director data generates new failure instruction data, and according to the new failure instruction data, cuts the input module；
Logging modle is recorded as single treatment if the fault simulation result and the correct simulation result are inconsistent
Device failure event.
It is repeated in and executes input module, judgment module, update module and logging modle, until the processing failure event
Number reach preset times, then described device further include:
Statistical module, for counting the failure instruction data accumulated in each processor failure event；
Computing module, for the number of the failure instruction data based on each accumulation, the reliability of computation processor.
The third aspect of the embodiment of the present invention provides a kind of electronic equipment, comprising:
Memory, processor and storage are on a memory and the computer program that can run on a processor, feature exist
In the processor realizes the processor reliability assessment side that first aspect of the embodiment of the present invention provides when executing described program
Method.
Fourth aspect of the embodiment of the present invention provides a kind of computer readable storage medium, is stored thereon with computer journey
Sequence realizes the processor reliability assessment that first aspect of the embodiment of the present invention provides when the computer program is executed by processor
Method.
From the embodiments of the present invention it is found that processor reliability estimation method provided by the invention, device, electronic equipment
And storage medium, failure instruction data is input in preset emulator, generates fault simulation as a result, judging fault simulation result
It is whether consistent with correct simulation result, if the fault simulation result is consistent with the correct simulation result, update the faulting instruction
Data generate new failure instruction data, and according to the new failure instruction data, execute this and be input to failure instruction data
In preset emulator, generate fault simulation result the step of, if the fault simulation result and the correct simulation result are inconsistent,
It is recorded as single treatment device failure event, is then repeated the above process, until the number of processing failure event reaches preset times,
Then count the failure instruction data accumulated in each processor failure event, the number of the failure instruction data based on each accumulation, meter
The reliability of processor is calculated, reliability assessment can be carried out in the design phase, reduce cost, while according to the knot for generating cumulative failure
Fruit easily calculates the reliability of processor.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those skilled in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 is the flow diagram for the processor reliability estimation method that one embodiment of the invention provides；
Fig. 2 is the structural schematic diagram for the processor reliability assessment device that further embodiment of this invention provides；
Fig. 3 is the probability of happening for the processor failure event that further embodiment of this invention provides and of failure instruction data
Several theory relation curve graphs and experimental data figure；
Fig. 4 shows the hardware structure diagram of a kind of electronic equipment.
Specific embodiment
In order to make the invention's purpose, features and advantages of the invention more obvious and easy to understand, below in conjunction with the present invention
Attached drawing in embodiment, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described reality
Applying example is only a part of the embodiment of the present invention, and not all embodiments.Based on the embodiments of the present invention, those skilled in the art
Member's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Referring to Fig. 1, Fig. 1 is the flow diagram for the processor reliability estimation method that one embodiment of the invention provides,
This method can be applied to have in the electronic equipment of copying, and this method mainly comprises the steps that
S1, failure instruction data is input in preset emulator, generates fault simulation result；
Failure instruction data generates parameter by failure and right instructions data input fault generator obtains, specific manifestation
To randomly choose and overturning the generation failure instruction data of a data in right instructions data.Wherein, failure generate parameter by
Artificial setting, can be changed as needed.Right instructions data and test are updated using failure generator before emulation starts
Code (test-bench), can be in hardware description language (HDL, the Hardware Description for not changing processor
Language cumulative failure is generated under conditions of).
Wherein, right instructions data refer to that there is no crossing the director data of failure.
Director data refers to the binary instruction data that the processor generated by compiling can be run.More, can pass through
Perl script controls failure generator, is realized under the premise of not changing former design code to the quick tired of processor fault
Product.
Intelligible, failure generating process is independent of logic circuit emulator command, i.e., the preset emulator can make
With any logic circuit emulator.Meanwhile the HDL design code of processor being input in the preset emulator, it therefore, should
Preset emulator generates fault simulation result according to the failure instruction data and the HDL design code.
Further, which can carry out Method at Register Transfer Level (RTL, Register with high-speed simulation device
Transfer Level) emulation, simulation velocity is remarkably improved compared to netlist grade and gate level emulation.
S2, judge whether the fault simulation result and correct simulation result are consistent；
Wherein, correct simulation result is input to the preset emulator by right instructions data and generates, that is, the right instructions number
Correct simulation result is generated by the preset emulator according to above-mentioned HDL design code.
If the fault simulation result is consistent with the correct simulation result, S3 is thened follow the steps: updating the failure instruction data,
New failure instruction data is generated, according to new failure instruction data, executes step S1.
The failure instruction data is handled using above-mentioned failure generator, specifically, randomly choosing and overturning the event
Hinder 1 data in director data, generates new failure instruction data.Then the new failure instruction data of generation is inputted again
Into the preset emulator, fault simulation is generated as a result, judge whether the fault simulation result and correct simulation result are consistent, according to
This circulation, until obtained fault simulation result and the correct simulation result are inconsistent, i.e. proof processor failure executes step
S4: it is recorded as single treatment device failure event.
Wherein, the generation of failure instruction data is caused in director data by Single event upset effecf occurs in processor
Certain positions be flipped, i.e., " 0 " becomes " 1 ", and " 1 " becomes " 0 ".
S5, step S1 to S4 is repeated, until the number of processing failure event reaches preset times, then counts each processor and lose
The failure instruction data accumulated in effect event, the number of the failure instruction data based on each accumulation, the reliability of computation processor.
First according to the failure instruction data of each accumulation, the probability of happening of computation processor failure event.Then according to place
The probability of happening of device failure event is managed, and, the reliability of the probability distribution computation processor of the failure instruction data of accumulation.
Specifically, due to generate every time failure instruction data can approximation see independent experiment as, then enable first secondary
Probability of happening at failure instruction data preprocessor failure event is p, and kth time generates the processor mistake after failure instruction data
The probability of happening of effect event is ak, then akMeet geometry distribution:
ak=p (1-p)(k-1), k=1,2,3 ... ...
Enabling the kth time generate the probability of failure instruction data is pk(t), then:
T indicates the working time of processor, and λ indicates the number of the failure instruction data of average accumulated in the unit time.It can
Understand, the generating process of above-mentioned failure instruction data is regarded as the Poisson process that intensity is λ.Wherein, λ and processor work
Environment and the relevant relating to parameters of memory are estimated software using single event upset rate and are calculated.
Then, the reliability for enabling processor is R (t), then:
In embodiments of the present invention, failure instruction data is input in preset emulator, generates fault simulation as a result, sentencing
Whether disconnected fault simulation result and correct simulation result are consistent, if the fault simulation result is consistent with the correct simulation result,
The failure instruction data is updated, new failure instruction data is generated, and according to the new failure instruction data, executes this for failure
The step of director data is input in preset emulator, generates fault simulation result, if the fault simulation result is correct imitative with this
True result is inconsistent, then is recorded as single treatment device failure event, then repeats the above process, until time of processing failure event
Number reaches preset times, then counts the failure instruction data accumulated in each processor failure event, and the failure based on each accumulation refers to
The number of data is enabled, the reliability of computation processor can carry out reliability assessment in the design phase, reduce cost, while basis
Generate cumulative failure as a result, easily calculating the reliability of processor.
Referring to Fig. 2, Fig. 2 is the structural representation for the processor reliability assessment device that further embodiment of this invention provides
Figure, the device mainly includes:
Input module 201, judgment module 202, update module 203, logging modle 204, statistical module 205 and computing module
206。
Input module 201 generates fault simulation result for failure instruction data to be input in preset emulator.
When emulation starts, director data is input to corresponding memory.Instruction memory size in processor is 16KB,
Director data will not take whole memory spaces under normal circumstances, and a part of memory space is in idle state, in idle
The bit flipping of the memory space of state will not cause processor disabler.So the target selection that failure generates has instruction to store
Memory space.
Processor is mainly by a processor array, a RISC32 microcontroller and some peripheral circuit modules composition.
Wherein the memory of store instruction has RISC instruction memory and VMIPS command memory.RISC instruction memory is for storing
The instruction of microcontroller, algorithm instruction of the VMIPS command memory for storage processor operation.
In the present embodiment, selecting failure to generate target is the RISC instruction memory in processor, processor operation
Algorithm is the sorting algorithm based on convolutional neural networks (CNN, Convolutional Neural Networks).By microcontroller
The compiling of instruction of device is binary instruction data.Fig. 3 gives to be counted after methods experiment provided in an embodiment of the present invention
The probability of happening of processor failure event and the number of failure instruction data between relationship.It is secondary by experiment statistics first
After probability of happening p at failure instruction data preprocessor failure event, the generation that can calculate processor failure event is general
The theory relation curve of rate and the number of failure instruction data.The result of the result and theoretical calculation tested as seen from Figure 3 has
There is good consistency.
Judgment module 202, for judging whether the fault simulation result and correct simulation result are consistent, the correct emulation knot
Fruit is input to the preset emulator by right instructions data and generates.
Update module 203 updates the faulting instruction if consistent with the correct simulation result for the fault simulation result
Data generate new failure instruction data, and according to the new failure instruction data, cut the input module 201.
Logging modle 204 is recorded as single treatment device if the fault simulation result and the correct simulation result are inconsistent
Failure event.
It is repeated in and executes input module 201, judgment module 202, update module 203 and logging modle 204, until processing
The number of failure event reaches preset times, then the device further include:
Statistical module 205, for counting the failure instruction data accumulated in each processor failure event；
Computing module 206, for the number of the failure instruction data based on each accumulation, the reliability of computation processor.
In embodiments of the present invention, failure instruction data is input in preset emulator, generates fault simulation as a result, sentencing
Whether disconnected fault simulation result and correct simulation result are consistent, if the fault simulation result is consistent with the correct simulation result,
The failure instruction data is updated, new failure instruction data is generated, and according to the new failure instruction data, executes this for failure
The step of director data is input in preset emulator, generates fault simulation result, if the fault simulation result is correct imitative with this
True result is inconsistent, then is recorded as single treatment device failure event, then repeats the above process, until time of processing failure event
Number reaches preset times, then counts the failure instruction data accumulated in each processor failure event, and the failure based on each accumulation refers to
The number of data is enabled, the reliability of computation processor can carry out reliability assessment in the design phase, reduce cost, while basis
Generate cumulative failure as a result, easily calculating the reliability of processor.
Fig. 4 is referred to, Fig. 4 shows the hardware structure diagram of a kind of electronic equipment.
Electronic equipment as described in this embodiment, comprising:
Memory 31, processor 32 and it is stored in the computer program that can be run on memory 31 and on a processor, located
Reason device realizes processor reliability estimation method described in aforementioned embodiment illustrated in fig. 1 when executing the program.
Further, the electronic equipment further include:
At least one input equipment 33；At least one output equipment 34.
Above-mentioned memory 31,32 input equipment 33 of processor and output equipment 34 are connected by bus 35.
Wherein, input equipment 33 concretely camera, touch panel, physical button or mouse etc..Output equipment
34 concretely display screens.
Memory 31 can be high random access memory body (RAM, Random Access Memory) memory, can also
For nonvolatile storage (non-volatile memory), such as magnetic disk storage.Memory 31 is executable for storing one group
Program code, processor 32 are coupled with memory 31.
Further, the embodiment of the invention also provides a kind of computer readable storage medium, the computer-readable storages
Medium can be in the terminal being set in the various embodiments described above, which can be shown in earlier figures 4
Memory in embodiment.It is stored with computer program on the computer readable storage medium, when which is executed by processor
Realize processor reliability estimation method described in aforementioned embodiment illustrated in fig. 1.
In multiple embodiments provided herein, it should be understood that disclosed device and method can pass through it
Its mode is realized.For example, embodiments described above is only schematical, for example, the division of the module, only
A kind of logical function partition, there may be another division manner in actual implementation, for example, multiple module or components can combine or
Person is desirably integrated into another system, or some features can be ignored or not executed.Another point, shown or discussed is mutual
Between coupling or direct-coupling or communication linkage can be through some interfaces, the INDIRECT COUPLING or communication linkage of module can
To be electrically mechanical or other forms.
The module as illustrated by the separation member may or may not be physically separated, aobvious as module
The component shown may or may not be physical module, it can and it is in one place, or may be distributed over multiple
On network module.Some or all of the modules therein can be selected to realize the mesh of this embodiment scheme according to the actual needs
's.
It, can also be in addition, each functional module in each embodiment of the present invention can integrate in a processing module
It is that modules physically exist alone, can also be integrated in two or more modules in a module.Above-mentioned integrated mould
Block both can take the form of hardware realization, can also be realized in the form of software function module.
It should be noted that for the various method embodiments described above, describing for simplicity, therefore, it is stated as a series of
Combination of actions, but those skilled in the art should understand that, the present invention is not limited by the sequence of acts described because
According to the present invention, certain steps can use other sequences or carry out simultaneously.Secondly, those skilled in the art should also know
It knows, the embodiments described in the specification are all preferred embodiments, and related actions and modules might not all be this hair
Necessary to bright.
In the above-described embodiments, it all emphasizes particularly on different fields to the description of each embodiment, there is no the portion being described in detail in some embodiment
Point, it may refer to the associated description of other embodiments.
The above are to processor reliability estimation method provided by the present invention, device, electronic equipment and storage medium
Description, for those of ordinary skill in the art, thought according to an embodiment of the present invention, in specific embodiment and application range
Upper there will be changes, and to sum up, the contents of this specification are not to be construed as limiting the invention.
Claims (10)
1. a kind of processor reliability estimation method characterized by comprising
S1, failure instruction data is input in preset emulator, generates fault simulation result；
S2, judge whether the fault simulation result and correct simulation result are consistent, and the correct simulation result is by right instructions
Data are input to the preset emulator and generate；
If S3, the fault simulation result are consistent with the correct simulation result, the failure instruction data is updated, is generated new
Failure instruction data, and according to the new failure instruction data, execute it is described failure instruction data is input to it is preset imitative
In true device, generate fault simulation result the step of；
If S4, the fault simulation result and the correct simulation result are inconsistent, it is recorded as single treatment device failure event；
S5, step S1 to S4 is repeated, until the number of the processing failure event reaches preset times, then counts each processing
The failure instruction data accumulated in device failure event, the number of the failure instruction data based on each accumulation, computation processor
Reliability.
2. processor reliability estimation method according to claim 1, which is characterized in that the failure instruction data passes through
It randomly chooses and overturns the generation of a data in the right instructions data；
Described to update the failure instruction data, obtaining new failure instruction data includes:
The a data in the failure instruction data is randomly choosed and overturn, new failure instruction data is generated.
3. processor reliability estimation method according to claim 1 or 2, which is characterized in that described based on each described tired
The reliability of the number of long-pending failure instruction data, computation processor includes:
According to the failure instruction data of each accumulation, the probability of happening of the processor failure event is calculated；
According to the probability of happening of the processor failure event, and, the probability distribution of the failure instruction data of accumulation calculates institute
State the reliability of processor.
4. processor reliability estimation method according to claim 3, which is characterized in that enable and generate faulting instruction for the first time
The probability of happening of the processor failure event is p after data, and kth time generates the processor failure thing after failure instruction data
The probability of happening of part is ak, then akMeet geometry distribution:
ak=p (1-p)(k-1), k=1,2,3 ... ...
5. processor reliability estimation method according to claim 4, which is characterized in that kth time is enabled to generate faulting instruction
The probability of data is pk(t), then:
Wherein, t indicates the working time of the processor, and λ indicates of the failure instruction data of average accumulated in the unit time
Number.
6. processor reliability estimation method according to claim 4 or 5, which is characterized in that enable the processor can
It is R (t) by property, then:
7. processor reliability estimation method according to claim 1, which is characterized in that the failure instruction data passes through
Failure is generated into parameter and the right instructions data are input in the failure generator by perl script design and generate.
8. a kind of processor reliability assessment device characterized by comprising
Input module generates fault simulation result for failure instruction data to be input in preset emulator；
Judgment module, for judging whether the fault simulation result and correct simulation result are consistent, the correct simulation result
The preset emulator is input to by right instructions data to generate；
Update module updates the faulting instruction if consistent with the correct simulation result for the fault simulation result
Data generate new failure instruction data, and according to the new failure instruction data, cut the input module；
Logging modle is recorded as the mistake of single treatment device if the fault simulation result and the correct simulation result are inconsistent
Effect event.
It is repeated in and executes input module, judgment module, update module and logging modle, until time of the processing failure event
Number reaches preset times, then described device further include:
Statistical module, for counting the failure instruction data accumulated in each processor failure event；
Computing module, for the number of the failure instruction data based on each accumulation, the reliability of computation processor.
9. a kind of electronic equipment, comprising: memory, processor and storage are on a memory and the calculating that can run on a processor
Machine program, which is characterized in that when the processor executes the computer program, realize any one of claim 1 to 7 institute
The each step in processor reliability estimation method stated.
10. a kind of computer readable storage medium, is stored thereon with computer program, which is characterized in that the computer program
When being executed by processor, each step in processor reliability estimation method described in any one of claim 1 to 7 is realized
Suddenly.
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| CN113884857A (en) * | 2021-09-29 | 2022-01-04 | 上海阵量智能科技有限公司 | Chip, chip pressure testing method and device, electronic equipment and storage medium |
| CN113884857B (en) * | 2021-09-29 | 2024-03-08 | 上海阵量智能科技有限公司 | Chip, chip pressure testing method and device, electronic equipment and storage medium |
| CN115562969A (en) * | 2022-12-05 | 2023-01-03 | 深圳市唯特视科技有限公司 | Simulation evaluation method, system, electronic device and medium for neural network processor |
| CN115562969B (en) * | 2022-12-05 | 2023-04-07 | 深圳市唯特视科技有限公司 | Simulation evaluation method, system, electronic device and medium for neural network processor |
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