CN113872576A - Radio frequency switch circuit - Google Patents
Radio frequency switch circuit Download PDFInfo
- Publication number
- CN113872576A CN113872576A CN202111120386.6A CN202111120386A CN113872576A CN 113872576 A CN113872576 A CN 113872576A CN 202111120386 A CN202111120386 A CN 202111120386A CN 113872576 A CN113872576 A CN 113872576A
- Authority
- CN
- China
- Prior art keywords
- bias
- network
- radio frequency
- bias resistor
- port
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
- H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
- H03K17/04106—Modifications for accelerating switching without feedback from the output circuit to the control circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
Landscapes
- Electronic Switches (AREA)
Abstract
The invention discloses a radio frequency switch circuit, which is characterized in that a plurality of radio frequency transistors are cascaded to form a network, and the head end and the tail end of the network form an input/output port; a source-drain bias resistor is arranged between the source end and the drain end of each radio frequency transistor, the grid electrode of each radio frequency transistor is also connected with a grid electrode bias resistor, and a first bias resistor is also connected between the grid electrode bias resistors of each adjacent radio frequency transistor; the substrate electrodes of the radio frequency transistors are also connected with body end bias resistors, and a second bias resistor is connected between the body end bias resistors of every two adjacent radio frequency transistors; both ends of the first bias resistor and both ends of the second bias resistor are connected with the switch networks with the same structure in parallel; the two ends of the first bias resistor or the second bias resistor are short-circuited or open-circuited by switching on or off of the switch network; and accelerating charge and discharge of charges at two ends of the first bias resistor or the second bias resistor during short circuit.
Description
Technical Field
The present invention relates to semiconductor devices and manufacturing, and more particularly to a radio frequency switch circuit for a radio frequency front end.
Background
The rf switch is a commonly used device in the rf path, and is used to control the rf signal transmission path and the signal size, and its performance indexes include isolation, insertion loss, and switching time.
The radio frequency switch comprises a conduction switch and an antenna switch, wherein the conduction switch is used for communicating any one path or a plurality of paths of radio frequency signals through control logic so as to realize the switching of different signal paths, including the switching of receiving and transmitting, the switching between different frequency bands and the like. The mobile intelligent terminal comprises a mobile communication conduction switch, a WiFi switch and the like, and is widely applied to mobile intelligent terminals such as smart phones.
The antenna switch is one of radio frequency switches, is directly connected with an antenna and is mainly used for tuning the transmission performance of antenna signals to ensure that the antenna signals achieve optimal efficiency at any applicable frequency; or alternatively, the antenna channel with the best performance is selected. The working principle of the radio frequency switch is mainly as follows: when different voltages are applied to the control ports of the radio frequency switch, the ports of the radio frequency switch can present different connectivity. Taking a single-pole double-throw radio frequency switch as an example, the single-pole double-throw radio frequency switch comprises 4 input/output ports 1-4, when a positive voltage is applied to a control port, a circuit connecting a port 2 and a port 3 is conducted, and meanwhile, a circuit connecting the port 2 and the port 3 is disconnected; when the control port is applied with zero voltage, the circuit of the connection port 1 and the connection port 3 is disconnected, and the circuit of the connection port 2 and the connection port 3 is conducted.
The radio frequency switching time is an important performance index of the radio frequency switch, and the radio frequency switching time of the device comprises the transient use time of the radio frequency switch and the switching use time of the radio frequency switch. The radio frequency switch transient is used as follows: when the radio frequency switch is turned on, the radio frequency output is increased from 10% to 90% of the required time (when the radio frequency switch is started), or when the radio frequency switch is turned on, the radio frequency output is decreased from 90% to 10% of the required time (when the radio frequency switch is turned off). The switching time of the radio frequency switch is as follows: when the radio frequency switch is turned on, the time required from the control voltage being at the 50% point to the increase of the radio frequency output reaching 90% is started, or when the radio frequency switch is turned off, the time required from the control voltage being at the 50% point to the decrease of the radio frequency output reaching 10%.
In the structure of the radio frequency switch circuit, a switch network is formed by cascading a plurality of transistors and corresponding bias resistors, and the switching time is limited by the transistor size and the bias resistor network of the transistor grid and body terminals:
to reduce the insertion loss of the switch, the size of the transistor is generally increased, which results in an increased switching time for turning on and off the rf switch.
In order to increase the breakdown voltage BV of the switch, the number of transistor stages is usually increased, and the increase of the number of transistor stages also increases the on/off switching time of the rf switch.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a radio frequency switch circuit, which can optimize the performance of the switch time.
In order to solve the above problems, the rf switch circuit according to the present invention includes a plurality of rf transistors cascaded in a network, and the head and tail ends of the network form an input/output port of the rf switch circuit.
The plurality of radio frequency transistors are provided with source drain bias resistors between the source and drain ends of each radio frequency transistor, the grid of each radio frequency transistor is also connected with a grid bias resistor, and a first bias resistor is also connected between the grid bias resistors of each adjacent radio frequency transistor.
The substrate electrodes of the radio-frequency transistors are also connected with body end bias resistors, and a second bias resistor is connected between the body end bias resistors of every two adjacent radio-frequency transistors.
The two ends of the first bias resistor are connected with a switch network in parallel, and the two ends of the first bias resistor are short-circuited or open-circuited by switching on or off the switch network; and accelerating charge and discharge of charges at two ends of the first biasing resistor during short circuit.
The two ends of the second biasing resistor are connected in parallel with a switch network, and the structure of the switch network is the same as that of the switch network connected in parallel with the two ends of the first biasing resistor; the two ends of the second bias resistor are short-circuited or opened through the connection or disconnection of the switch network; and accelerating charge and discharge of charges at two ends of the second biasing resistor during short circuit.
In a further improvement, the switch network is configured as a switch controlled by a control signal.
In a further improvement, the first bias resistor leads out a VG port at the head end or the tail end of the network.
In a further improvement, the second bias resistor is led out of the VB port at the head end or the tail end of the network.
In a further refinement, the switching network is switched on or off under the control of an external control signal.
The further improvement is that the radio frequency transistors are cascaded to form a network, and input and output ports formed at the head end and the tail end of the network are respectively connected with a transmitter or a receiver.
Or, the switch network has a structure that a first bias transistor is connected across two ends of each of the plurality of first bias resistors, a source end and a drain end of the first bias transistor are respectively connected across two ends of the first bias resistor to form a cascade network, and a substrate of the first bias transistor is all led out through the bias resistors and connected together to form a VBSUG port.
The gates of the first bias transistors are connected together through a bias resistor to form a VGSUG port.
The two ends of the second bias resistor are also provided with the switch network with the structure, the source end and the drain end of the second bias transistor are respectively bridged at the two ends of the second bias resistor, and the substrates of the second bias transistor are all led out through the bias resistor and connected together to form a VBSUB port.
The gates of the second biasing transistors are connected together through biasing resistors to form a VGSUB port.
The further improvement is that the VBSUG port, the VGSUG port, the VBSUB port and the VGSUB port are controlled by external timing signals, and the short circuit or the open circuit of two ends of the first bias resistor and the second bias resistor is formed by controlling the switch network through the external timing signals; when the two ends of the first bias resistor or the second bias resistor are short-circuited, the charging and discharging speed of the first bias resistor or the second bias resistor is increased.
Or, the switch network has a structure that a first bias transistor is connected across two ends of each of the plurality of first bias resistors, and a source end and a drain end of each of the first bias transistors are respectively connected to two ends of each of the first bias resistors to form a cascade network; the grids of the first bias transistors are respectively led out, a bias resistor is connected in series between the grids of every two adjacent first bias transistors to form a cascade network, and a VGSUG port is led out from the tail end of the cascade network.
Substrate electrodes of the first bias transistors are respectively led out, a bias resistor is connected in series between the substrate electrodes of every two adjacent first bias transistors to form a cascade network, and a VBSUG port is led out from the tail end of the cascade network.
The two ends of the second bias resistor are also provided with the switch network, the source end and the drain end of the second bias transistor are respectively bridged at the two ends of the second bias resistor, the grid electrodes of the second bias transistors are respectively led out, a bias resistor is connected in series between the grid electrodes of every two adjacent second bias transistors to form a cascade network, and a VGSUB port is led out from the tail end of the network.
Substrate electrodes of the second bias transistors are respectively led out, a bias resistor is connected in series between the substrate electrodes of every two adjacent second bias transistors to form a cascade network, and a VBSUB port is led out from the network tail end of the cascade network.
The further improvement is that the VBSUG port, the VGSUG port, the VBSUB port and the VGSUB port are controlled by external timing signals, and the short circuit or the open circuit of two ends of the first bias resistor and the second bias resistor is formed by controlling the switch network through the external timing signals; when the two ends of the first bias resistor or the second bias resistor are short-circuited, the charging and discharging speed of the first bias resistor or the second bias resistor is increased.
The invention connects a switch network in parallel at two ends of the bias resistor of the radio frequency transistor, realizes short circuit or open circuit at two ends of the bias resistor of the radio frequency transistor through on-off formed by the switch network, and conducts the switch network for a period of time between on-off switching, and accelerates charge and discharge when two ends of the bias resistor of the radio frequency transistor are short-circuited by the switch network, thereby reducing switching time.
Drawings
Fig. 1 is a schematic diagram of the structural principle of the rf switch circuit of the present invention.
Fig. 2 is a schematic structural diagram of a first embodiment of the rf switch circuit of the present invention.
Fig. 3 is a schematic structural diagram of a second embodiment of the rf switch circuit of the present invention.
FIG. 4 is a timing diagram of signals at each port according to the present invention.
Detailed Description
The following detailed description of the present invention is provided with reference to the accompanying drawings, and the technical solutions in the present invention will be clearly and completely described, but the present invention is not limited to the following embodiments. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is noted that the drawings are in greatly simplified form and that non-precision ratios are used for convenience and clarity only to aid in the description of the embodiments of the invention. All other embodiments obtained by a person skilled in the art without making any inventive step are within the scope of protection of the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout. It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further explained below by combining the specific drawings.
The structure principle of the radio frequency switch circuit is shown in figure 1, a plurality of radio frequency transistors (FETs 1-N in the figure, N is a natural number) are cascaded to form a network, the head end and the tail end of the network form an input/output port of the radio frequency switch circuit, for example, an RF1 port close to a radio frequency transistor FETN in figure 1 and an RF2 port close to a radio frequency transistor FET1, and the input/output ports RF1 and RF2 can be respectively connected with a transmitter or a receiver.
The plurality of radio frequency transistors are provided with source-drain bias resistors (resistors connected between the source and the drain of the radio frequency transistors in parallel in the figure) between the source and the drain of each radio frequency transistor, the grid of each radio frequency transistor is also connected with a grid bias resistor, and a first bias resistor is also connected between the grid bias resistors of every two adjacent radio frequency transistors. The number of the first bias resistors corresponds to the number of the radio frequency transistors, the first bias resistors are cascaded one by one to form a network by the structure, and finally a signal port VG is formed at the tail end of the network.
The substrate electrodes of the radio-frequency transistors are also connected with body end bias resistors, and a second bias resistor is connected between the body end bias resistors of every two adjacent radio-frequency transistors. The number of the second bias resistors corresponds to the number of the radio frequency transistors, the second bias resistors are cascaded one by one to form a network by the structure, and finally, a signal port VB is formed at the tail end of the network.
The two ends of the first bias resistor are also connected in parallel with a switch (network), as shown in a dashed box in fig. 1, and the two ends of the first bias resistor are short-circuited or open-circuited by switching on or off the switch network; and accelerating charge and discharge of charges at two ends of the first biasing resistor during short circuit.
And the two ends of the second biasing resistor are also connected with a switch network in parallel, and the structure of the switch network is the same as that of the switch network connected with the two ends of the first biasing resistor in parallel. The two ends of the second bias resistor are short-circuited or opened through the connection or disconnection of the switch network; and accelerating charge and discharge of charges at two ends of the second biasing resistor during short circuit.
The above-mentioned switch network structure is controlled by external control signal, so that the switch network forms on/off mode.
In a further improvement, the first bias resistor leads out a VG port at the head end or the tail end of the network.
In a further improvement, the second bias resistor is led out of the VB port at the head end or the tail end of the network.
The following describes the actual configuration of the above-mentioned switch network by taking two embodiments, and the functions of the above-mentioned switch network are realized by the circuit configurations of the following two embodiments, and the following two embodiments are only explained for different switch network configurations, and the same part is the rest of the configuration in fig. 1 except the dashed line box.
Example one
The switch network is structured such that, as shown in fig. 2, a first bias transistor is connected across two ends of each of the plurality of first bias resistors, a source terminal and a drain terminal of the first bias transistor are respectively connected to two ends of the first bias resistor to form a cascade network, and substrates of the first bias transistors are all led out through the bias resistors and then connected together to form a VBSUG port.
The grids of the first bias transistors are connected together through bias resistors to form a VGSUG port.
The two ends of the second bias resistor are also provided with the switch network with the structure, the source end and the drain end of the second bias transistor are respectively bridged at the two ends of the second bias resistor, and the substrates of the second bias transistor are all led out through the bias resistor and connected together to form a VBSUB port.
The gates of the second biasing transistors are connected together through biasing resistors to form a VGSUB port.
The VBSUG port, the VGSUG port, the VBSUB port and the VGSUB port are controlled by external timing signals, and short circuit or open circuit of two ends of the first bias resistor and the second bias resistor is formed by controlling the switch network through the external timing signals; when the two ends of the first bias resistor or the second bias resistor are short-circuited, the charging and discharging speed of the first bias resistor or the second bias resistor is increased.
The other ports are as before VG, VB.
Example two
The switch network is configured such that, as shown in fig. 3, a first bias transistor is connected across both ends of the plurality of first bias resistors, and a source terminal and a drain terminal of the first bias transistor are respectively connected to both ends of the first bias resistor to form a cascade network; the grids of the first bias transistors are respectively led out, a bias resistor is connected in series between the grids of every two adjacent first bias transistors to form a cascade network, and a VGSUG port is led out from the tail end of the cascade network.
Substrate electrodes of the first bias transistors are respectively led out, a bias resistor is connected in series between the substrate electrodes of every two adjacent first bias transistors to form a cascade network, and a VBSUG port is led out from the tail end of the cascade network.
The two ends of the second bias resistor are also provided with the switch network, the source end and the drain end of the second bias transistor are respectively bridged at the two ends of the second bias resistor, the grid electrodes of the second bias transistor are respectively led out, a bias resistor is connected in series between the grid electrodes of every two adjacent second bias transistors to form a cascade network, and a VGSUB port is led out from the tail end of the network.
Substrate electrodes of the second bias transistors are respectively led out, a bias resistor is connected in series between the substrate electrodes of every two adjacent second bias transistors to form a cascade network, and a VBSUB port is led out from the network tail end of the cascade network.
The VBSUG port, the VGSUG port, the VBSUB port and the VGSUB port are controlled by external timing signals, and short circuit or open circuit of two ends of the first bias resistor and the second bias resistor is formed by controlling the switch network through the external timing signals; when the two ends of the first bias resistor or the second bias resistor are short-circuited, the charging and discharging speed of the first bias resistor or the second bias resistor is increased.
The other ports are as before VG, VB.
The invention connects a switch network in parallel at two ends of the bias resistor of the radio frequency transistor, realizes short circuit or open circuit at two ends of the bias resistor of the radio frequency transistor through on-off formed by the switch network, and conducts the switch network for a period of time between on-off switching, and accelerates charge and discharge when two ends of the bias resistor of the radio frequency transistor are short-circuited by the switch network, thereby reducing switching time. As shown in fig. 4, a switching speed curve diagram of the RF switch obtained after the structure of the first embodiment or the second embodiment of the present invention is tested by providing corresponding timing sequences to each port, including inputting corresponding timing sequences to each port of VG, VB, VGSUG, VBSUG, VGSUB, and VBSUB, controlling the open and closed states of the entire switch network, and increasing the charging and discharging speed of the bias resistor to increase the switching speed of the RF2 port.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A radio frequency switch circuit, characterized by: the radio frequency switch circuit is formed by cascading N radio frequency transistors into a network, wherein N is a natural number which is more than or equal to 1; the head end and the tail end of the network form an input/output port of the radio frequency switch circuit;
the plurality of radio frequency transistors are provided with source drain bias resistors between the source and drain ends of each radio frequency transistor, the grid of each radio frequency transistor is also connected with a grid bias resistor, and a first bias resistor is also connected between the grid bias resistors of each adjacent radio frequency transistor;
the substrate electrodes of the radio frequency transistors are also connected with body end bias resistors, and a second bias resistor is connected between the body end bias resistors of every two adjacent radio frequency transistors;
the two ends of the first bias resistor are connected with a switch network in parallel, and the two ends of the first bias resistor are short-circuited or open-circuited by switching on or off the switch network; accelerating charge and discharge of charges at two ends of the first biasing resistor during short circuit;
the two ends of the second biasing resistor are connected in parallel with a switch network, and the structure of the switch network is the same as that of the switch network connected in parallel with the two ends of the first biasing resistor; the two ends of the second bias resistor are short-circuited or opened through the connection or disconnection of the switch network; and accelerating charge and discharge of charges at two ends of the second biasing resistor during short circuit.
2. The radio frequency switch circuit of claim 1, wherein: the structure of the switch network is a switch controlled by a control signal.
3. The radio frequency switch circuit of claim 1, wherein: the first bias resistor is led out from a VG port at the head end or the tail end of the network.
4. The radio frequency switch circuit of claim 1, wherein: the second bias resistor is led out of a VB port at the head end or the tail end of the network.
5. The radio frequency switch circuit of claim 1, wherein: the switching on or off of the switching network is controlled by an external control signal.
6. The radio frequency switch circuit of claim 1, wherein: the radio frequency transistors are cascaded to form a network, and input and output ports formed at the head end and the tail end of the network are respectively connected with a transmitter or a receiver.
7. The radio frequency switch circuit of claim 1, wherein: the switch network is structurally characterized in that a first bias transistor is connected across two ends of each of the plurality of first bias resistors, a source end and a drain end of each first bias transistor are respectively connected to two ends of each first bias resistor to form a cascade network, and a substrate of each first bias transistor is led out and connected together through the corresponding bias resistor to form a VBSUG port;
the grids of the first bias transistors are connected together through bias resistors to form a VGSUG port;
the two ends of the second bias resistor are also provided with the switch network with the structure, the source end and the drain end of the second bias transistor are respectively bridged at the two ends of the second bias resistor, and the substrate of the second bias transistor is led out and connected together after passing through the bias resistor to form a VBSUB port;
and the grids of the second biasing transistors are connected together through biasing resistors to form a VGSUB port.
8. The radio frequency switch circuit of claim 7, wherein: the VBSUG port, the VGSUG port, the VBSUB port and the VGSUB port are controlled by external timing signals, and short circuit or open circuit of two ends of the first bias resistor and the second bias resistor is formed by controlling the switch network through the external timing signals; when the two ends of the first bias resistor or the second bias resistor are short-circuited, the charging and discharging speed of the first bias resistor or the second bias resistor is increased.
9. The radio frequency switch circuit of claim 1, wherein: the switch network is structurally characterized in that a first bias transistor is connected across two ends of each of the plurality of first bias resistors, and a source end and a drain end of each first bias transistor are respectively connected to two ends of each first bias resistor to form a cascade network; the grids of the first bias transistors are respectively led out, a bias resistor is connected in series between the grids of every two adjacent first bias transistors to form a cascade network, and a VGSUG port is led out from the tail end of the cascade network;
substrate electrodes of the first bias transistors are respectively led out, a bias resistor is connected in series between the substrate electrodes of every two adjacent first bias transistors to form a cascade network, and a VBSUG port is led out from the tail end of the cascade network;
the two ends of the second bias resistor are also provided with the switch network, the source end and the drain end of the second bias transistor are respectively bridged at the two ends of the second bias resistor, the grid electrodes of the second bias transistors are respectively led out, a bias resistor is connected in series between the grid electrodes of every two adjacent second bias transistors to form a cascade network, and a VGSUB port is led out from the tail end of the network;
substrate electrodes of the second bias transistors are respectively led out, a bias resistor is connected in series between the substrate electrodes of every two adjacent second bias transistors to form a cascade network, and a VBSUB port is led out from the network tail end of the cascade network.
10. The radio frequency switch circuit of claim 9, wherein: the VBSUG port, the VGSUG port, the VBSUB port and the VGSUB port are controlled by external timing signals, and short circuit or open circuit of two ends of the first bias resistor and the second bias resistor is formed by controlling the switch network through the external timing signals; when the two ends of the first bias resistor or the second bias resistor are short-circuited, the charging and discharging speed of the first bias resistor or the second bias resistor is increased.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111120386.6A CN113872576A (en) | 2021-09-24 | 2021-09-24 | Radio frequency switch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111120386.6A CN113872576A (en) | 2021-09-24 | 2021-09-24 | Radio frequency switch circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113872576A true CN113872576A (en) | 2021-12-31 |
Family
ID=78993759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111120386.6A Pending CN113872576A (en) | 2021-09-24 | 2021-09-24 | Radio frequency switch circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113872576A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117614427A (en) * | 2024-01-19 | 2024-02-27 | 上海安其威微电子科技有限公司 | Switch module, switch switching method and radio frequency switch device |
-
2021
- 2021-09-24 CN CN202111120386.6A patent/CN113872576A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117614427A (en) * | 2024-01-19 | 2024-02-27 | 上海安其威微电子科技有限公司 | Switch module, switch switching method and radio frequency switch device |
| CN117614427B (en) * | 2024-01-19 | 2024-04-26 | 上海安其威微电子科技有限公司 | Switch module, switch switching method and radio frequency switch device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10090834B2 (en) | Radio frequency antenna switch | |
| CN102185594B (en) | Single pole multi throw switch | |
| US7221207B2 (en) | Semiconductor switching circuit for switching the paths of a high frequency signal in a mobile communications unit | |
| US7817966B2 (en) | Switching device with reduced intermodulation distortion | |
| US5945867A (en) | Switch circuit device | |
| CN105049015B (en) | The single-pole double throw RF switch and hilted broadsword of single-pole single-throw(SPST RF switch and its composition throw RF switch more | |
| EP2008362B1 (en) | High-frequency switching device with reduced harmonics | |
| US20090073078A1 (en) | Systems, Methods and Apparatuses for High Power Complementary Metal Oxide Semiconductor (CMOS) Antenna Switches Using Body Switching and External Component in Multi-Stacking Structure | |
| CN105322933A (en) | System and Method for a Radio Frequency Switch | |
| CN105049012A (en) | System and Method for a Radio Frequency Integrated Circuit | |
| CN108736866B (en) | CMOS SOI radio frequency switch circuit | |
| CN105049016B (en) | The single-pole double throw RF switch and hilted broadsword of single-pole single-throw(SPST RF switch and its composition throw RF switch more | |
| US7646260B2 (en) | Switching device with selectable phase shifting modes for reduced intermodulation distortion | |
| CN113872576A (en) | Radio frequency switch circuit | |
| CN104935317A (en) | CMOS SOI radio frequency switch structure capable of realizing low insertion loss and low harmonic | |
| CN104682936A (en) | CMOS SOI (Complementary Metal-Oxide-Semiconductor Transistor Silicon On Insulator) radio frequency switch structure with body region self-adapted bias function | |
| CN115225073A (en) | Novel double-mode change-over switch | |
| CN101420055A (en) | Single-pole double-throw switch based on E PHEMT | |
| CN113595542B (en) | Single-pole double-throw radio frequency switch | |
| CN216599573U (en) | Radio frequency switch subunit and radio frequency switch | |
| CN114374379A (en) | Single-chip positive-voltage controlled low-control-voltage high-power-capacity single-pole double-throw switch | |
| CN209767491U (en) | single-pole single-throw radio frequency switch and single-pole double-throw radio frequency switch and single-pole multi-throw radio frequency switch formed by same | |
| CN112491407A (en) | Coupling type single-pole double-throw switch applied to radio frequency integrated circuit | |
| US10171076B2 (en) | Independent control of branch FETs for RF performance improvement | |
| CN212935887U (en) | Antenna tuning switch with parallel branch having high voltage-resistant capability |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |