CN113595542B - Single-pole double-throw radio frequency switch - Google Patents
Single-pole double-throw radio frequency switch Download PDFInfo
- Publication number
- CN113595542B CN113595542B CN202111156263.8A CN202111156263A CN113595542B CN 113595542 B CN113595542 B CN 113595542B CN 202111156263 A CN202111156263 A CN 202111156263A CN 113595542 B CN113595542 B CN 113595542B
- Authority
- CN
- China
- Prior art keywords
- transistor
- ant
- channel
- resistors
- transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 34
- 230000003068 static effect Effects 0.000 claims abstract description 23
- 230000000087 stabilizing effect Effects 0.000 claims description 47
- 230000006641 stabilisation Effects 0.000 claims description 3
- 238000011105 stabilization Methods 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 230000002457 bidirectional effect Effects 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000010295 mobile communication Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
Abstract
The invention provides a single-pole double-throw radio frequency switch which is provided with an ANT antenna input port, wherein a TX-ANT channel, an ANT-RX channel and an electrostatic discharge channel are connected with the ANT antenna input port; the TX-ANT channel and the ANT-RX channel both comprise a series branch knot and a parallel branch knot; the static leakage channels are provided with three groups, the output end of each group of static leakage channels is grounded, the input end of each group of static leakage channels is lapped on an ANT antenna input port, the input end of each group of static leakage channels is lapped on a TX port, and the input end of each group of static leakage channels is lapped on an RX port. According to the invention, the bidirectional diode is bridged at two ends of the capacitor of the electrostatic discharge channel, so that a small parasitic effect is introduced while the chip is subjected to electrostatic protection, and the impedance matching performance and linearity of the channel are improved.
Description
Technical Field
The invention belongs to the technical field of wireless communication radio frequency switches, and particularly relates to a single-pole double-throw radio frequency switch.
Background
With the continuous development of mobile communication technology, the fifth generation mobile communication technology has become mature, and the influence of the performance of the radio frequency switch in the communication system on the whole transceiving system is more and more obvious. In addition to the two important indexes of the traditional insertion loss and the isolation degree of the radio frequency switch, the high power processing capability and the better linearity are also the key factors influencing the performance of the switch.
The traditional radio frequency switch circuit structure adopts a structure that a series branch knot and a parallel branch knot are combined, the series branch knot is necessary for the radio frequency switch circuit, and the introduction of a parallel branch circuit can greatly improve the isolation degree between ports and simultaneously influence the insertion loss of a channel and the impedance matching at the ports. The parasitic capacitance and the parasitic resistance component introduced by the parallel branch knot also deteriorate the linearity of the channel. Meanwhile, in order to prevent the core circuit of the radio frequency switch chip from being burnt out by external electrostatic breakdown, an additional electrostatic discharge channel is required to be added at each port of the chip.
However, the increase of the electrostatic discharge path and its parasitic effect can have a serious impact on the matching and linearity of the switch path.
Disclosure of Invention
Aiming at the defects brought by the electrostatic discharge channel in the prior art, the invention provides the single-pole double-throw radio frequency switch, a novel radio frequency switch circuit structure is adopted, and a bidirectional diode is bridged at two ends of a capacitor of the electrostatic discharge channel, so that a chip is ensured to introduce a small parasitic effect while carrying out electrostatic protection, and the impedance matching performance and the linearity of the channel are improved.
The specific implementation content of the invention is as follows:
the invention provides a single-pole double-throw radio frequency switch which is provided with an ANT antenna input port, wherein a TX-ANT channel, an ANT-RX channel and an electrostatic discharge channel are connected with the ANT antenna input port; the TX-ANT channel and the ANT-RX channel both comprise a series branch knot and a parallel branch knot;
the input port of the ANT antenna is respectively connected with the series branches of the TX-ANT channel and the ANT-RX channel, and then connected with the corresponding parallel branches through the respective connected series branches to lead out the corresponding TX port and RX port;
the series branch of the TX-ANT channel comprises n series transistors, and the parallel branch of the TX-ANT channel comprises m series transistors; the series branch of the ANT-RX channel comprises m series transistors, and the parallel branch of the ANT-RX channel comprises n series transistors; the gates of the transistors in the series branch of the TX-ANT channel and the parallel branch of the ANT-RX channel are connected with a logic control level VC; the grid electrodes of the transistors of the parallel branch of the TX-ANT channel and the series branch of the ANT-RX channel are connected with a logic control level NVC; the amplitude of the logic control level VC is equal to that of the logic control level NVC, and the phase difference is 180 degrees;
the static leakage channels are provided with three groups, the output end of each group of static leakage channels is grounded, the input ends of one group of static leakage channels are lapped on an ANT antenna input port, the input ends of one group of static leakage channels are lapped on a TX port, and the input ends of one group of static leakage channels are lapped on an RX port;
the electrostatic discharge channel comprises a transistor M1-a transistor Mk, wherein k groups of transistors are connected in series through the source and the drain of each transistor; the value of k is equal to the larger of the value m and the value n;
a capacitor C is respectively connected to the source electrode of the transistor M1 and the drain electrode of the transistor Mk in a bridging mode; two diode groups connected in parallel are lapped at two ends of each capacitor C; one diode group comprises a plurality of diodes with the same direction, and the inter-group directions of two groups of diode groups corresponding to one capacitor C are opposite;
the gates of the transistors M1 and Mk are connected with a logic control low level VC 1;
the input end of the capacitor C connected to the source of the transistor M1 is the input end of the electrostatic discharge channel, and the output end of the capacitor C connected to the drain of the transistor Mk is the output end of the electrostatic discharge channel.
In order to better implement the present invention, the serial branch of the TX-ANT channel is provided with n transistors, i.e., a transistor M11-a transistor M1n, the n transistors are connected in series through the source and the drain of each other, the source of the transistor M11 is connected to the ANT antenna input port, and the drain of the transistor M1n is connected to the parallel branch of the TX-ANT channel
N +1 transistor constant voltage resistors R1, n transistor stabilizing resistors R2 and n level stabilizing resistors Rb are arranged in the series branch of the TX-ANT channel;
n-1 transistor constant voltage resistors R1 are respectively lapped between the source and the drain of the transistor M11-the transistor M1n, and two transistor constant voltage resistors R1 are respectively lapped on the source of the transistor M11 and the drain of the transistor M1 n; then n +1 transistors of the serial branch of the TX-ANT channel are connected with equal voltage resistors R1 in an overlapping mode;
the n transistor stabilizing resistors R2 are respectively and correspondingly lapped on the grid electrodes of the transistor M11-the transistor M1n and then are connected with a logic control level VC;
the n level stabilizing resistors Rb are grounded and correspondingly connected to the body ends of the transistor M11 and the transistor M1n respectively.
In order to better realize the invention, the parallel branch of the TX-ANT channel is provided with m transistors, namely a transistor N11 and a transistor N1m, wherein the m transistors are connected in series through the source and the drain of each other and then connected in parallel and lapped on the TX-ANT channel through the drain of a transistor N11;
m transistor constant-voltage resistors R1, m transistor stable resistors R2 and m level stable resistors Rb are arranged in parallel branches of the TX-ANT channel;
the m transistor constant voltage resistors R1 are correspondingly lapped on the source and the drain of one transistor of the transistors N11-N1 m respectively;
the m transistor stabilizing resistors R2 are correspondingly lapped on the grid electrode of one transistor from the transistor N11 to the transistor N1m respectively and then are connected with a logic control level NVC;
m of the level stabilizing resistors Rb are grounded and then respectively and correspondingly connected to the body terminal of one of the transistors N11-N1 m.
In order to better implement the present invention, a fixed resistor R3 is further disposed in the parallel branch of the TX-ANT channel, the fixed resistor R3 is grounded and then connected to the source of the transistor N1m, and the resistance of the fixed resistor R3 is 50 ohms.
In order to better implement the present invention, the serial branch of the ANT-RX channel is provided with M transistors M21-M2M, the M transistors are connected in series through their sources and drains, the source of the transistor M21 is connected to the ANT antenna input port, the drain of the transistor M2M is connected to the parallel branch of the ANT-RX channel
M +1 transistor constant voltage resistors R1, m transistor stabilizing resistors R2 and m level stabilizing resistors Rb are arranged in the series branch of the ANT-RX channel;
m-1 transistor constant voltage resistors R1 are respectively lapped between the source and the drain of the transistor M21-the transistor M2M, and two transistor constant voltage resistors R1 are respectively lapped on the source of the transistor M21 and the drain of the transistor M2M; then m +1 transistors of the serial branch of the ANT-RX channel are connected with equal voltage resistors R1 in an overlapping mode;
the M transistor stabilizing resistors R2 are respectively and correspondingly lapped on the grid electrodes of the transistor M21-the transistor M2M and then are connected with a logic control level VC;
m level stabilizing resistors Rb are grounded and correspondingly connected to the body terminals of the transistor M21-the transistor M2M respectively.
In order to better implement the invention, the parallel branch of the ANT-RX channel is provided with N transistors, namely a transistor N21 and a transistor N2N, wherein the N transistors are connected in series through the source and the drain of each other and then connected in parallel on the ANT-RX channel through the drain of a transistor N21;
n transistor constant voltage resistors R1, n transistor stable resistors R2 and n level stable resistors Rb are arranged in parallel branches of the ANT-RX channel;
the N transistor constant voltage resistors R1 are correspondingly lapped on the source and the drain of one transistor of the transistors N21-N2N respectively;
the N transistor stabilizing resistors R2 are correspondingly lapped on the grid electrode of one transistor from the transistor N21 to the transistor N2N respectively and then are connected with a logic control level NVC;
the N level stabilizing resistors Rb are grounded and respectively connected to the body terminal of one of the transistors N21-N2N.
In order to better implement the present invention, a fixed resistor R3 is further disposed in the parallel branch of the ANT-RX channel, the fixed resistor R3 is grounded and then connected to the source of the transistor N2N, and the resistance of the fixed resistor R3 is 50 ohms.
In order to better implement the invention, further, each electrostatic discharge channel is further provided with k +1 transistor equal-voltage resistors R1, k transistor stabilizing resistors R2 and k level stabilizing resistors Rb;
k-1 transistor constant voltage resistors R1 are respectively lapped between the source and the drain of the transistor M1-transistor Mk, and two transistor constant voltage resistors R1 are respectively lapped on the source of the transistor M1 and the drain of the transistor Mk;
k transistor stabilization resistors R2 are respectively and correspondingly lapped on the grid electrodes of the transistors M1-Mk and then are connected with a logic control low level VC 1;
k level stabilizing resistors Rb are grounded and correspondingly connected to the body ends of the transistors M1 and Mk respectively.
In order to better implement the present invention, the ANT-RX channel is further provided with two capacitors C1, and two capacitors C1 are respectively disposed at a side of the ANT-RX channel connected to the ANT antenna input port and at a side of the RX port.
In order to better implement the present invention, the TX-ANT channel is further provided with two capacitors C1, and two capacitors C1 are respectively disposed on a side of the TX-ANT channel connected to the ANT antenna input port and a side of the TX port.
Compared with the prior art, the invention has the following advantages and beneficial effects:
(1) the electrostatic discharge channel is connected with the bidirectional diode at two ends of the capacitor in a bridging manner, so that a small parasitic effect is introduced while the chip is subjected to electrostatic protection, and the impedance matching performance and linearity of the channel are improved;
(2) the influence of the electrostatic discharge channel on the impedance matching and the linearity of the channel is solved, and the stability of the chip is improved;
(3) the structure of the invention ensures that the voltage differences born by the transistor source and drain electrodes stacked by the serial branch and the parallel branch are equal and are both lower than the breakdown voltage of the transistor process, thereby improving the stability of the circuit.
Drawings
FIG. 1 is a circuit schematic of the switch architecture of the present invention;
fig. 2 is a circuit diagram of the electrostatic discharge path of the present invention.
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and therefore should not be considered as a limitation to the scope of protection. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Example 1:
the embodiment provides a single-pole double-throw radio frequency switch, as shown in fig. 1 and fig. 2, which is provided with an ANT antenna input port, and a TX-ANT channel, an ANT-RX channel and an electrostatic discharge channel are connected to the ANT antenna input port; the TX-ANT channel and the ANT-RX channel both comprise a series branch knot and a parallel branch knot;
the input port of the ANT antenna is respectively connected with the series branches of the TX-ANT channel and the ANT-RX channel, and then connected with the corresponding parallel branches through the respective connected series branches to lead out the corresponding TX port and RX port;
the series branch of the TX-ANT channel comprises n series transistors, and the parallel branch of the TX-ANT channel comprises m series transistors; the series branch of the ANT-RX channel comprises m series transistors, and the parallel branch of the ANT-RX channel comprises n series transistors; the gates of the transistors in the series branch of the TX-ANT channel and the parallel branch of the ANT-RX channel are connected with a logic control level VC; the grid electrodes of the transistors of the parallel branch of the TX-ANT channel and the series branch of the ANT-RX channel are connected with a logic control level NVC; the amplitude of the logic control level VC is equal to that of the logic control level NVC, and the phase difference is 180 degrees;
the static leakage channels are provided with three groups, the output end of each group of static leakage channels is grounded, the input ends of one group of static leakage channels are lapped on an ANT antenna input port, the input ends of one group of static leakage channels are lapped on a TX port, and the input ends of one group of static leakage channels are lapped on an RX port;
the electrostatic discharge channel comprises a transistor M1-a transistor Mk, wherein k groups of transistors are connected in series through the source and the drain of each transistor; the value of k is equal to the larger of the value m and the value n;
a capacitor C is respectively connected to the source electrode of the transistor M1 and the drain electrode of the transistor Mk in a bridging mode; two diode groups connected in parallel are lapped at two ends of each capacitor C; one diode group comprises a plurality of diodes with the same direction, and the inter-group directions of two groups of diode groups corresponding to one capacitor C are opposite;
the gates of the transistors M1 and Mk are connected with a logic control low level VC 1;
the input end of the capacitor C connected to the source of the transistor M1 is the input end of the electrostatic discharge channel, and the output end of the capacitor C connected to the drain of the transistor Mk is the output end of the electrostatic discharge channel.
The working principle is as follows: fig. 2 shows a schematic diagram of an electrostatic discharge channel at a port, wherein a capacitor C is connected to an input port and an output port of the channel, respectively, and the other end of the capacitor is connected to a core circuit of the electrostatic discharge channel formed by stacking n transistors. Two bidirectional diodes are bridged at two ends of the capacitor C to be used as discharge channels, and two diodes are cascaded in each direction. The core circuit of the electrostatic discharge channel is formed by stacking n MOS transistors, wherein two resistors R1 are connected between the drain and the source of the transistor M1, so as to ensure that the dc levels between the drain and the source of the transistor are equal during normal operation. The source of M2 is connected to the drain of M1, and two resistors R1 are connected between the drain and source of transistor M2, similar to transistor M1. By analogy, the drain electrode of the transistor Mn-1 is connected with the source electrode of the Mn, and two resistors R1 are bridged between the drain electrode and the source electrode of the Mn, so that the voltage difference between the drain electrode and the source electrode of all the transistors in the series branch section is equal, and the problem that the transistors are burnt out due to overlarge voltage difference between the drain electrode and the source electrode of one transistor to cause chip failure during static electricity discharge is avoided. The gates of the transistors M1-Mn are connected with a resistor R2 with a large resistance value, the other end of the resistor R2 is connected with a logic control low level VC1 of the series branch circuit, so that the transistors are in a conducting state, and when the static electricity of the input port is large, the charges are discharged to the ground through the diode.
Example 2:
in this embodiment, on the basis of the above embodiment 1, in order to better implement the present invention, as shown in fig. 1 and fig. 2, the serial branch of the TX-ANT channel is provided with n transistors, i.e., a transistor M11 and a transistor M1n, the n transistors are connected in series through their sources and drains, the source of the transistor M11 is connected to the ANT antenna input port, and the drain of the transistor M1n is connected to the parallel branch of the TX-ANT channel
N +1 transistor constant voltage resistors R1, n transistor stabilizing resistors R2 and n level stabilizing resistors Rb are arranged in the series branch of the TX-ANT channel;
n-1 transistor constant voltage resistors R1 are respectively lapped between the source and the drain of the transistor M11-the transistor M1n, and two transistor constant voltage resistors R1 are respectively lapped on the source of the transistor M11 and the drain of the transistor M1 n; then n +1 transistors of the serial branch of the TX-ANT channel are connected with equal voltage resistors R1 in an overlapping mode;
the n transistor stabilizing resistors R2 are respectively and correspondingly lapped on the grid electrodes of the transistor M11-the transistor M1n and then are connected with a logic control level VC;
the n level stabilizing resistors Rb are grounded and correspondingly connected to the body ends of the transistor M11 and the transistor M1n respectively.
Furthermore, a parallel branch of the TX-ANT channel is provided with a transistor N11-a transistor N1m which are m transistors in total, and the m transistors are connected in series through the source and the drain of each other and then connected in parallel and lapped on the TX-ANT channel through the drain of the transistor N11;
m transistor constant-voltage resistors R1, m transistor stable resistors R2 and m level stable resistors Rb are arranged in parallel branches of the TX-ANT channel;
the m transistor constant voltage resistors R1 are correspondingly lapped on the source and the drain of one transistor of the transistors N11-N1 m respectively;
the m transistor stabilizing resistors R2 are correspondingly lapped on the grid electrode of one transistor from the transistor N11 to the transistor N1m respectively and then are connected with a logic control level NVC;
m of the level stabilizing resistors Rb are grounded and then respectively and correspondingly connected to the body terminal of one of the transistors N11-N1 m.
Furthermore, a fixed resistor R3 is further arranged in the parallel branch of the TX-ANT channel, the fixed resistor R3 is connected with the source of the transistor N1m after being grounded, and the resistance value of the fixed resistor R3 is 50 ohms.
Further, the series branch of the ANT-RX channel is provided with M transistors of M21-M2M, the M transistors are connected in series through the source and the drain of each other, the source of the transistor M21 is connected with the ANT antenna input port, and the drain of the transistor M2M is connected with the parallel branch of the ANT-RX channel
M +1 transistor constant voltage resistors R1, m transistor stabilizing resistors R2 and m level stabilizing resistors Rb are arranged in the series branch of the ANT-RX channel;
m-1 transistor constant voltage resistors R1 are respectively lapped between the source and the drain of the transistor M21-the transistor M2M, and two transistor constant voltage resistors R1 are respectively lapped on the source of the transistor M21 and the drain of the transistor M2M; then m +1 transistors of the serial branch of the ANT-RX channel are connected with equal voltage resistors R1 in an overlapping mode;
the M transistor stabilizing resistors R2 are respectively and correspondingly lapped on the grid electrodes of the transistor M21-the transistor M2M and then are connected with a logic control level VC;
m level stabilizing resistors Rb are grounded and correspondingly connected to the body terminals of the transistor M21-the transistor M2M respectively.
Furthermore, the parallel branch of the ANT-RX channel is provided with N transistors, namely a transistor N21 and a transistor N2N, the N transistors are connected in series through the source and the drain of each other and then connected in parallel and lapped on the ANT-RX channel through the drain of the transistor N21;
n transistor constant voltage resistors R1, n transistor stable resistors R2 and n level stable resistors Rb are arranged in parallel branches of the ANT-RX channel;
the N transistor constant voltage resistors R1 are correspondingly lapped on the source and the drain of one transistor of the transistors N21-N2N respectively;
the N transistor stabilizing resistors R2 are correspondingly lapped on the grid electrode of one transistor from the transistor N21 to the transistor N2N respectively and then are connected with a logic control level NVC;
the N level stabilizing resistors Rb are grounded and respectively connected to the body terminal of one of the transistors N21-N2N.
Furthermore, a fixed resistor R3 is further arranged in the parallel branch of the ANT-RX channel, the fixed resistor R3 is connected with the source of the transistor N2N after being grounded, and the resistance value of the fixed resistor R3 is 50 ohms.
Furthermore, each electrostatic discharge channel is also provided with k +1 transistor constant voltage resistors R1, k transistor stabilizing resistors R2 and k level stabilizing resistors Rb;
k-1 transistor constant voltage resistors R1 are respectively lapped between the source and the drain of the transistor M1-transistor Mk, and two transistor constant voltage resistors R1 are respectively lapped on the source of the transistor M1 and the drain of the transistor Mk;
k transistor stabilization resistors R2 are respectively and correspondingly lapped on the grid electrodes of the transistors M1-Mk and then are connected with a logic control low level VC 1;
k level stabilizing resistors Rb are grounded and correspondingly connected to the body ends of the transistors M1 and Mk respectively.
Further, the ANT-RX channel is further provided with two capacitors C1, and two capacitors C1 are respectively disposed on a side of the ANT-RX channel connected to an ANT antenna input port and a side of an RX port.
Further, the TX-ANT channel is further provided with two capacitors C1, and the two capacitors C1 are respectively disposed on one side of the TX-ANT channel connected to the ANT antenna input port and one side of the TX port.
The working principle is as follows: a transistor constant voltage resistor R1 is lapped between the drain and the source of the transistor to ensure that the direct current level between the drain and the source of the transistor is equal during normal operation;
the transistor stabilizing resistor R2 adopts a resistor with a larger resistance value, the resistance value is about dozens of K omega, 60K omega can be selected, and the access of a large resistance value R2 avoids the breakdown of the gate oxide layer capacitor of the transistor due to higher fluctuation generated by controlling a logic level, and improves the stability of the series branch, the parallel branch and the electrostatic discharge channel.
The level stabilizing resistor Rb is grounded and then connected with the body end of the transistor in an overlapping mode, and the direct-current level of the body end is guaranteed to maintain a certain potential.
The setting of the resistor R3 is fixed to ensure that when the channel is closed, the impedance matching between the port and the external rf circuit is achieved.
Other parts of this embodiment are the same as those of embodiment 1, and thus are not described again.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and all simple modifications and equivalent variations of the above embodiments according to the technical spirit of the present invention are included in the scope of the present invention.
Claims (1)
1. A single-pole double-throw radio frequency switch is characterized in that an ANT antenna input port is arranged, and a TX-ANT channel, an ANT-RX channel and an electrostatic discharge channel are connected through the ANT antenna input port; the TX-ANT channel and the ANT-RX channel both comprise a series branch knot and a parallel branch knot;
the input port of the ANT antenna is respectively connected with the series branches of the TX-ANT channel and the ANT-RX channel, and then connected with the corresponding parallel branches through the respective connected series branches to lead out the corresponding TX port and RX port;
the series branch of the TX-ANT channel comprises n series transistors, and the parallel branch of the TX-ANT channel comprises m series transistors; the series branch of the ANT-RX channel comprises m series transistors, and the parallel branch of the ANT-RX channel comprises n series transistors; the gates of the transistors in the series branch of the TX-ANT channel and the parallel branch of the ANT-RX channel are connected with a logic control level VC; the grid electrodes of the transistors of the parallel branch of the TX-ANT channel and the series branch of the ANT-RX channel are connected with a logic control level NVC; the amplitude of the logic control level VC is equal to that of the logic control level NVC, and the phase difference is 180 degrees;
the static leakage channels are provided with three groups, the output end of each group of static leakage channels is grounded, the input ends of one group of static leakage channels are lapped on an ANT antenna input port, the input ends of one group of static leakage channels are lapped on a TX port, and the input ends of one group of static leakage channels are lapped on an RX port;
the electrostatic discharge channel comprises a transistor M1-a transistor Mk, wherein k groups of transistors are connected in series through the source and the drain of each transistor; the value of k is equal to the larger of the value m and the value n;
a capacitor C is respectively connected to the source electrode of the transistor M1 and the drain electrode of the transistor Mk in a bridging mode; two diode groups connected in parallel are lapped at two ends of each capacitor C; one diode group comprises a plurality of diodes with the same direction, and the inter-group directions of two groups of diode groups corresponding to one capacitor C are opposite;
the gates of the transistors M1 and Mk are connected with a logic control low level VC 1;
the input end of the capacitor C connected to the source of the transistor M1 is the input end of the electrostatic discharge channel, and the output end of the capacitor C connected to the drain of the transistor Mk is the output end of the electrostatic discharge channel;
the series branch of the TX-ANT channel is provided with a transistor M11-a transistor M1n with n transistors, the n transistors are connected in series through the source and the drain of each other, the source of the transistor M11 is connected with the ANT antenna input port, and the drain of the transistor M1n is connected with the parallel branch of the TX-ANT channel
N +1 transistor constant voltage resistors R1, n transistor stabilizing resistors R2 and n level stabilizing resistors Rb are arranged in the series branch of the TX-ANT channel;
n-1 transistor constant voltage resistors R1 are respectively lapped between the source and the drain of the transistor M11-the transistor M1n, and two transistor constant voltage resistors R1 are respectively lapped on the source of the transistor M11 and the drain of the transistor M1 n; then n +1 transistors of the serial branch of the TX-ANT channel are connected with equal voltage resistors R1 in an overlapping mode;
the n transistor stabilizing resistors R2 are respectively and correspondingly lapped on the grid electrodes of the transistor M11-the transistor M1n and then are connected with a logic control level VC;
the n level stabilizing resistors Rb are grounded and correspondingly connected to the body end of the transistor M11-the body end of the transistor M1n respectively;
the parallel branch knot of the TX-ANT channel is provided with m transistors, namely a transistor N11 and a transistor N1m, the m transistors are connected in series through the source electrode and the drain electrode of each transistor, and then are connected in parallel and lapped on the TX-ANT channel through the drain electrode of the transistor N11;
m transistor constant-voltage resistors R1, m transistor stable resistors R2 and m level stable resistors Rb are arranged in parallel branches of the TX-ANT channel;
the m transistor constant voltage resistors R1 are correspondingly lapped on the source and the drain of one transistor of the transistors N11-N1 m respectively;
the m transistor stabilizing resistors R2 are correspondingly lapped on the grid electrode of one transistor from the transistor N11 to the transistor N1m respectively and then are connected with a logic control level NVC;
the m level stabilizing resistors Rb are respectively and correspondingly connected with the body end of one transistor of the transistors N11-N1 m after being grounded;
a fixed resistor R3 is further arranged in a parallel branch of the TX-ANT channel, the fixed resistor R3 is connected with the source electrode of the transistor N1m after being grounded, and the resistance value of the fixed resistor R3 is 50 ohms;
the series branch of the ANT-RX channel is provided with M transistors including a transistor M21 and a transistor M2M, the M transistors are connected in series through the source and the drain of each other, the source of the transistor M21 is connected with the ANT antenna input port, and the drain of the transistor M2M is connected with the parallel branch of the ANT-RX channel
M +1 transistor constant voltage resistors R1, m transistor stabilizing resistors R2 and m level stabilizing resistors Rb are arranged in the series branch of the ANT-RX channel;
m-1 transistor constant voltage resistors R1 are respectively lapped between the source and the drain of the transistor M21-the transistor M2M, and two transistor constant voltage resistors R1 are respectively lapped on the source of the transistor M21 and the drain of the transistor M2M; then m +1 transistors of the serial branch of the ANT-RX channel are connected with equal voltage resistors R1 in an overlapping mode;
the M transistor stabilizing resistors R2 are respectively and correspondingly lapped on the grid electrodes of the transistor M21-the transistor M2M and then are connected with a logic control level VC;
the M level stabilizing resistors Rb are grounded and correspondingly connected to the body ends of the transistor M21 and the transistor M2M respectively;
the parallel branch of the ANT-RX channel is provided with N transistors, namely a transistor N21 and a transistor N2N, the N transistors are connected in series through the source electrode and the drain electrode of each transistor, and then are connected in parallel and lapped on the ANT-RX channel through the drain electrode of the transistor N21;
n transistor constant voltage resistors R1, n transistor stable resistors R2 and n level stable resistors Rb are arranged in parallel branches of the ANT-RX channel;
the N transistor constant voltage resistors R1 are correspondingly lapped on the source and the drain of one transistor of the transistors N21-N2N respectively;
the N transistor stabilizing resistors R2 are correspondingly lapped on the grid electrode of one transistor from the transistor N21 to the transistor N2N respectively and then are connected with a logic control level NVC;
the N level stabilizing resistors Rb are respectively and correspondingly connected with the body end of one transistor of the transistors N21-N2N after being grounded;
a fixed resistor R3 is further arranged in a parallel branch of the ANT-RX channel, the fixed resistor R3 is connected with the source electrode of the transistor N2N after being grounded, and the resistance value of the fixed resistor R3 is 50 ohms;
each static leakage channel is also provided with k +1 transistor constant-voltage resistors R1, k transistor stabilizing resistors R2 and k level stabilizing resistors Rb;
k-1 transistor constant voltage resistors R1 are respectively lapped between the source and the drain of the transistor M1-transistor Mk, and two transistor constant voltage resistors R1 are respectively lapped on the source of the transistor M1 and the drain of the transistor Mk;
k transistor stabilization resistors R2 are respectively and correspondingly lapped on the grid electrodes of the transistors M1-Mk and then are connected with a logic control low level VC 1;
k level stabilizing resistors Rb are grounded and then correspondingly connected to the body end of the transistor M1-the body end of the transistor Mk respectively;
the ANT-RX channel is further provided with two capacitors C1, and two capacitors C1 are respectively arranged on one side of the ANT-RX channel, which is connected with an ANT antenna input port, and one side of an RX port;
the TX-ANT channel is further provided with two capacitors C1, and the two capacitors C1 are respectively arranged on one side of the TX-ANT channel, which is connected with an ANT antenna input port, and one side of the TX port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111156263.8A CN113595542B (en) | 2021-09-30 | 2021-09-30 | Single-pole double-throw radio frequency switch |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111156263.8A CN113595542B (en) | 2021-09-30 | 2021-09-30 | Single-pole double-throw radio frequency switch |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113595542A CN113595542A (en) | 2021-11-02 |
| CN113595542B true CN113595542B (en) | 2022-01-04 |
Family
ID=78242531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111156263.8A Active CN113595542B (en) | 2021-09-30 | 2021-09-30 | Single-pole double-throw radio frequency switch |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113595542B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116073768A (en) * | 2023-03-20 | 2023-05-05 | 成都明夷电子科技有限公司 | Electrostatic protection circuit of radio frequency low noise amplifier chip and radio frequency amplifying circuit |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201230205Y (en) * | 2008-07-14 | 2009-04-29 | 武汉光迅科技股份有限公司 | Electrostatic protection circuit for radio frequency circuit port |
| US8970278B2 (en) * | 2010-04-27 | 2015-03-03 | Rf Micro Devices, Inc. | High power FET switch |
| KR20140067478A (en) * | 2012-11-26 | 2014-06-05 | 삼성전기주식회사 | Radio frequency input circuit with esd protection function |
| JP6256320B2 (en) * | 2014-11-28 | 2018-01-10 | 三菱電機株式会社 | ESD protection circuit and RF switch |
| US9742400B2 (en) * | 2015-05-06 | 2017-08-22 | Infineon Technologies Ag | System and method for driving radio frequency switch |
| US10211830B2 (en) * | 2017-04-28 | 2019-02-19 | Qualcomm Incorporated | Shunt termination path |
| KR102348686B1 (en) * | 2017-08-04 | 2022-01-06 | 삼성전기주식회사 | Radio frequency switch apparatus with integrated shunt and bias |
| US10666313B2 (en) * | 2017-11-07 | 2020-05-26 | Qorvo Us, Inc. | Radio frequency switch branch circuitry |
| US10389400B2 (en) * | 2017-11-07 | 2019-08-20 | Qorvo Us, Inc. | Radio frequency switch circuitry |
| TWI647909B (en) * | 2018-01-19 | 2019-01-11 | 立積電子股份有限公司 | Switching device |
| CN110611499B (en) * | 2018-06-15 | 2024-01-12 | 锐迪科微电子（上海）有限公司 | ESD protection circuit of radio frequency switch based on D-pHEMT device |
| KR102583788B1 (en) * | 2018-07-09 | 2023-09-26 | 삼성전기주식회사 | Radio frequency switch device of leakage current reduction type |
| CN109104173B (en) * | 2018-07-20 | 2022-05-10 | 上海华虹宏力半导体制造有限公司 | Radio frequency switch ESD system |
| CN112542453A (en) * | 2020-12-11 | 2021-03-23 | 康希通信科技（上海）有限公司 | Radio frequency chip and ESD protection circuit design method thereof |
-
2021
- 2021-09-30 CN CN202111156263.8A patent/CN113595542B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN113595542A (en) | 2021-11-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10505537B2 (en) | Radio frequency antenna switch | |
| US7391282B2 (en) | Radio-frequency switch circuit and semiconductor device | |
| CN105049015B (en) | The single-pole double throw RF switch and hilted broadsword of single-pole single-throw(SPST RF switch and its composition throw RF switch more | |
| CN109088626B (en) | Ultralow-power-consumption biased radio frequency switch | |
| KR20150114910A (en) | System and method for driving a radio frequency switch | |
| US20060119451A1 (en) | Switching circuits | |
| JPH11136111A (en) | High frequency circuit | |
| JP5997624B2 (en) | High frequency semiconductor switch and radio equipment | |
| CN108736866B (en) | CMOS SOI radio frequency switch circuit | |
| WO2018058147A1 (en) | Main-auxiliary field-effect transistor configurations for radio frequency applications | |
| CN113595542B (en) | Single-pole double-throw radio frequency switch | |
| US10749501B2 (en) | High power silicon on insulator switch | |
| CN115189682A (en) | Radio frequency switch circuit | |
| JP5492672B2 (en) | Design method of high-frequency switch circuit | |
| CN111342829B (en) | Broadband radio frequency switch and switching method thereof, switch module and circuit module | |
| CN216599573U (en) | Radio frequency switch subunit and radio frequency switch | |
| CN113544974B (en) | Radio frequency switch circuit, chip and communication terminal | |
| CN115333503A (en) | Digital attenuator | |
| CN114039584A (en) | High-voltage-resistant SOI CMOS radio frequency switch | |
| CN213783269U (en) | Radio frequency switch circuit and radio frequency front end module | |
| EP3930203A1 (en) | Switch device, system and corresponding methods | |
| CN217985025U (en) | Radio frequency switch circuit | |
| CN219145388U (en) | Radio frequency access, radio frequency switch and electronic equipment | |
| US20230353140A1 (en) | Biasing body node of a transistor | |
| CN212935887U (en) | Antenna tuning switch with parallel branch having high voltage-resistant capability |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CB03 | Change of inventor or designer information | ||
| CB03 | Change of inventor or designer information |
Inventor after: Yuan Xiaofang Inventor after: Liu Chengpeng Inventor after: Yao Jingshi Inventor before: Yuan Xiaofang Inventor before: Liu Chengpeng Inventor before: Yao Jingshi |
|
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: Floor 9, block a, Xiewei center, No. 333 Dehua Road, hi tech Zone, Chengdu, Sichuan 610000 Patentee after: Chengdu Mingyi Electronic Technology Co.,Ltd. Country or region after: China Address before: Floor 9, block a, Xiewei center, No. 333 Dehua Road, hi tech Zone, Chengdu, Sichuan 610000 Patentee before: Chengdu Mingyi Electronic Technology Co.,Ltd. Country or region before: China |