CN113871462A - GaN vertical Schottky diode and manufacturing method thereof - Google Patents

GaN vertical Schottky diode and manufacturing method thereof Download PDF

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CN113871462A
CN113871462A CN202111014875.3A CN202111014875A CN113871462A CN 113871462 A CN113871462 A CN 113871462A CN 202111014875 A CN202111014875 A CN 202111014875A CN 113871462 A CN113871462 A CN 113871462A
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gan
layer
substrate
epitaxial layer
metal layer
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谭永亮
廖龙忠
杨志虎
刘亚亮
高昶
崔玉兴
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CETC 13 Research Institute
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204—Diodes
    • H01L29/66212—Schottky diodes

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Abstract

The invention provides a GaN vertical Schottky diode and a manufacturing method thereof, belonging to the technical field of semiconductors. According to the hetero-epitaxial GaN vertical Schottky diode and the manufacturing method thereof, the GaN vertical diode with the same structure as the Si diode can be obtained, the chip integration level is high, the current density is high, and the subsequent chip assembly is facilitated.

Description

GaN vertical Schottky diode and manufacturing method thereof
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a GaN vertical Schottky diode and a manufacturing method thereof.
Background
The wide-bandgap semiconductor GaN has the advantages of large bandgap width, high thermal conductivity, high breakdown field strength, high electron saturation drift velocity and the like, and has wide market application prospect in the field of power device manufacturing. The diode made of the GaN material can transmit larger current and bear higher voltage compared with the traditional Si diode under the same chip area. However, because the single crystal substrate material of GaN is still in the research and development stage, the defects of small single crystal size, high defect density and the like exist at present, and the development of devices related to GaN homoepitaxy is severely restricted, for example, the GaN schottky diode and the P-i-N diode manufactured by the GaN homoepitaxy used have low yield and low wafer processing capacity, so that the chips cannot be produced in batches. At present, the international GaN heteroepitaxy technology is developed rapidly, and GaN materials with excellent performance can be epitaxially grown on large-size SiC, Si or sapphire. There have been international reports of using GaN heteroepitaxial materials to fabricate semi-vertical diodes where the anode and cathode of the diode are on the same side of the wafer. This type of device has two major problems: firstly, the electrodes are concentrated on the same surface of the wafer, the area of the chip is increased, and the current density of the chip is small; and secondly, in the subsequent assembly and use, the anode and the cathode need to be led out by adopting a routing mode simultaneously, so that the use difficulty and the use cost are increased, and therefore, the semi-vertical diode is not widely applied to actual industrial products.
Disclosure of Invention
The invention aims to provide a GaN vertical Schottky diode and a manufacturing method thereof, and aims to solve the technical problem that a vertical device cannot be manufactured by using a hetero-epitaxial GaN material.
In order to achieve the purpose, the invention adopts the technical scheme that: the GaN vertical Schottky diode comprises a substrate, a GaN buffer layer, an anode metal layer, a deposited metal layer and a cathode metal layer, wherein the GaN buffer layer is formed on the substrate, an N + GaN epitaxial layer and an N-GaN epitaxial layer are sequentially formed on the upper surface of the GaN buffer layer, openings which are communicated with each other are formed in the middle of the substrate and the GaN buffer layer, one end of each opening is communicated with the outside of the substrate, and the other end of each opening is exposed out of the N + GaN epitaxial layer; an anode metal layer is formed on the upper surface of the N-GaN epitaxial layer; a deposited metal layer is formed in the opening and is arranged on the N + GaN epitaxial layer; a cathode metal layer is formed on the substrate and the deposited metal layer and on the inner side of the GaN buffer layer.
In one possible implementation manner, a passivation medium is formed on the N-GaN epitaxial layer and the anode metal layer.
The GaN vertical Schottky diode provided by the invention has the beneficial effects that: compared with the prior art, the GaN vertical Schottky diode has the advantages that the anode and the cathode are formed on different surfaces, the area of a chip is reduced, the current density of the chip is high, the technical problem that a vertical device cannot be manufactured by a heteroepitaxial GaN material is solved, the GaN vertical diode with the same structure as a Si diode can be obtained by the manufacturing method, the integration level of the chip is high, the current density is high, and the subsequent chip assembly is facilitated.
The invention also provides a manufacturing method of the GaN vertical Schottky diode, which comprises the following steps:
forming a GaN buffer layer on a substrate, sequentially forming an N + GaN epitaxial layer and an N-GaN epitaxial layer on the upper surface of the GaN buffer layer, forming mutually communicated openings in the middle of the substrate and the GaN buffer layer, wherein one end of each opening is communicated with the outside of the substrate, and the other end of each opening is exposed out of the N + GaN epitaxial layer;
forming an anode metal layer on the upper surface of the N-GaN epitaxial layer;
forming a deposited metal layer in the opening, wherein the deposited metal layer is also arranged on the N + GaN epitaxial layer;
and forming a cathode metal layer on the substrate and the deposition metal layer and on the inner side surface of the GaN buffer layer.
In one possible implementation, forming a GaN buffer layer on a substrate includes:
performing GaN heteroepitaxy on the substrate, and sequentially forming an N + GaN epitaxial layer and an N-GaN epitaxial layer on the upper surface of the GaN buffer layer;
the thickness of the GaN buffer layer is 0.01-5 mu m, the thickness of the N + GaN epitaxial layer is 0.1-5 mu m, and the thickness of the N-GaN epitaxial layer is 1-100 mu m.
In a possible implementation manner, the substrate and the GaN buffer layer are formed with openings in the middle thereof, the openings are communicated with each other, one end of each opening is communicated with the outside of the substrate, and the other end of each opening is exposed out of the N + GaN epitaxial layer, including:
and removing the substrate and the GaN buffer layer positioned in the middle, and exposing the N + GaN epitaxial layer to ensure that the thickness of the residual substrate is 10-200 mu m.
In one possible implementation, forming an anode metal layer on the upper surface of the N-GaN epitaxial layer includes:
manufacturing an anode electrode on the upper surface of the N-GaN epitaxial layer, and forming an anode metal layer on the upper surface of the N-GaN epitaxial layer;
the anode metal of the anode electrode is one of Ti/Au, Ni/Au or Ti/Al;
the thickness of the anode metal layer is 1-10 μm.
In one possible implementation manner, forming a deposited metal layer within the opening, the deposited metal layer being further disposed on the N + GaN epitaxial layer, includes:
forming an ohmic contact metal system by the deposited metal layer and the N + GaN epitaxial layer, and then scanning, irradiating and annealing the deposited metal layer by using pulse laser;
the metal of the deposited metal layer is one of Ti/Al, Ti/Al/Ni/Au, Ti/Al/Ti/Au or Ti/Al/Pt/Au.
In one possible implementation, the substrate material is one of SiC, Si, or sapphire.
In a possible implementation manner, after the anode metal layer is manufactured, a passivation medium is used for performing passivation protection on the anode electrode, and the thickness of the passivation medium is 0.1-10 μm.
In one possible implementation, the energy density of the pulse laser is 1J/cm2～5J/cm2。
The manufacturing method of the GaN vertical Schottky diode has the beneficial effects that: compared with the prior art, the manufacturing method of the GaN vertical Schottky diode comprises the steps of forming a GaN buffer layer on a substrate, sequentially forming an N + GaN epitaxial layer and an N-GaN epitaxial layer on the upper surface of the GaN buffer layer, forming mutually communicated openings in the middle of the substrate and the GaN buffer layer, wherein one end of each opening is communicated with the outside of the substrate, and the other end of each opening is exposed out of the N + GaN epitaxial layer; forming an anode metal layer on the upper surface of the N-GaN epitaxial layer; forming a deposited metal layer in the opening, wherein the deposited metal layer is also arranged on the N + GaN epitaxial layer; the method has the advantages that the cathode metal layers are formed on the substrate and the deposition metal layer and on the inner side face of the GaN buffer layer, the technical problem that a vertical device cannot be manufactured by a heteroepitaxial GaN material is solved, the GaN vertical diode with the same structure as the Si diode can be obtained by the manufacturing method, the anode and the cathode are on different faces, the area of a chip is reduced, the chip integration level is high, the current density is high, and subsequent chip assembly is facilitated.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an epitaxial GaN material of a method for manufacturing a GaN vertical schottky diode according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an anode electrode of a GaN schottky diode according to a method for manufacturing a GaN vertical schottky diode according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a GaN schottky diode backside opening according to a method for manufacturing a GaN vertical schottky diode according to an embodiment of the present invention (after removing the substrate and the GaN buffer layer);
fig. 4 is a schematic diagram illustrating a back ohmic contact formation of a GaN schottky diode according to a method for forming a GaN vertical schottky diode according to an embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a back cathode electrode of a GaN schottky diode according to a method for fabricating a GaN vertical schottky diode according to an embodiment of the present invention.
Description of reference numerals:
1. a substrate; 2. a GaN buffer layer; 3. an N + GaN epitaxial layer; 4. an N-GaN epitaxial layer; 5. an anode metal layer; 6. passivating the medium; 7. depositing a metal layer; 8. and a cathode metal layer.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1 to 5, a GaN vertical schottky diode and a method for fabricating the same according to the present invention will now be described.
Referring to fig. 5, the GaN vertical schottky diode includes a substrate 1, a GaN buffer layer 2, an anode metal layer 5, a deposition metal layer 7 and a cathode metal layer 8, wherein the GaN buffer layer 2 is formed on the substrate 1, an N + GaN epitaxial layer 3 and an N-GaN epitaxial layer 4 are sequentially formed on the upper surface of the GaN buffer layer 2, openings communicated with each other are formed in the middle of the substrate 1 and the GaN buffer layer 2, one end of each opening is communicated with the outside of the substrate 1, and the other end of each opening exposes the N + GaN epitaxial layer 3; the anode metal layer 5 is formed on the upper surface of the N-GaN epitaxial layer 4; the deposited metal layer 7 is formed in the opening and is arranged on the N + GaN epitaxial layer 3; a cathode metal layer 8 is formed on the substrate 1 and the deposited metal layer 7 and on the inner side of the GaN buffer layer 2.
The GaN vertical Schottky diode provided by the invention has the beneficial effects that: compared with the prior art, the GaN vertical Schottky diode has the advantages that the anode and the cathode are formed on different surfaces, the area of a chip is reduced, the current density of the chip is high, the technical problem that a vertical device cannot be manufactured by a heteroepitaxial GaN material is solved, the GaN vertical diode with the same structure as a Si diode can be obtained by the manufacturing method, the integration level of the chip is high, the current density is high, and the subsequent chip assembly is facilitated.
In some embodiments, referring to fig. 5, a passivation dielectric 6 is formed on both the N-GaN epitaxial layer 4 and the anode metal layer 5.
And passivating and protecting the anode electrode by using a passivating medium 6, wherein the thickness of the passivating medium 6 is 0.1-10 mu m.
The passivation mediums 6 used for passivation protection are arranged on the anode metal layer 5, the N-GaN epitaxial layer 4 and the region between the anode metal layer 5 and the N-GaN epitaxial layer 4, namely, the shape of the passivation mediums 6 is Z-shaped when viewed in appearance, so that the passivation protection of the N-GaN epitaxial layer 4 of the anode metal layer 5 is realized.
Specifically, in the present embodiment, the name and type of the passivation medium 6 used are not limited as long as passivation protection can be provided.
Referring to fig. 1 to 5, the present invention further provides a method for manufacturing a GaN vertical schottky diode, including:
forming a GaN buffer layer 2 on a substrate 1, sequentially forming an N + GaN epitaxial layer 3 and an N-GaN epitaxial layer 4 on the upper surface of the GaN buffer layer 2, forming mutually communicated openings in the middle of the substrate 1 and the GaN buffer layer 2, wherein one end of each opening is communicated with the outside of the substrate 1, and the other end of each opening is exposed out of the N + GaN epitaxial layer 3;
forming an anode metal layer 5 on the upper surface of the N-GaN epitaxial layer 4;
forming a deposited metal layer 7 in the opening, wherein the deposited metal layer 7 is also arranged on the N + GaN epitaxial layer 3;
and forming a cathode metal layer 8 on the substrate 1 and the deposited metal layer 7 and on the inner side surface of the GaN buffer layer 2 to complete the manufacture of the GaN vertical Schottky diode.
The manufacturing method of the GaN vertical Schottky diode has the beneficial effects that: compared with the prior art, the manufacturing method of the GaN vertical Schottky diode comprises the steps of forming a GaN buffer layer 2 on a substrate 1, sequentially forming an N + GaN epitaxial layer 3 and an N-GaN epitaxial layer 4 on the upper surface of the GaN buffer layer 2, forming mutually communicated openings in the middle of the substrate 1 and the GaN buffer layer 2, wherein one end of each opening is communicated with the outside of the substrate 1, and the other end of each opening is exposed out of the N + GaN epitaxial layer 3; forming an anode metal layer 5 on the upper surface of the N-GaN epitaxial layer 4; forming a deposited metal layer 7 in the opening, wherein the deposited metal layer 7 is also arranged on the N + GaN epitaxial layer 3; the cathode metal layer 8 is formed on the substrate 1, the deposition metal layer 5 and the inner side surface of the GaN buffer layer 2, the technical problem that a vertical device cannot be manufactured by a heteroepitaxial GaN material is solved, the GaN vertical diode with the same structure as the Si diode can be obtained by the manufacturing method, the anode and the cathode are on different surfaces, the area of a chip is reduced, the chip integration level is high, the current density is high, and subsequent chip assembly is facilitated.
After the cathode metal layer 8 is manufactured, the cathode metal layer 8 is in a convex shape in appearance, the substrate 1 with the hole and the GaN buffer layer 2 are filled, and the substrate and the GaN buffer layer are integrally combined with a wafer to form an integral structure, so that the GaN vertical Schottky diode is manufactured. The name of the metal material of the cathode metal layer 8 is not limited in the present embodiment.
In some embodiments, referring to fig. 1 to 5, forming a GaN buffer layer 2 on a substrate 1 includes:
performing GaN heteroepitaxy on the substrate 1, and sequentially forming an N + GaN epitaxial layer 3 and an N-GaN epitaxial layer 4 on the upper surface of the GaN buffer layer 2;
the thickness of the GaN buffer layer 2 is 0.01-5 μm, the thickness of the N + GaN epitaxial layer 3 is 0.1-5 μm, and the thickness of the N-GaN epitaxial layer 4 is 1-100 μm.
The substrate 1, the GaN buffer layer 2, the N + GaN epitaxial layer 3 and the N-GaN epitaxial layer 4 jointly form a wafer, the anode and the cathode are respectively formed on different surfaces of the wafer, the anode is arranged on the N-GaN epitaxial layer 4, and the cathode is arranged on the substrate 1, the GaN buffer layer 2 and the deposited metal layer 7.
The specific epitaxial method for GaN heteroepitaxy on the substrate 1 described above can be implemented using conventional techniques.
In some embodiments, referring to fig. 1 to 5, the substrate 1 and the GaN buffer layer 2 are formed with an opening in the middle, one end of the opening is connected to the outside of the substrate 1, and the other end of the opening exposes the N + GaN epitaxial layer 3, including:
and removing the substrate 1 and the GaN buffer layer 2 positioned in the middle, and exposing the N + GaN epitaxial layer 3 to ensure that the thickness of the residual substrate 1 is 10-200 mu m.
In this embodiment, the depth of the opening is the sum of the thickness of the substrate 1 and the thickness of the GaN buffer layer 2, and the opening is preferably a straight hole in appearance. The opening is made in the middle of the substrate 1 and the GaN buffer layer 2, not in the side or off-center position.
In some embodiments, referring to fig. 1 to 5, an anode metal layer 5 is formed on the upper surface of the N-GaN epitaxial layer 4, and includes:
manufacturing an anode electrode on the upper surface of the N-GaN epitaxial layer 4, and forming an anode metal layer 5 on the upper surface of the N-GaN epitaxial layer;
the anode metal of the anode electrode is one of Ti/Au, Ni/Au or Ti/Al;
the thickness of the anode metal layer 5 is 1 μm to 10 μm.
The thickness of the anode metal layer 5 is slightly smaller than that of the N-GaN epitaxial layer 4 and larger than that of the N + GaN epitaxial layer 3, the length or the width of the anode metal layer 5 is smaller than that of the N-GaN epitaxial layer 4, namely, the anode metal layer 5 and the N-GaN epitaxial layer 4 form a structure similar to a convex shape in appearance, and the anode metal layer 5 is located in the middle of the upper end of the N-GaN epitaxial layer 4.
In some embodiments, referring to fig. 1 to 5, a deposited metal layer 7 is formed within the opening, the deposited metal layer 7 is further disposed on the N + GaN epitaxial layer 3, and the method includes:
forming an ohmic contact metal system by the deposited metal layer 7 and the N + GaN epitaxial layer 3, and then scanning, irradiating and annealing the deposited metal layer 7 by using pulse laser; the pulsed laser method used at this time corresponds to a pulsed laser.
The metal deposited on the metal layer 7 is one of Ti/Al, Ti/Al/Ni/Au, Ti/Al/Ti/Au or Ti/Al/Pt/Au. The thickness of the deposited metal layer is generally less than the thickness of the N + GaN epitaxial layer 3.
In some embodiments, referring to fig. 1 to 5, the material of the substrate 1 is one of SiC, Si or sapphire.
The substrate 1 is generally a plate-like member having a thickness greater than that of the GaN buffer layer 2, the N + GaN epitaxial layer 3 having a thickness greater than that of the GaN buffer layer 2 and less than that of the substrate 1, and the N-GaN epitaxial layer 4 having a thickness greater than that of the N + GaN epitaxial layer 3 and less than that of the substrate 1.
In some embodiments, referring to fig. 1 to 5, after the anode metal layer 5 is manufactured, the passivation medium 6 is used to perform passivation protection on the anode electrode, and the thickness of the passivation medium is 0.1 μm to 10 μm.
The passivation mediums 6 used for passivation protection are arranged on the anode metal layer 5, the N-GaN epitaxial layer 4 and the region between the anode metal layer 5 and the N-GaN epitaxial layer 4, namely, the shape of the passivation mediums 6 is Z-shaped when viewed in appearance, so that the passivation protection of the N-GaN epitaxial layer 4 of the anode metal layer 5 is realized.
Specifically, in the present embodiment, the name and type of the passivation medium 6 used are not limited as long as passivation protection can be provided.
In some embodiments, referring to FIGS. 1-5, the pulsed laser is used at a fluence of 1J/cm2～5J/cm2。
In the present embodiment, the methods of depositing the anode metal layer, the cathode metal layer and the deposited metal layer can all be performed by the prior art, and the method of annealing the deposited metal layer 7 by the pulsed laser scanning can all be performed by the prior art.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (10)

1. A GaN vertical schottky diode comprising:
a substrate;
the GaN buffer layer is formed on the substrate, an N + GaN epitaxial layer and an N-GaN epitaxial layer are sequentially formed on the upper surface of the GaN buffer layer, communicated openings are formed in the middle of the substrate and the middle of the GaN buffer layer, one end of each opening is communicated with the outside of the substrate, and the other end of each opening is exposed out of the N + GaN epitaxial layer;
the anode metal layer is formed on the upper surface of the N-GaN epitaxial layer;
depositing a metal layer which is formed in the opening and is arranged on the N + GaN epitaxial layer;
and the cathode metal layer is formed on the substrate, the deposition metal layer and the inner side face of the GaN buffer layer.
2. The GaN vertical schottky diode of claim 1 wherein a passivation dielectric is formed on both the N-GaN epitaxial layer and the anode metal layer.
3. A method for manufacturing a GaN vertical Schottky diode is characterized by comprising the following steps:
forming a GaN buffer layer on a substrate, sequentially forming an N + GaN epitaxial layer and an N-GaN epitaxial layer on the upper surface of the GaN buffer layer, forming mutually communicated openings in the middle of the substrate and the GaN buffer layer, wherein one end of each opening is communicated with the outside of the substrate, and the other end of each opening is exposed out of the N + GaN epitaxial layer;
forming an anode metal layer on the upper surface of the N-GaN epitaxial layer;
forming a deposited metal layer in the opening, wherein the deposited metal layer is also arranged on the N + GaN epitaxial layer;
and forming a cathode metal layer on the substrate and the deposition metal layer and on the inner side surface of the GaN buffer layer.
4. The method of claim 3, wherein forming a GaN buffer layer on a substrate comprises:
performing GaN heteroepitaxy on the substrate, and sequentially forming an N + GaN epitaxial layer and an N-GaN epitaxial layer on the upper surface of the GaN buffer layer;
the thickness of the GaN buffer layer is 0.01-5 mu m, the thickness of the N + GaN epitaxial layer is 0.1-5 mu m, and the thickness of the N-GaN epitaxial layer is 1-100 mu m.
5. The method of claim 3, wherein the substrate and the GaN buffer layer have openings formed therein that are in communication with each other, one end of the openings being in communication with the outside of the substrate and the other end of the openings exposing the N + GaN epitaxial layer, the method comprising:
and removing the substrate and the GaN buffer layer positioned in the middle, and exposing the N + GaN epitaxial layer to ensure that the thickness of the residual substrate is 10-200 mu m.
6. The method of claim 3, wherein forming an anode metal layer on the top surface of the N-GaN epitaxial layer comprises:
manufacturing an anode electrode on the upper surface of the N-GaN epitaxial layer, and forming an anode metal layer on the upper surface of the N-GaN epitaxial layer;
the anode metal of the anode electrode is one of Ti/Au, Ni/Au or Ti/Al;
the thickness of the anode metal layer is 1-10 μm.
7. The method of claim 3, wherein forming a deposited metal layer within said opening, said deposited metal layer further disposed on said N + GaN epitaxial layer, comprises:
forming an ohmic contact metal system by the deposited metal layer and the N + GaN epitaxial layer, and then scanning, irradiating and annealing the deposited metal layer by using pulse laser;
the metal of the deposited metal layer is one of Ti/Al, Ti/Al/Ni/Au, Ti/Al/Ti/Au or Ti/Al/Pt/Au.
8. The method of claim 3, wherein the substrate material is one of SiC, Si, or sapphire.
9. The method of claim 3, wherein the anode electrode is passivated and protected by a passivation medium after the anode metal layer is fabricated, and the thickness of the passivation medium is 0.1 μm to 10 μm.
10. The method of claim 7, wherein the pulsed laser has an energy density of 1J/cm2～5J/cm2。
CN202111014875.3A 2021-08-31 2021-08-31 GaN vertical Schottky diode and manufacturing method thereof Pending CN113871462A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102054875A (en) * 2010-10-29 2011-05-11 中山大学 Power type GaN base Schottky diode and manufacture method thereof
CN103346083A (en) * 2013-07-09 2013-10-09 苏州捷芯威半导体有限公司 Gallium nitride schottky diode and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102054875A (en) * 2010-10-29 2011-05-11 中山大学 Power type GaN base Schottky diode and manufacture method thereof
CN103346083A (en) * 2013-07-09 2013-10-09 苏州捷芯威半导体有限公司 Gallium nitride schottky diode and manufacturing method thereof

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