CN113871315A - Tube core failure analysis method and stacked packaging chip failure analysis method - Google Patents
Tube core failure analysis method and stacked packaging chip failure analysis method Download PDFInfo
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- CN113871315A CN113871315A CN202111078535.7A CN202111078535A CN113871315A CN 113871315 A CN113871315 A CN 113871315A CN 202111078535 A CN202111078535 A CN 202111078535A CN 113871315 A CN113871315 A CN 113871315A
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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Abstract
The invention discloses a method for analyzing the failure of a tube core and a method for analyzing the failure of a stacked packaging chip, wherein the tube core comprises a substrate and a device layer positioned on the substrate, and the method for analyzing the failure comprises the following steps: carrying out hot spot positioning on the defects in the tube core from the back surface of the tube core, namely the surface where the substrate is positioned; removing the substrate from the backside of the die to expose the target circuit; and making electrical measurements on the backside of the die to obtain information of the defects. The stacked package chip comprises a lead frame, a plurality of dies stacked on the lead frame and an encapsulating material covering the lead frame and the dies, and the failure analysis method comprises the following steps: performing electrical measurements on the stacked packaged chips to determine a failed die; if a fault tube core which is not subjected to failure analysis exists, the failure analysis step is repeatedly executed; the failure analysis step comprises: removing a portion of the lead frame, encapsulant and/or die until a substrate of a first failed die not subjected to failure analysis is exposed; and performing failure analysis on the failed tube core by adopting a tube core failure analysis method.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for analyzing the failure of a tube core and a method for analyzing the failure of a stacked packaging chip.
Background
The 3D NAND memory is, for example, a stack package chip in which a plurality of dies (die) are stacked and bonded together to form a multilayer structure to provide a larger storage capacity. With the market demand for storage capacity of a single memory chip increasing, as many as 16 layers, or even more, of die are stacked in stacked package chips. The stacked packaging chip can increase storage density and has better performance in the aspects of service life, performance, stability and the like.
However, failure analysis of the stacked packaged chips becomes difficult. When failure analysis is performed on a single die, hot spot positioning is usually performed from the back side of the die, i.e., the side on which the substrate is located. With the improvement of the chip integration level, one hot spot on the imaging comprises hundreds of transistors or more, and the failure point is difficult to be accurately positioned by simply carrying out hot spot positioning from the back surface of the die, so that in the prior art, after the hot spot positioning is carried out from the back surface of the die, the layer is removed from the front surface of the die to a target position to further position the failure point. Therefore, when failure analysis is performed on the stacked packaged chip, the substrate ground from the back side where the lead frame of the stacked packaged chip is located to the faulty die is exposed, the device layer ground from the front side of the stacked packaged chip to the faulty die is exposed, and then the failure analysis is performed according to the single-die failure analysis method.
In the failure analysis method in the prior art, when a single tube core is subjected to failure analysis, the time consumption for removing layers on the front surface is long, and devices and circuit structures in a device layer are easily damaged, so that the failure analysis effect is not ideal. When failure analysis is performed on a stacked packaged chip, in order to obtain a failed die, other dies except the failed die need to be removed, if two or more dies in the stacked packaged chip fail at the same time, only one of the dies can be reserved as the failed die, and the other die can be removed, which inevitably causes related defect information to be lost, and is not beneficial to finding and correcting defects in design and production.
Disclosure of Invention
In view of the foregoing problems, an object of the present invention is to provide a method for analyzing a failure of a die and a method for analyzing a failure of a stacked package chip, in which a target region including a failure point is preliminarily determined by hot spot positioning, and then the target region is thinned to further accurately position the failure point, so that the failure point can be accurately analyzed from the back side of a failed die, and thus when a plurality of failed dies exist in the stacked package chip, the failure analysis can be performed on the failed dies one by one, and more accurate defect information can be obtained.
According to an aspect of the present invention, there is provided a method for analyzing a failure of a die, the die including a substrate and a device layer on the substrate, the method comprising: carrying out hot spot positioning on the defects in the tube core from the back surface of the tube core, namely the surface where the substrate is positioned; removing the substrate from the backside of the die to expose a target line; and making electrical measurements on the backside of the die to obtain information of the defects.
Optionally, after the step of performing hot spot positioning on the defect in the die from the back side of the die, the method further includes: and forming a marking point on the surface of the substrate by using laser according to the hot spot positioning so as to determine a first target area.
Optionally, the hot spot locating the defect in the die from the back side of the die comprises: hot spot locating defects in the die from the backside of the die using either one of micro-light microscopy, light induced resistance change, or a combination thereof.
Optionally, the removing the substrate from the backside of the die to expose the target line comprises: cutting the substrate material on the first target area by adopting either a focused ion beam or a plasma focused ion beam, and reducing the substrate thickness of the first target area to a preset value; determining a second target area including the target line according to the layout, and removing substrate material of the second target area by adopting either the focused ion beam or the plasma focused ion beam to form an opening exposing the target line; wherein the second target region is located in the first target region.
Optionally, the performing electrical measurements on the backside of the die to obtain information of the defect comprises: and electrically connecting a probe with the target circuit, and acquiring the information of the defect by adopting electrically induced resistance change.
Optionally, the obtaining information of the defect by using the electrically induced resistance change comprises: and positioning a failure point by adopting electric induction resistance change, and preparing the failure point into a sample by adopting any one of a focused ion beam or a plasma focused ion beam and carrying out failure analysis to obtain the information of the defect.
Optionally, the preset value is 2 microns.
Optionally, the first target area is a square with a side of 150 microns.
According to another aspect of the present invention, there is provided a method of analyzing a failure of a stacked package chip including a lead frame, a plurality of dies stacked on the lead frame, and an encapsulant covering the lead frame and the plurality of dies, the method including: performing electrical measurements on the stacked packaged chips to determine a failed die; if a fault tube core which is not subjected to failure analysis exists in the stacked packaged chips, the failure analysis step is repeatedly executed; wherein the failure analysis step comprises: removing the lead frame, a portion of the encapsulant, and/or the die until a substrate of a first failed die that has not been subjected to failure analysis is exposed; and performing failure analysis on the failed die by using the failure analysis method.
Optionally, the removing the leadframe, a portion of the encapsulant, and/or the die comprises: a grinding process is used to remove the leadframe, a portion of the encapsulant, and/or the die.
According to the failure analysis method of the failed tube core, disclosed by the embodiment of the invention, the failure analysis is carried out on the failed tube core from the back side of the substrate, so that the structures of lines, devices and the like in the device layer can be well reserved, and the condition that the failure analysis effect is poor or even the failure analysis cannot be carried out due to the damage of the structure in the device layer is avoided.
Optionally, in the embodiment of the present invention, the thickness of the substrate material in the first target region in the substrate is reduced to a preset value, and then the substrate material on the second target region is removed to expose the target line, so as to avoid the occurrence of a situation that structures such as a line and a device in a device layer are damaged due to the direct removal of the substrate to expose the target line, and further ensure the integrity of the line and the device in the first target region.
Optionally, in the embodiment of the present invention, an EMMI (Emission Microscope) or an OBIRCH (Optical Beam Induced Resistance Change) is used to perform hot spot positioning with a lower resolution, the probe is electrically connected to the target line after the target line is exposed, and an EBIRCH (Electrical Beam Induced Resistance Change) is used to accurately position the failure point, so that the process time is short and the positioning accuracy is high.
According to the failure analysis method of the stacked packaged chip provided by the embodiment of the invention, when the stacked packaged chip comprises two or more failure tube cores, the failure analysis is carried out on all the failure tube cores one by taking the distance between the failure tube cores and the lead frame as the sequence, so that the failure analysis information of a plurality of tube cores can be obtained, the analysis efficiency of the stacked packaged chip is improved, the defects in design and production are favorably corrected, the generation efficiency is improved, and the reliability and the stability of the manufacturing process are improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 illustrates a method flow diagram of a method of die failure analysis of an embodiment of the present invention;
FIGS. 2a to 2d are schematic structural diagrams illustrating steps of a die failure analysis method according to an embodiment of the present invention;
FIG. 3 is a flow chart of a method of stacked package chip failure analysis according to an embodiment of the invention;
fig. 4a to 4c are schematic structural diagrams illustrating steps of a stacked package chip failure analysis method according to an embodiment of the invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, the same elements or modules are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "connected to" another element or circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.
Also, certain terms are used throughout the description and claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. This patent specification and claims do not intend to distinguish between components that differ in name but not function.
In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Moreover, it is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Fig. 1 shows a method flowchart of a die failure analysis method according to an embodiment of the present invention, and fig. 2a to 2d show schematic structural diagrams of steps of the die failure analysis method according to an embodiment of the present invention. The method flow diagram of fig. 1 will be described with reference to fig. 2a to 2 d.
Die 220 includes a substrate 221 and a device layer 222 located over substrate 221. The substrate 221 is selected from a silicon substrate, for example, and the device layer 222 includes structures such as lines, devices, and the like.
In step S410, a hot spot is located on a defect in the die 220 from the back side of the die 220, i.e., the side where the substrate 221 is located.
As shown in fig. 2a, fig. 2a shows a cross-sectional view and a bottom view of die 220, using either or a combination of EMMI, OBIRCH, or both, to locate a hot spot 223 of die 220 from the backside of die 220.
In an alternative embodiment, a laser is used to form a plurality of marker dots 224 on the surface of the substrate 221 away from the device layer 222 to define a first target area 225. Wherein the hotspot 223 is located within the first target region 225.
In step S420, from the backside of the die 220, the substrate 221 is removed to expose the target line. Wherein, step S420 includes:
step S421, the substrate material on the first target area is cut. As shown in fig. 2b, fig. 2b shows a cross-sectional view and a bottom view of the die 220, a PFIB (Plasma Focused ion beam) or FIB (Focused ion beam) is used to cut the substrate material on the first target region 225 until the thickness of the substrate 221 within the first target region 225 is reduced to a preset value x1 to form the first opening 226.
Alternatively, the first target area is for example selected from a square with a side length of 150 micrometers, and the preset value x1 is for example selected from 2 micrometers.
The PFIB or FIB cutting has higher precision and better controllability, and can avoid material deformation caused by a grinding process, maintain the structural strength of the substrate 221 and prevent the die 220 from generating cracks in subsequent processing.
Step S422, remove the substrate material of the second target area. Fig. 2c shows a close-up view of the first aperture 226 of fig. 2 b. A second target area 227 including the target line is determined from the layout of the die 220 and the substrate material of the second target area 227 is removed using either PFIB or FIB, resulting in a second opening 229 forming the exposed target line 228 as shown in fig. 2 d. The first opening 226 and the second opening 229 collectively constitute an opening that exposes the target line 228.
In step S430, electrical measurements are made on the backside of the die 220 to obtain information about defects. The nanoprobes are electrically connected to the target line 228, and are further positioned using EBIRCH to obtain an accurate failure point 228, and the failure point 228 is made into a sample for failure analysis to obtain defect information.
In one possible embodiment, the failure point 228 is cut and sampled using PFIB or FIB for failure analysis to obtain information about the defects of the die 220.
According to the die failure analysis method provided by the embodiment of the invention, the die 220 is subjected to failure analysis from the back side of the substrate 221, so that the structures of lines, devices and the like in the device layer 222 can be well reserved, and the condition that the failure analysis effect is poor or even the failure analysis cannot be carried out due to the damage of the structure in the device layer 222 is avoided.
Optionally, in the embodiment of the present invention, the thickness of the substrate material in the first target region 225 in the substrate 221 is reduced to the preset value x1, and then the substrate material on the second target region 227 is removed to expose the target line 228, so as to avoid the occurrence of a situation that the structure of a line, a device, and the like in the device layer 222 is damaged due to the direct removal of the substrate to expose the target line, and further ensure the integrity of the line and the device in the first target region 225.
Optionally, in the embodiment of the present invention, the EMMI/OBIRCH is used to perform the positioning of the lower resolution hot spot, the probe is electrically connected to the target line 228 after the substrate material is removed to expose the target line 228, and the EBIRCH is used to accurately position the failure spot 230, which is short in process time and high in positioning accuracy.
Fig. 3 is a flowchart of a method for analyzing a failure of a stacked chip package according to an embodiment of the present invention, and fig. 4a to 4c are schematic structural diagrams of steps of a method for locating a failure of a stacked chip package according to an embodiment of the present invention. The method flow diagram of fig. 3 will be described with reference to fig. 4a to 4 c.
As shown in fig. 4a, the stacked package chip 200 includes a lead frame 210, dies 220-1 to 220-8 stacked on the lead frame 210, an encapsulant (not shown) covering the lead frame 210 and the dies 220-1 to 220-8, and bonding wires 240 for connecting adjacent dies and dies to the lead frame 210. It should be understood that the stacked packaged chip 200 includes eight dies, two of which are failed dies, in this embodiment, however, the invention is not limited thereto, and the stacked packaged chip 200 may include four or sixteen dies, wherein the number of failed dies may be one or three.
Step S100, electrical measurements are performed on the stacked packaged chips to determine a faulty die.
Electrical measurements are performed on the stacked packaged chips 200, such as by using EFA (Electrical failure analysis) to determine that die 220-4 and die 220-6 are faulty dies.
In an alternative embodiment, the failed die 220-4 and the failed die 220-6 are marked after the step of using EFA to determine that the die 220-4 and the die 220-6 are failed dies, such as by marking the pads of the failed die 220-4 and the failed die 220-6, respectively, with probes.
Step S200, judging whether a fault tube core which is not subjected to failure analysis exists, if so, executing step S300; if not, go to step S500.
In the stacked package chip 200, if neither the failed die 220-4 nor the failed die 220-6 is failure analyzed, step S300 is performed.
Step S300, the leadframe 210, a portion of the encapsulant, and/or a portion of the die are removed until the substrate of the first failed die that has not been subjected to failure analysis is exposed.
A grinding process is used to remove the leadframe 210, a portion of the encapsulant, and the dies 220-1 through 220-3 until the substrate of the failed die 220-4 is exposed, resulting in the semiconductor structure shown in fig. 4 b.
And step S400, performing failure analysis on the semiconductor chip by using a chip failure analysis method.
Failure analysis is performed from the back side on the failed die 220-4 using the die failure analysis method shown in fig. 1.
After the failure analysis is completed, step S200 is executed.
In this embodiment, the failed die 200-6 of the stacked packaged chip 200 has not yet been subjected to failure analysis, and the above steps are continuously performed:
the die 220-4 and the die 220-5 are removed by a grinding process until the substrate of the failed die 220-6 is exposed, resulting in the semiconductor structure shown in fig. 4c, and the failed die 220-6 is analyzed for failure from the back side by the die failure analysis method shown in fig. 1. After the analysis is completed, step 200 is executed, and at this time, all the failed dies have completed the failure analysis, step S500 is executed.
And step S500, ending. Failure analysis of all failed die in the stacked packaged chips 200 has been completed.
Alternatively, the stack package chip 200 is selected from, for example, a three-dimensional memory.
According to the failure analysis method of the stacked packaged chip provided by the embodiment of the invention, when the stacked packaged chip comprises two or more failure tube cores, the failure analysis is carried out on all the failure tube cores one by taking the distance between the failure tube cores and the lead frame as the sequence, so that the failure analysis information of a plurality of tube cores can be obtained, the analysis efficiency of the stacked packaged chip is improved, the defects in design and production are favorably corrected, the generation efficiency is improved, and the reliability and the stability of the manufacturing process are improved.
In summary, according to the failure analysis method for the failed die in the embodiment of the present invention, failure analysis is performed on the failed die from the back side of the substrate, so that structures such as lines and devices in the device layer can be well retained, and the occurrence of a situation that the failure analysis effect is poor or even failure analysis cannot be performed due to the damaged structure in the device layer is avoided.
Optionally, in the embodiment of the present invention, the thickness of the substrate material in the first target region in the substrate is reduced to a preset value, and then the substrate material on the second target region is removed to expose the target line, so as to avoid the occurrence of a situation that structures such as a line and a device in a device layer are damaged due to the direct removal of the substrate to expose the target line, and further ensure the integrity of the line and the device in the first target region.
Optionally, in the embodiment of the invention, the EMMI/OBIRCH is used for positioning the hot spot with lower resolution, the probe is electrically connected with the target line after the target line is exposed, and the EBIRCH is used for accurately positioning the failure point, so that the time consumption of the process is short and the positioning accuracy is high.
According to the failure analysis method of the stacked packaged chip provided by the embodiment of the invention, when the stacked packaged chip comprises two or more failure tube cores, the failure analysis is carried out on all the failure tube cores one by taking the distance between the failure tube cores and the lead frame as the sequence, so that the failure analysis information of a plurality of tube cores can be obtained, the analysis efficiency of the stacked packaged chip is improved, the defects in design and production are favorably corrected, the generation efficiency is improved, and the reliability and the stability of the manufacturing process are improved.
It should be noted that as used herein, the words "during", "when" and "when … …" in relation to the operation of a circuit are not strict terms indicating an action that occurs immediately upon the start of a startup action, but rather there may be some small but reasonable delay or delays, such as various transmission delays, between it and the reaction action (action) initiated by the startup action. The words "about" or "substantially" are used herein to mean that the value of an element (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation that makes it difficult for the value or position to be exactly the stated value. It has been well established in the art that a deviation of at least ten percent (10%) for a semiconductor doping concentration of at least twenty percent (20%) is a reasonable deviation from the exact ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used.
In accordance with the present invention, as set forth above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The scope of the invention should be determined with reference to the appended claims and their equivalents.
Claims (10)
1. A method of analyzing die failure, the die comprising a substrate and a device layer located on the substrate,
the failure analysis method comprises the following steps:
carrying out hot spot positioning on the defects in the tube core from the back surface of the tube core, namely the surface where the substrate is positioned;
removing the substrate from the backside of the die to expose a target line; and
electrical measurements are made on the backside of the die to obtain information about the defects.
2. The die failure analysis method of claim 1, further comprising, after the step of hot spot locating defects in the die from the backside of the die:
and forming a marking point on the surface of the substrate by using laser according to the hot spot positioning so as to determine a first target area.
3. The die failure analysis method of claim 2, the hot spot locating defects in the die from the backside of the die comprising:
hot spot locating defects in the die from the backside of the die using either one of micro-light microscopy, light induced resistance change, or a combination thereof.
4. The die failure analysis method of claim 3, the removing the substrate from the backside of the die to expose a target line comprising:
cutting the substrate material on the first target area by adopting either a focused ion beam or a plasma focused ion beam, and reducing the substrate thickness of the first target area to a preset value;
determining a second target area including the target line according to the layout, and removing substrate material of the second target area by adopting either the focused ion beam or the plasma focused ion beam to form an opening exposing the target line; wherein the content of the first and second substances,
the second target region is located in the first target region.
5. The die failure analysis method of claim 1, the making electrical measurements on the backside of the die to obtain information of defects comprising:
and electrically connecting a probe with the target circuit, and acquiring the information of the defect by adopting electrically induced resistance change.
6. The die failure analysis method of claim 5, the obtaining information of the defect using electrically induced resistance changes comprising:
and positioning a failure point by adopting electric induction resistance change, and preparing the failure point into a sample by adopting any one of a focused ion beam or a plasma focused ion beam and carrying out failure analysis to obtain the information of the defect.
7. The method of failure analysis of a faulty die of claim 4, the preset value being 2 microns.
8. The method of failure analysis of a failed die of claim 2, the first target area being a square 150 microns on a side.
9. A method of failure analysis for a stacked packaged chip, the stacked packaged chip comprising a leadframe, a plurality of dies stacked on the leadframe, and an encapsulant covering the leadframe and the plurality of dies,
the failure analysis method comprises the following steps:
performing electrical measurements on the stacked packaged chips to determine a failed die;
if a fault tube core which is not subjected to failure analysis exists in the stacked packaged chips, the failure analysis step is repeatedly executed; wherein the content of the first and second substances,
the failure analysis step comprises:
removing the lead frame, a portion of the encapsulant, and/or the die until a substrate of a first failed die that has not been subjected to failure analysis is exposed;
performing a failure analysis on the faulty die using the failure analysis method of any of claims 1-8.
10. The method of failure analysis of stacked packaged chips of claim 9, said removing said leadframe, a portion of said encapsulant, and/or a die comprising:
a grinding process is used to remove the leadframe, a portion of the encapsulant, and/or the die.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114441598A (en) * | 2022-04-11 | 2022-05-06 | 胜科纳米(苏州)股份有限公司 | 3D stacked and packaged integrated circuit chip and failure positioning method and device thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114441598A (en) * | 2022-04-11 | 2022-05-06 | 胜科纳米(苏州)股份有限公司 | 3D stacked and packaged integrated circuit chip and failure positioning method and device thereof |
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