CN113870748A - Display picture testing method and testing device - Google Patents
Display picture testing method and testing device Download PDFInfo
- Publication number
- CN113870748A CN113870748A CN202111136269.9A CN202111136269A CN113870748A CN 113870748 A CN113870748 A CN 113870748A CN 202111136269 A CN202111136269 A CN 202111136269A CN 113870748 A CN113870748 A CN 113870748A
- Authority
- CN
- China
- Prior art keywords
- control chip
- signal
- display
- level clock
- pattern generator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 claims abstract description 15
- 230000008569 process Effects 0.000 claims abstract description 8
- 238000012549 training Methods 0.000 claims description 25
- 230000005540 biological transmission Effects 0.000 claims description 18
- 238000011084 recovery Methods 0.000 claims description 18
- 230000005856 abnormality Effects 0.000 claims description 8
- 230000008054 signal transmission Effects 0.000 claims description 4
- 238000010998 test method Methods 0.000 claims 6
- 230000002159 abnormal effect Effects 0.000 abstract description 22
- 239000002699 waste material Substances 0.000 abstract description 7
- 238000012544 monitoring process Methods 0.000 abstract description 5
- 238000002474 experimental method Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000005034 decoration Methods 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention relates to a method and a device for testing a display picture.A pattern generator can keep a starting-up state when monitoring that the picture display is abnormal, so that abnormal pictures can be continuously displayed, a time sequence control chip can be always kept in the starting-up display process when the abnormal phenomenon occurs, the manpower waste caused by the observation of manpower by naked eyes or the financial waste caused by CCD monitoring is saved, the abnormal state is timely saved, and the analysis of an analyst is convenient.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display screen testing method and a display screen testing apparatus.
Background
One of the reliability tests of the display panel is a power-on/power-off test, which is a test for periodically powering on/off the display panel at normal temperature or high/low temperature to check whether the product has random or probabilistic defects, and whether the product has an abnormality under severe conditions or whether the product has an abnormality in an initialization state.
In a reliability experiment, a time sequence control chip (Tcon) may have probabilistic abnormality due to continuous power on/off, which causes abnormal image display of a display panel in a power on state, but the image may be recovered after the power on next time after the power off, and the abnormality is hard to reappear again, which causes the abnormality to be ignored or missed, thereby causing difficulty in analyzing the abnormal problem by an analyst.
In order to avoid neglecting or missing the problem, the existing solution is to have a testing staff to sit in front of the platform all the time to observe the display screen image and record whether there is an abnormal phenomenon when doing the reliability test. However, since the power on/off experiment is often performed ten thousand times, the experimenter always observes in front of the platform to cause great waste of manpower, and the fatigue of the experimenter also causes the possibility of missing abnormal phenomena. Moreover, because a plurality of platforms are needed to carry out the experiment simultaneously in the reliability experiment, if a CCD (charge coupled device) is erected in front of each platform for monitoring, material resources are greatly wasted, and the cost is increased.
Disclosure of Invention
The invention aims to provide a display picture testing method and a testing device to solve the problem that the difficulty in finding abnormal phenomena in the conventional startup and shutdown experiment is high.
Specifically, the technical scheme adopted by the invention is as follows:
a display screen testing method comprises the following steps:
the pattern generator transmits a high-level clock lock signal to the time sequence control chip;
the time sequence control chip pulls down the high-level clock lock signal into a low-level clock lock signal;
the pattern generator transmits a display signal to the time sequence control chip;
and in the transmission process of the display signal, if the high-level clock lock signal appears in the time sequence control chip again at least once, the pattern generator keeps a power-on state.
Optionally, the step of keeping the pattern generator in the power-on state further includes that the timing control chip pulls down the high-level clock lock signal appearing again to a low-level clock lock signal, and the pattern generator transmits a display signal to the timing control chip.
Optionally, the step of the pattern generator transmitting the high-level clock lock signal to the timing control chip further includes:
the pattern generator transmits a clock data recovery training signal to the timing control chip to initiate a handshake operation;
the time sequence control chip recovers the transmitted clock signal according to the clock data recovery training signal;
and the time sequence control chip pulls down the high-level clock lock signal into a low-level clock lock signal to finish the handshake operation.
Optionally, in the display signal transmission process, if a high-level clock lock signal occurs again in the timing control chip, the pattern generator transmits a clock data recovery training signal to the timing control chip to reinitiate the handshake operation.
Optionally, the occurrence duration of the high-level clock lock signal occurring in the display signal transmission process corresponds to the transmission duration of the clock data recovery training signal.
Optionally, the occurrence duration of the high-level clock lock signal is greater than or equal to 2 ms.
Optionally, in the display signal transmission process, if a high-level clock lock signal occurs again in the timing control chip, the graphic generator displays a prompt message to prompt an abnormality.
Optionally, the power-on start time of the pattern generator is earlier than the start time of the pattern generator transmitting the clock data recovery training signal to the timing control chip.
Optionally, the sum of the duration of the single handshake operation and the duration of the single transmission of the display signal by the graphic generator is less than the duration of the single power-on.
In order to achieve the above object, the present invention further provides a testing apparatus, comprising: the pattern generator comprises a display module for displaying prompt information; the control panel comprises a time sequence control chip, the pattern generator is connected with a signal receiving end of the time sequence control chip through an input end of the control panel, and a signal output end of the time sequence control chip is connected with an output end of the control panel.
The display picture testing method and the testing device provided by the invention have the beneficial effects that when the picture display abnormity is monitored, the pattern generator can keep the starting-up state, so that the abnormal picture can be continuously displayed, the time sequence control chip can be always kept in the starting-up display process when the abnormity occurs, the manpower waste caused by the observation of manpower by naked eyes or the financial waste caused by the monitoring of a CCD (charge coupled device) is saved, the abnormal state is timely saved, and the analysis of an analyzer is convenient.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
FIG. 1 is a flowchart illustrating a method for testing a display according to an exemplary embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a testing apparatus and a display panel according to an exemplary embodiment of the invention;
FIG. 3 is a signal waveform diagram in a normal display state in a display screen testing method according to an exemplary embodiment of the present invention;
FIG. 4 is a waveform diagram of signals when an abnormal display state occurs in the method for testing a display screen according to an exemplary embodiment of the present invention;
the parts in the figure are numbered as follows:
100. the device comprises a testing device, 110, a pattern generator, 111, a display module, 120, a control panel, 121, an input end, 122, an output end, 130 and a time sequence control chip;
200. a display panel.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The display picture testing method and the testing device can keep the startup state when the picture display abnormity is monitored by the pattern generator, so that the abnormal picture can be continuously displayed, the time sequence control chip can be always kept in the startup display process when the abnormity occurs, the manpower waste caused by the observation of the human eyes or the financial waste caused by the monitoring of the CCD is saved, the abnormal state is timely saved, and the analysis of an analyzer is convenient. As a typical application, the display screen testing method of the present invention may be applied to a reliability experiment test of a display panel, such as a liquid crystal display panel, an OLED display panel, and the like, the display panel tested by the testing method may be applied to a mobile terminal, the mobile terminal includes a terminal main body and a display panel, and the mobile terminal may be: any product or component with practical functions such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
In an embodiment of the present invention, a testing apparatus 100 is used to perform a reliability test on a power on/off operation of a display Panel 200(Panel), the testing apparatus 100 includes a Pattern Generator 110 (PG) and a Control Board 120(CB, Control Board), a timing Control chip 130(Tcon) is disposed on the Control Board 120, the Pattern Generator 110 is connected to a signal receiving end of the timing Control chip 130 through an input end 121 of the Control Board 120, a signal output end of the timing Control chip 130 is connected to an output end 122 of the Control Board 120, and an output end 122 of the Control Board 120 is connected to the display Panel 200.
Referring to fig. 1, the method for testing a display screen provided in this embodiment includes:
s110, the pattern generator 110 transmits a high-level clock lock signal Lockn1 to the timing control chip 130;
s120, the timing control chip 130 pulls down the high-level clock lock signal Lockn1 into a low-level clock lock signal Lockn 2;
s130, the pattern generator 110 transmits a display signal Sd to the timing control chip 130;
s140, during the transmission of the display signal Sd, if a high-level clock lock signal Lockn1 appears in the timing control chip 130, the pattern generator 110 maintains the power-on state.
Referring to fig. 3, the graphic generator 110 is powered on and turned on, the clock lock signal Lockn generated by the graphic generator 110 is a high level clock lock signal Lockn1, the graphic generator 110 transmits the high level clock lock signal Lockn1 to the timing control chip 130, the timing control chip 130 pulls down the high level clock lock signal Lockn1 to a low level clock lock signal Lockn2 and locks it to a low level clock lock signal Lockn2, that is, during the transmission of the display signal Sd, the timing control chip 130 locks the clock lock signal Lockn to the low level clock lock signal Lockn2 and informs the graphic generator 110 to transmit the display signal Sd, the timing control chip 130 transmits the display signal Sd to the display panel 200 through the control board 120 for displaying, at this time, the display screen displayed by the display panel 200 is a normal display screen, the graphic generator 110 transmits the display signal Sd for a period of time (the time can be set according to actual test requirements), the pattern generator 110 stops transmitting the display signal Sd to the timing control chip 130, the timing control chip 130 is unlocked, the low level clock lock signal Lockn2 is recovered to the high level clock lock signal Lockn1, the pattern generator 110 is powered off, a power on/off experiment is completed, and in such a reciprocating manner, a periodic power on/off alternation experiment can be performed to test the display reliability of the display panel 200.
In the process of transmitting the display signal Sd, if the high-level clock lock signal Lockn1 'occurs again, it indicates that the timing control chip 130 is unlocked, that is, the timing control chip 130 loses the lock on the low-level clock lock signal Lockn2 and recovers to the high-level clock lock signal Lockn1, and an abnormal state occurs, at this time, the display panel 200 keeps a power-on state (i.e., keeps the power-on state) by the pattern generator 110, the power-on and power-off experiment is terminated, so that the abnormal state occurs is retained, then the timing control chip 130 pulls down and locks the high-level clock lock signal Lockn 1' that occurs again to the low-level clock lock signal Lockn2, and the pattern generator 110 continues to transmit the display signal Sd to the timing control chip 130.
As an improvement, in this embodiment, before transmitting the display signal Sd to the timing control chip 130, the pattern generator 110 is powered on and transmits a clock data recovery training signal CDR training to the timing control chip 130 to initiate a handshake operation, the timing control chip 130 recovers a transmitted clock signal clock (not shown in the figure) according to the clock data recovery training signal CDR training, then the timing control chip 130 pulls down the high-level clock lock signal Lockn1 to a low-level clock lock signal Lockn2 to complete the handshake operation, and the pattern generator 110 transmits the display signal Sd to the timing control chip 130. The clock data recovery training signal CDR training corresponds to the high level clock lock signal Lockn 1. During the transmission of the display signal Sd, if the high level clock lock signal Lockn1 ' occurs again in the timing control chip 130, that is, the high level clock lock signal Lockn1 ' occurs for the second time (the first occurrence is a handshake operation between the timing control chip 130 and the graphic generator 110), indicating that the timing control chip 130 is out of lock (the surface handshake operation is turned off), the timing control chip 130 loses the lock of the low level clock lock signal Lockn2 and returns to the high level clock lock signal Lockn1 ', an abnormal state occurs (the normal state, that is, the timing control chip 130 continuously locks the low level clock lock signal Lockn2 during the transmission of the display signal Sd), at this time, due to the occurrence of the high level clock lock signal Lockn1 ', the graphic generator 110 transmits a clock data recovery training signal CDR training to the timing control chip 130 to reinitiate the handshake operation, the timing control chip 130 pulls down the high level clock lock signal Lockn1 ' occurring again to the low level clock lock signal Lockn2 to complete the handshake operation, at this time, the pattern generator 110 keeps the power-on state (i.e., keeps the power-on state), the display panel 200 keeps the power-on state accordingly, and the power-on/off experiment is terminated, so as to keep the abnormal state, and the timing control chip 130 transmits the clock data recovery training signal CDR training transmitted for the second time to the display panel 200 through the control board 120, so that the display panel 200, which should display the display signal Sd transmitted by the pattern generator 110, displays the clock data recovery training signal, and the abnormal state of the display screen occurs.
As a preferable mode, to eliminate the influence of noise, in the transmission process of the display signal Sd, the pattern generator 110 triggers the abnormal state handling mechanism after the occurrence time of the high-level clock lock signal Lockn 1' is 2ms or more, that is, the pattern generator 110 remains in the power-on state, and the setting criterion of the required time for triggering the abnormal state handling mechanism is: the duration of the handshake operation between the pattern generator 110 and the timing control chip 130 is longer than that of the handshake operation between the pattern generator 110 and the timing control chip 130, that is, since the high-level clock lock signal Lockn1 'occurs for the second time, the handshake operation between the pattern generator 110 and the timing control chip 130 needs to be performed again, and the duration of the handshake operation is generally longer than 2ms, the abnormal state handling mechanism is triggered after the high-level clock lock signal Lockn 1' occurs for 2 ms. The occurrence duration of the high-level clock lock signal Lockn 1' occurring during the transmission of the display signal Sd corresponds to the transmission duration of the clock data recovery training signal CDR training.
As a modification, the graphic generator 110 may be provided with a display module 111 for displaying a prompt message to prompt the occurrence of an abnormality. In this embodiment, the display module 111 may be an LED nixie tube or a display screen, and the prompt message may be a number (e.g. 8888) or a letter.
Referring to fig. 3 and 4, the power-on start time of the pattern generator 110 is earlier than the start time of the pattern generator 110 transmitting the clock data recovery training signal CDR training to the timing control chip 130; in the normal transmission process of the display signal Sd, the sum of the single handshake operation time length Tt and the single transmission time length Td of the display signal Sd by the graphic generator is less than the single power-on time length Tc. When the high-level clock lock signal Lockn 1' appears during the normal transmission of the display signal Sd, the power-on state is maintained. The single power-on time Tc is the time from one power-on to power-off, the power-on and the power-off are periodically alternated, the periodic power-on and power-off alternation experiment is realized, and the power-on voltage is 12V.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A display screen testing method is characterized by comprising the following steps:
the pattern generator transmits a high-level clock lock signal to the time sequence control chip;
the time sequence control chip pulls down the high-level clock lock signal into a low-level clock lock signal;
the pattern generator transmits a display signal to the time sequence control chip;
and in the transmission process of the display signal, if the high-level clock lock signal appears in the time sequence control chip again at least once, the pattern generator keeps a power-on state.
2. The method for testing a display screen according to claim 1, wherein the step of the pattern generator maintaining the power-on state further comprises the step of the timing control chip pulling down the high-level clock lock signal appearing again to a low-level clock lock signal, and the pattern generator transmitting a display signal to the timing control chip.
3. The display screen test method according to claim 1,
the step of the pattern generator transmitting the high level clock lock signal to the timing control chip further comprises:
the pattern generator transmits a clock data recovery training signal to the timing control chip to initiate a handshake operation;
the time sequence control chip recovers the transmitted clock signal according to the clock data recovery training signal;
and the time sequence control chip pulls down the high-level clock lock signal into a low-level clock lock signal to finish the handshake operation.
4. The method according to claim 3, wherein in the display signal transmission process, if a high level clock lock signal occurs again in the timing control chip, the pattern generator transmits a clock data recovery training signal to the timing control chip to reinitiate the handshake operation.
5. The display screen test method according to claim 4, wherein an occurrence period of a high-level clock lock signal occurring during transmission of a display signal corresponds to a transmission period of the clock data recovery training signal.
6. The display screen test method according to claim 4, wherein the high level clock lock signal occurs for a period of time greater than or equal to 2 ms.
7. The method according to claim 4, wherein in the transmission of the display signal, if the high level clock lock signal occurs again in the timing control chip, the graphic generator displays a prompt message to prompt an abnormality.
8. The display screen test method according to claim 3, wherein a power-on start time of the pattern generator is earlier than a start time of the pattern generator transmitting the clock data recovery training signal to the timing control chip.
9. The display screen test method according to claim 3, wherein the sum of the duration of a single handshake operation and the duration of a single transmission of the display signal by the graphics generator is less than the duration of a single power-on.
10. A test apparatus, characterized in that the test apparatus performs a test by using the display screen test method according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111136269.9A CN113870748A (en) | 2021-09-27 | 2021-09-27 | Display picture testing method and testing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111136269.9A CN113870748A (en) | 2021-09-27 | 2021-09-27 | Display picture testing method and testing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113870748A true CN113870748A (en) | 2021-12-31 |
Family
ID=78991252
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111136269.9A Pending CN113870748A (en) | 2021-09-27 | 2021-09-27 | Display picture testing method and testing device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113870748A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103854617A (en) * | 2012-11-28 | 2014-06-11 | 乐金显示有限公司 | Method of detecting data bit depth and interface device for display device using the same |
| CN107071568A (en) * | 2017-04-10 | 2017-08-18 | 青岛海信电器股份有限公司 | Transmitter and condition control method |
| CN110021253A (en) * | 2019-04-24 | 2019-07-16 | 晶晨半导体(上海)股份有限公司 | The V-by-One signal control method and system of display device |
| CN111326098A (en) * | 2020-04-08 | 2020-06-23 | Tcl华星光电技术有限公司 | Source electrode driving control method and device and display terminal |
| CN111613161A (en) * | 2020-05-19 | 2020-09-01 | 深圳Tcl数字技术有限公司 | Display data transmission method, display device and storage medium |
| CN112601090A (en) * | 2020-11-26 | 2021-04-02 | 苏州华兴源创科技股份有限公司 | Image transmission system and image signal generator |
-
2021
- 2021-09-27 CN CN202111136269.9A patent/CN113870748A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103854617A (en) * | 2012-11-28 | 2014-06-11 | 乐金显示有限公司 | Method of detecting data bit depth and interface device for display device using the same |
| CN107071568A (en) * | 2017-04-10 | 2017-08-18 | 青岛海信电器股份有限公司 | Transmitter and condition control method |
| CN110021253A (en) * | 2019-04-24 | 2019-07-16 | 晶晨半导体(上海)股份有限公司 | The V-by-One signal control method and system of display device |
| CN111326098A (en) * | 2020-04-08 | 2020-06-23 | Tcl华星光电技术有限公司 | Source electrode driving control method and device and display terminal |
| CN111613161A (en) * | 2020-05-19 | 2020-09-01 | 深圳Tcl数字技术有限公司 | Display data transmission method, display device and storage medium |
| CN112601090A (en) * | 2020-11-26 | 2021-04-02 | 苏州华兴源创科技股份有限公司 | Image transmission system and image signal generator |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11087655B2 (en) | Gate driving signal detection circuit, detection method, and display device | |
| CN102272825B (en) | Timing controller capable of switching between graphics processing units | |
| JP4181228B2 (en) | Liquid crystal display device driving circuit having power saving function | |
| CN106548761B (en) | A kind of display control circuit of display panel, display control method and relevant apparatus | |
| CN101515443B (en) | Timing controller for reducing power consumption and display device having the same | |
| US7310094B2 (en) | Liquid crystal display and driving method thereof | |
| CN106601173B (en) | time schedule controller, pixel driving method and touch display device | |
| CN108877731B (en) | Display panel driving method and display panel | |
| CN104916243B (en) | The detection method and detection means of scan drive circuit, liquid crystal panel | |
| CN103794171A (en) | Display device and method for driving the same | |
| KR101121958B1 (en) | Apparatus and method for testing lcd module of lcd system | |
| JP2009058685A (en) | Panel display device, and method for detecting abnormality in panel | |
| CN113870748A (en) | Display picture testing method and testing device | |
| CN114385100A (en) | Multi-screen lock catch state prompting system and method | |
| CN102148019A (en) | Rotary display device and picture display method of rotary display device | |
| US6661412B1 (en) | Device for testing digital monitor | |
| CN106297682A (en) | Display device and its grid drive method | |
| CN1489394A (en) | Display apparatus for detecting anormal picture signal and method thereof | |
| CN112017612A (en) | Time schedule controller, control method thereof and display device with time schedule controller | |
| WO2023221789A9 (en) | Display apparatus, panel drive circuit thereof, and charge discharge method | |
| US10963091B2 (en) | Touch panel control apparatus, touch panel control method, and input display apparatus | |
| JP2001134244A (en) | Planar display device and its driving method | |
| JP2007093695A (en) | Display driving device and drive control method thereof | |
| JPH09179532A (en) | Driving device for matrix type display panel | |
| US8237694B2 (en) | Method and circuit for controlling timings of display devices using a single data enable signal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20211231 |