JP2001134244A - Planar display device and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate a flickering of screen display caused by intrusion of noise into synchronizing signals and an erroneous conversion and to obtain a good display image on a planar display device which conducts image display based on data and synchronizing signals transmitted from a control circuit. SOLUTION: Synchronizing signals transmitted from a PC processor 16 are monitored by a signal compensating circuit 21 of a control IC14. When an abnormality is detected in signal waveforms, data and synchronizing signals being transmitted are fixed to an L or an H level in one frame scanning interval only and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat display device capable of obtaining a good display image by eliminating the influence of noise or erroneous conversion to a synchronization signal supplied from the outside and a driving method thereof.

[0002]

2. Description of the Related Art In recent years, a flat display device represented by a liquid crystal display device has been widely used as a display device for OA equipment and home electric appliances because of its thinness, light weight and low power consumption. .

FIG. 4 is a block diagram showing a general circuit configuration of a personal computer (PC) having a flat display device. In FIG. 4, the control IC 2 of the flat panel display 1 and the GUI 5 of the PC processor 4 are connected via respective I / F units 3 and 6, and
The data signal, synchronization signal, and clock signal (hereinafter, data signal, etc.) sent from the UI 5 are subjected to predetermined conversion processing by the control IC 2 and then to a display panel (not shown).
Has been sent to

In the signal transmission between the flat display device 1 and the control circuit 4, a method of transmitting a data signal or the like as a differential signal is adopted in order to reduce the influence of EMI (radio wave interference) noise. ing. In order to perform signal transmission using the differential signal, each I / F unit is provided with an LVDS circuit (not shown). I / on the PC processor 4 side
The F section 6 performs processing to increase the frequency by converting parallel data into serial data by an LVDS transmission circuit, and transmits these data signals and the like as differential signals with a reduced signal voltage (amplitude). On the other hand, the I / F unit 3 of the flat panel display 1 performs serial-parallel conversion of a received data signal or the like by a predetermined signal conversion circuit, and further performs LVDS.
The receiving circuit performs processing such as restoring the voltage and frequency of the differential signal. In the signal transmission using such a differential signal, the voltage of the data signal can be reduced, so that the influence of EMI noise can be reduced.

[0005]

When noise is mixed in a synchronous signal among data signals and the like transmitted as differential signals, or when a signal is erroneously converted by the I / F unit 3, the next stage. Erroneous operation may be performed in the control IC 2. For example, in a synchronous signal as shown in FIG. 5A, if timing is detected at the rising edge of the signal, and if noises as shown by symbols a and b in FIG. Since the rising edge is detected at a position different from the position of the signal, a malfunction such as flickering of the screen display is caused.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a flat display device capable of obtaining a good display image by preventing flickering of a screen display due to mixing of noise or erroneous conversion, and a driving method thereof.

[0007]

In order to achieve the above object, a flat display device according to the present invention comprises a matrix of display pixels including a pixel electrode, a counter electrode, and a light modulation layer interposed between these electrodes. And at least a data signal, a synchronization signal, and a clock signal from the outside of the display panel, and output a signal voltage based on the data signal to each pixel electrode of the display panel in synchronization with the synchronization signal and the clock signal. A flat panel display comprising a driving circuit unit, wherein the driving circuit unit is configured to perform signal compensation for fixing at least the data signal and the synchronization signal to a fixed level for a predetermined period when detecting an abnormality in the synchronization signal input from the outside. It is characterized by including a circuit.

Further, the method for driving a flat display device according to the present invention is characterized in that a display panel in which display pixels including a pixel electrode, a counter electrode, and a light modulation layer interposed between these electrodes are arranged in a matrix, A plane having at least a data signal, a synchronization signal, and a clock signal, and a driving circuit unit that outputs, to each pixel electrode of the display panel, a signal voltage based on the data signal in synchronization with the synchronization signal and the clock signal. In the method of driving a display device, the synchronization signal input from the outside is monitored, and when an abnormality of the synchronization signal is detected, at least the data signal and the synchronization signal are fixed at a predetermined level for a predetermined period.

According to the above configuration, when an abnormality is detected, for example, when noise is mixed in the synchronization signal input from the outside,
Since the data signal and the synchronizing signal are fixed at a fixed level for a predetermined period, the rising edge is not detected at a position different from the original signal position in the next-stage control IC or the like. Malfunction such as flicker is prevented.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which a flat display device according to the present invention and a method of driving the same are applied to a liquid crystal display device of a personal computer and a method of driving the same will be described below.

FIG. 1 is a block diagram showing a circuit configuration of a personal computer having a liquid crystal display device according to this embodiment.

A liquid crystal display device 10 shown in FIG. 1 has a liquid crystal panel 11 in which n × m display pixels are arranged in a matrix.
And an X driver 1 for driving the liquid crystal panel 11
2 and a Y driver 13 and a control I which supplies various signals such as data signals and synchronization signals to these drivers.
C14 and an I / F unit 1 for inputting an external signal
And 5.

The X driver 12 and the Y driver 1
The control circuit 3 and the control IC 14 constitute a drive circuit unit of the liquid crystal display device 10.

The liquid crystal panel 11 is a light transmission type display panel for displaying images by using light from a backlight (not shown). The signal lines X1, X2... Xm and the scanning lines Y1,
In the vicinity of the intersection with Y2... Yn, a TFT using amorphous silicon (a-Si) for an active layer, a pixel electrode, a counter electrode, and a liquid crystal as a light modulation layer held between these electrodes Layers and the like (both not shown) are arranged.

The X driver (signal line driving circuit) 12 includes a shift register, a D / A converter, and a latch circuit, and outputs a horizontal clock signal (CPH) and a horizontal synchronizing signal (S
TH) and the data signal (DATA) input together with
Signal lines X1, X2... Xm as analog video signals
Output to

A Y driver (scanning line drive circuit) 13 includes a shift register and a buffer, and applies scanning signals to scanning lines Y1, Y2,... Yn based on a vertical clock signal (CPV) and a vertical synchronizing signal (STV). Is output.

The control IC 14 includes a timing control unit (not shown) for controlling the timing of a digital data signal supplied from the PC processor 16, which will be described later.
Based on the synchronization signal and the clock signal supplied from the PC processor 16, the X driver 12 outputs the CPH and ST to the X driver 12.
The H driver 13 is provided with a circuit (not shown) for supplying CPV and STV, respectively. The synchronizing signal is input as a composite synchronizing signal including a vertical synchronizing signal and a horizontal synchronizing signal, and is separated into two signals on the output side of the control IC 14.

The control IC 14 monitors the synchronizing signal supplied from the PC processor 16 and, when detecting an abnormality due to noise contamination or erroneous conversion in the signal waveform, changes the signal waveform of each of the data signal and the synchronizing signal to one.
A signal compensation circuit 21 is provided which is fixed at “L” or “H” level for a predetermined period such as a horizontal scanning period or a one-frame scanning period (fixed to “L” level in this embodiment).

The I / F unit 15 converts the differential signals transmitted from the PC processor 16 as a plurality of serial data into LV signals.
The data is converted into parallel data by a DS receiving circuit (not shown), and a process of restoring the voltage of the differential signal is performed.

The PC processor 16 has a GUI 17 and I
/ F section 18. The data signal, synchronization signal, and clock signal sent from the GUI 17 are
The F section 18 performs parallel-to-serial conversion of data such as a data signal by a built-in LVDS transmission circuit (not shown), lowers the signal voltage, and transmits the signal to the control IC 14 as a differential signal.

Next, the circuit configuration of the signal compensation circuit 21 included in the control IC 14 will be described, and the operation thereof will be described.

FIG. 2 is a block diagram showing a circuit configuration of the signal compensation circuit 21. The signal compensation circuit 21 includes a signal comparison circuit 22 and a masking circuit 23.

The signal comparison circuit 22 is a PC processor 16
This is a circuit for monitoring an abnormality in the signal waveform of the synchronization signal sent from the control circuit, and is configured by a circuit including a PLL.
The signal comparison circuit 22 compares the synchronization signal subjected to a predetermined conversion process in the I / F unit 15 with a standard signal supplied from a pulse generation circuit (not shown) set by an external setting pin 24. When the two signal waveforms match, nothing is output to the masking circuit 23, and only when the two signal waveforms do not match, an abnormality detection signal is output to the masking circuit 23.

The signal comparing circuit 22 is provided with a plurality of external setting pins 24, and can be connected to a pulse generating circuit driven at a target frequency depending on the connection position of the pins. For example, XGA size, frame frequency 60Hz,
When the clock frequency is 65 MHz, the horizontal period is 60.00
A pulse generating circuit that generates a standard signal of 4 Hz and a vertical period of 48.363 KHz is set by an external setting pin. In addition,
The standard signal may be created by a method of counting from a clock signal input from the outside.

The masking circuit 23 includes a signal comparing circuit 22
, The input data signal and the synchronization signal are fixed at the “L” level (or “H” level) for, for example, one frame scanning period. Masking circuit 2
3 is provided with a counter circuit (not shown). When an abnormality detection signal is received from the signal comparison circuit 22, for example, by counting the number of pulses of a clock signal, the end of the frame scanning period in which the abnormality occurs Detect the position.
Then, when the one frame scanning period ends, the fixing of the “L” level for the data signal and the synchronization signal is released.
Further, when the abnormality detection signal is received within the next frame scanning period, the data signal and the synchronization signal are fixed at the “L” level only for one frame scanning period. Thereafter, the data signal and the synchronization signal are fixed to the “L” level only for one frame scanning period each time the abnormality detection signal is received.

FIG. 3 is a timing chart showing the signal waveforms of the standard signal input to the signal comparison circuit 22 and the synchronization signal output from the masking circuit 23. Note that FIG.
Here, for the sake of simplicity, the signal waveforms of the actual standard signal and the synchronization signal are simplified.

FIG. 3A shows the signal waveform of the standard signal.
(B) shows a state in which noise as indicated by the symbol a is mixed in a normal synchronization signal. The signal comparison circuit 22 is a PC
The signal waveform of the synchronization signal sent from the processor 16 is compared with the signal waveform of the standard signal supplied from the external setting pin 24. Here, when the two signal waveforms substantially coincide, the abnormality detection signal is not output to the masking circuit 23, and the input synchronization signal (and data signal) is output from the masking circuit 23 as it is. Meanwhile, 2
If the two signal waveforms do not match, that is, if the comparison of the waveforms reaches the noise portion indicated by the symbol a, the signal comparison circuit 2
2 outputs an abnormality detection signal to the masking circuit 23. When the masking circuit 23 receives the abnormality detection signal from the signal comparison circuit 22, the masking circuit 23 fixes the input synchronization signal to the “L” level only for the corresponding one-frame scanning period and outputs it, as shown in FIG. . Thereafter, when the corresponding one-frame scanning period ends, the fixing of the “L” level to the synchronization signal (and the data signal) is released and output.

Although FIG. 3 shows an example in which the synchronization signal is fixed at the "L" level, it goes without saying that the data signal is also fixed at the "L" level for the same period.

As described above, when the synchronizing signal and the data signal are fixed at the "L" level (or "H" level) for a predetermined period, for example, one frame scanning period when noise is mixed in the synchronizing signal, the screen display becomes Although the entire surface of one frame is displayed in white or black, the rising edge is not detected at a position different from the original signal position (for example, the position of the symbol “a”). Malfunctions such as flickering can be prevented,
It is possible to obtain a better display image than before.

In the above embodiment, the example in which the signal compensation circuit 21 is arranged in the control IC 14 has been described. However, the signal compensation circuit 21 can be arranged in the I / F section 15.

In the above embodiment, the data signal and the synchronizing signal are fixed at the "L" level for one frame scanning period together with the occurrence of the abnormality detection signal. Alternatively, the data signal and the synchronizing signal may be fixed at the “L” level (or the “H” level) over one frame scanning period.

[0032]

As described above, according to the flat panel display device and the method of driving the same according to the present invention, a synchronization signal input from the outside is monitored, and when an abnormality is detected, at least the data signal and the synchronization signal are converted. Since the level is fixed at a fixed level for a predetermined period, there is no problem that the control IC detects a signal at a position different from the original position. Therefore, even if noise or erroneous conversion occurs in the synchronization signal, malfunction such as flickering of the screen display can be prevented, and a better display image can be obtained as compared with the related art.

[Brief description of the drawings]

FIG. 1 is an exemplary block diagram showing a circuit configuration of a personal computer including a liquid crystal display device according to an embodiment.

FIG. 2 is a block diagram illustrating a circuit configuration of a signal compensation circuit.

FIG. 3 is a timing chart showing signal waveforms of a standard signal input to a signal comparison circuit and a synchronization signal output from a masking circuit.

FIG. 4 is a block diagram showing a general circuit configuration of a personal computer including a flat panel display device.

FIG. 5 is a timing chart showing signal waveforms of a normal synchronization signal and a synchronization signal mixed with noise.

[Explanation of symbols]

 Reference Signs List 11 liquid crystal panel 12 X driver 13 Y driver 14 control IC 15, 18 I / F section 16 PC processor 17 GUI 21 signal compensation circuit 22 signal comparison circuit 23 masking circuit 24 external setting pin

Continued on the front page F term (reference) 2H093 NC27 NC34 NC58 NC59 NC64 ND10 ND40 NE07 5C006 AB05 AC02 AF44 AF59 AF65 AF78 BB16 BC03 BC06 BC13 BC16 BF03 BF04 BF15 BF49 EC05 FA23 5C080 AA10 BB05 DD06 DD09 DD30 EE32 JJ04 KK02

Claims (6)

[Claims] 1. A display panel in which display pixels each including a pixel electrode, a counter electrode, and a light modulation layer interposed between these electrodes are arranged in a matrix, and at least a data signal, a synchronization signal, and a clock signal are input from outside. A driving circuit unit that outputs a signal voltage based on the data signal to each pixel electrode of the display panel in synchronization with the synchronization signal and the clock signal. A flat display device, comprising: a signal compensating circuit for fixing at least the data signal and the synchronization signal to a fixed level for a predetermined period when an abnormality of the input synchronization signal is detected. 2. The signal compensating circuit includes: a signal comparing circuit that detects an abnormality of the synchronization signal input from the outside based on a standard signal; and at least when the signal comparing circuit detects an abnormality of the synchronization signal, 2. The flat display device according to claim 1, further comprising a masking circuit for fixing the data signal and the synchronization signal to 0 or 1 level during one frame scanning period. 3. The flat display device according to claim 2, wherein the standard signal is supplied from a predetermined pulse generation circuit set by an external setting pin. 4. The flat display device according to claim 2, wherein the masking circuit includes a counter circuit that counts the number of pulses and detects an end position of a frame scanning period in which an abnormality has occurred. 5. The flat display device according to claim 1, wherein the signal compensating circuit is included in an interface circuit arranged at a stage preceding the driving circuit unit. 6. A display panel in which display pixels each including a pixel electrode, a counter electrode, and a light modulation layer interposed between these electrodes are arranged in a matrix, and at least a data signal, a synchronization signal, and a clock signal are input from outside. A driving circuit for outputting, to each pixel electrode of the display panel, a signal voltage based on the data signal in synchronization with the synchronizing signal and the clock signal; A method of driving a flat panel display, comprising: monitoring a synchronization signal; and detecting an abnormality in the synchronization signal, wherein at least the data signal and the synchronization signal are fixed at a predetermined level for a predetermined period.