CN113868077A - Computer platform with double-double parallel system structure - Google Patents
Computer platform with double-double parallel system structure Download PDFInfo
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Abstract
The invention provides a computer platform with a double-double parallel system structure, which comprises a computer A and a computer B with different structures; an incompletely symmetrical monitoring channel and a control channel of a reliable series structure are integrated in the computer A; a fault-tolerant computer with a reliability gridding structure is integrated in the computer B; the computer A controls the output priority to be higher than that of the computer B; the B computer comprises a hot backup control computer. The double-double parallel system structure computer platform provided by the invention connects the double-machine serial security structure and the double-machine networking structure in parallel to form a novel double-double parallel fault-tolerant reliability structure, the theoretical reliability MTBF value is more than 1.625 times of that of a single machine, a synchronous indicating circuit is not arranged between the computer A and the computer B, the operation independence of the computer A and the computer B is improved, and the cable interconnection between the double machines is reduced.
Description
Technical Field
The invention belongs to the field of airborne computers, and particularly relates to a computer platform with a double-parallel system structure.
Background
On-board computer systems often employ multi-machine parallel redundant fault tolerant architectures to improve reliable performance characteristics, where Mean Time Between Failure (MTBF) is an important indicator of system reliability.
In the prior art, the improvement of the MTBF value of the two-unit parallel system (as shown in fig. 3) is 50% relative to the single processor structure, the MTBF value of the three-unit parallel system is only 22.2% relative to the two-unit parallel system, and by sequential analogy, the MTBF value of the six-unit parallel system is only 7.31% relative to the five-unit parallel system, and obviously, the improvement of the reliability of the two-unit parallel system relative to a single processor is most significant, but actually, the two-unit parallel system is not suitable for being directly used in a use environment with high requirements on safety and reliability, and the two-unit system is more suitable for being applied only as the series system structure (as shown in fig. 4) by adopting a working mechanism of mutual comparison monitoring based on safety consideration. Although the two units adopt a serial structure, which is important to ensure the safety of the system compared with a single unit structure, the reliability MTBF value is only 1/2 of the single unit, in order to solve the problem of low reliability, the 2 computers with two-unit series structure can be connected in parallel again and then applied, the general 'double' series-parallel structure is shown in figure 5, that is, the computer A and the computer B form a parallel structure of a master/backup mode, the computer A and the computer B are both composed of a monitoring channel and a control channel, the control channel is responsible for signal output, the monitoring channel has an auxiliary monitoring function and forms a monitoring pair with the control channel, when two channels in the computer A with high priority find a fault endangering system safety or data are inconsistent, the two channels can jointly realize the cutting off of the signal output, and the computer B which is switched to the low priority level continues to realize the signal output. However, the reliability MTBF value of the "dual-dual" parallel fault-tolerant computer system is still only 0.75 times that of a single computer, and although the reliability is improved relative to the reliability of a dual-computer series structure, the reliability is still lower than the theoretical reliability MTBF value of the single computer. The reliability MTBF value under the dual-machine gridding reliability structure shown in fig. 6 is also hard to meet the requirement.
Therefore, a dual-parallel fault-tolerant computer platform suitable for an airborne core control management computer system of a military medium-large unmanned aerial vehicle and a helicopter needs to be provided.
Disclosure of Invention
In order to solve the above problems, the present invention provides a dual-dual parallel architecture computer platform, which can ensure that the serial and network architectures are effectively connected in parallel, and thus, the forward effective security feature and the enhanced reliability feature are exerted.
The invention aims to provide a double-double parallel system structure computer platform, which comprises a computer A and a computer B with different structures; an incompletely symmetrical monitoring channel and a control channel of a reliable series structure are integrated in the computer A; a fault-tolerant computer with a reliability gridding structure is integrated in the computer B; the computer A controls the output priority to be higher than that of the computer B; the B computer comprises a hot backup control computer.
The computer platform with double-parallel architecture provided by the invention is also characterized in that the monitoring channel comprises a first processor, a first input signal circuit, a first channel cross link, a first synchronization circuit, a first monitoring circuit, a first watchdog, a first internal power supply, a first connection/fault logic circuit, a control channel ID, a signal output circuit, a first signal transmission switch KA1, a second signal output switch KA2 and a connection delay circuit; the control channel comprises a second processor, a second input signal circuit, a second channel cross link, a second synchronization circuit, a second monitoring circuit, a second watchdog, a second internal power supply, a second on/fault logic circuit, a monitoring channel ID, an authorization release delay circuit, a safety indication circuit and an A/B machine communication circuit.
The computer platform with double-double parallel connection system structure provided by the invention is also characterized in that a bidirectional direct communication path is arranged between the first input signal circuit and the second input signal circuit; the first processor circuit and the second processor circuit realize bidirectional communication through a first channel cross link, a first synchronous circuit, a second channel cross link and a second synchronous circuit; said first and second on/fault logic circuits being interconnected to effect a bi-directional status indication; the control channel ID is input to a first on/off logic circuit as a priority identification signal; the monitoring channel ID is used as a priority identification signal and is input into a second channel/fault logic circuit; computer ID is input to both the first and second pass/fail logic circuits.
The computer platform with the double-double parallel architecture is also characterized in that the first signal transmission switch KA1 and the second signal output switch KA2 are arranged in series; the first signal output switch KA1 is controlled by a control signal output by the first on/fault logic circuit; the second signal output switch KA2 is controlled by the control signal output by the second on/fault logic circuit; the output ends of the first signal output switch KA1 and the second signal output switch KA2 carry out loop-back monitoring through a control channel and a monitoring channel.
The computer platform with the double-double parallel system structure provided by the invention is also characterized in that the computer B comprises a main processor module A, a main processor module B, a system I/O processor module A and a system I/O processor module B, wherein the main processor module A is connected with the system I/O processor module A through a double-port memory A-M and is connected with the system I/O processor module B through a double-port memory B-M; the main processor module B is connected with the system I/O processor module A through a dual-port memory A-S, and is connected with the system I/O processor module B through a dual-port memory B-S, and the system I/O processor module A and the system I/O processor module B are connected with the computer A.
The computer platform with double-double parallel system structure provided by the invention is also characterized in that the main processor module A comprises a main processor A, a main processor A bus and a first special data communication line; the main processor A is connected with the watchdog 1-1, the ID identification 1-1, the synchronization A, the data transmission A, the data reception A, the double-port memory A-M and the double-port memory B-M through a main processor A bus; the main processor A is used for connecting the embedded USB flash disk A through a first special data communication line; monitoring result signals output by the watchdog 1-1 and the ID identification 1-1 are transmitted to the fault comprehensive monitoring 1-1; and the signal output end of the fault comprehensive monitoring 1-1 is connected with the main processor module B.
The computer platform with double-double parallel system structure provided by the invention is also characterized in that the main processor module B comprises a main processor B, a main processor B bus and a second special data communication line; the main processor B is connected with the watchdog 2-1, the ID identification 2-1, the synchronization B, the data transmission B and the data reception B through a main processor B bus; the main processor B is used for connecting the embedded USB flash disk B through a second special data communication line; monitoring result signals output by the watchdog 2-1 and the ID identification 2-1 are transmitted to the fault comprehensive monitoring 2-1; and the signal output end of the fault comprehensive monitoring module 2-1 is connected with the main processor module A.
The computer platform with double parallel system structure provided by the invention is also characterized in that the system I/O processor module A comprises a system I/O processor A, ID identification 1-2, a watchdog 1-2, a system I/O output A, an output monitoring A, a fault comprehensive monitoring 1-2 and output signal connection control switches KA1 and KA 2; the system I/O processor A is connected with the A machine communication circuit 1, the ID identification 1-2, the watchdog 1-2, the system I/O output A, the output monitoring A and the fault comprehensive monitoring 1-2 through a system I/O processor A bus; the ID identification 1-2, the watchdog 1-2, the internal power supply A monitoring and the output indication signal connection fault comprehensive monitoring 1-2 of the external power supply A monitoring; the output signal of the fault comprehensive monitoring 1-2 is connected with control switches KA1 and KA 2; the signal output by the system I/O output A, the KA1 switch output signal and the KA2 switch output signal are connected with the output monitor A; the fault comprehensive monitoring 1-2 outputs an indication signal to be connected with the I/O processor module A of the system; and the computer B inputs the ID of the fault comprehensive monitoring 1-2.
The computer platform with double-parallel architecture provided by the invention is also characterized in that the system I/O processor module B comprises a system I/O processor B, ID, an identification 2-2, a watchdog 2-2, a system I/O output B, an output monitoring B, a fault comprehensive monitoring 2-2 and output signal connection control switches KB1 and KB 2; the system I/O processor B is connected with the machine A communication circuit 2, the ID identification 2-2, the watchdog 2-2, the system I/O output B, the output monitoring B and the fault comprehensive monitoring 2-2 through a system I/O processor B bus; the ID identification 2-2, the watchdog 2-2, the internal power supply B monitoring and the output indication signal connection fault comprehensive monitoring 2-2 of the external power supply B monitoring; the output signal of the fault comprehensive monitoring 2-2 is connected with control switches KB1 and KB 2; the signal output by the system I/O output B, the KB1 switch output signal and the KB2 switch output signal are connected with the output monitor B; the fault comprehensive monitoring 2-2 outputs an indication signal to be connected with the I/O processor module A of the system; and the computer B inputs the ID of the fault comprehensive monitoring 2-2.
The computer platform with the double-parallel system structure is also characterized in that the computer A is also provided with a safety indication circuit and an A/B pole communication circuit which are used for being connected with the computer B; and the computer B is provided with a safety indication receiving circuit which is used for being connected with the computer A and feeding back the result to the safety indication circuit.
Compared with the prior art, the invention has the beneficial effects that:
the double-double parallel system structure computer platform provided by the invention connects the double-machine serial security structure and the double-machine networking structure in parallel to form a novel double-double parallel fault-tolerant reliability structure, the theoretical reliability MTBF value is more than 1.625 times of that of a single machine, a synchronous indicating circuit is not arranged between the computer A and the computer B, the operation independence of the computer A and the computer B is improved, and the cable interconnection between the double machines is reduced.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a block diagram of the reliability of a dual parallel architecture computer platform provided by the present invention;
FIG. 2 is a block diagram of a dual parallel architecture computer platform provided by the present invention;
FIG. 3 is a block diagram of the reliability of a classical parallel system of the prior art;
FIG. 4 is a block diagram of the reliability of a prior art series system;
FIG. 5 is a reliability block diagram of a prior art serial-parallel architecture;
fig. 6 is a reliability block diagram of a gridding structure in the prior art.
Detailed Description
In order to make the technical means, the creation features, the achievement purposes and the effects of the invention easy to understand, the following embodiments are combined with the accompanying drawings to specifically describe the dual-dual parallel architecture computer platform provided by the invention.
In the description of the embodiments of the present invention, it should be understood that the terms "central", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only used for convenience in describing and simplifying the description of the present invention, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to a number of indicated technical features. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the invention, the meaning of "a plurality" is two or more unless otherwise specified.
The terms "mounted," "connected," and "coupled" are to be construed broadly and may, for example, be fixedly coupled, detachably coupled, or integrally coupled; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the creation of the present invention can be understood by those of ordinary skill in the art through specific situations.
As shown in fig. 1-2, an embodiment of the present invention provides a dual-dual parallel architecture computer platform, which includes a computer a and a computer B having different structures; an incompletely symmetrical monitoring channel and a control channel of a reliable series structure are integrated in the computer A; a fault-tolerant computer with a reliability gridding structure is integrated in the computer B; the computer A controls the output priority to be higher than that of the computer B; the B computer comprises a hot backup control computer. The safety structure of the double-machine series connection and the double-machine gridding structure are connected in parallel to form a novel double-double parallel fault-tolerant system structure, and the theoretical reliability MTBF value of the novel double-double parallel fault-tolerant system structure is more than 1.625 times of that of a single machine.
In some embodiments, the supervisory channel includes a first processor, a first input signal circuit, a first channel cross-link, a first synchronization circuit, a first supervisory circuit, a first watchdog, a first internal power supply, a first on/fault logic circuit, a control channel ID, a signal output circuit, a first signal delivery switch KA1, a second signal output switch KA2, and an on delay circuit; the control channel comprises a second processor, a second input signal circuit, a second channel cross link, a second synchronization circuit, a second monitoring circuit, a second watchdog, a second internal power supply, a second on/fault logic circuit, a monitoring channel ID, an authorization release delay circuit, a safety indication circuit and an A/B machine communication circuit.
In some embodiments, a bidirectional direct communication path is provided between the first input signal circuit and the second input signal circuit; the first processor circuit and the second processor circuit realize bidirectional communication through a first channel cross link, a first synchronous circuit, a second channel cross link and a second synchronous circuit; said first and second on/fault logic circuits being interconnected to effect a bi-directional status indication; the control channel ID is input to a first on/off logic circuit as a priority identification signal; the monitoring channel ID is used as a priority identification signal and is input into a second channel/fault logic circuit; computer ID is input to both the first and second pass/fail logic circuits.
In some embodiments, the first signal transmission switch KA1 and second signal output switch KA2 are arranged in series; the first signal output switch KA1 is controlled by a control signal output by the first on/fault logic circuit; the second signal output switch KA2 is controlled by the control signal output by the second on/fault logic circuit; the output ends of the first signal output switch KA1 and the second signal output switch KA2 carry out loop-back monitoring through a control channel and a monitoring channel.
In some embodiments, the computer B comprises a main processor module a, a main processor module B, a system I/O processor module a and a system I/O processor module B, wherein the main processor module a is connected with the system I/O processor module a through a dual-port memory a-M and connected with the system I/O processor module B through a dual-port memory B-M; the main processor module B is connected with the system I/O processor module A through a dual-port memory A-S, and is connected with the system I/O processor module B through a dual-port memory B-S, and the system I/O processor module A and the system I/O processor module B are connected with the computer A.
In some embodiments, the main processor module a includes a main processor a, a main processor a bus, and a first dedicated data communication line; the main processor A is connected with the watchdog 1-1, the ID identification 1-1, the synchronization A, the data transmission A, the data reception A, the double-port memory A-M and the double-port memory B-M through a main processor A bus; the main processor A is used for connecting the embedded USB flash disk A through a first special data communication line; monitoring result signals output by the watchdog 1-1 and the ID identification 1-1 are transmitted to the fault comprehensive monitoring 1-1; and the signal output end of the fault comprehensive monitoring 1-1 is connected with the main processor module B.
In some embodiments, the main processor module B includes a main processor B, a main processor B bus, and a second dedicated data communication line; the main processor B is connected with the watchdog 2-1, the ID identification 2-1, the synchronization B, the data transmission B and the data reception B through a main processor B bus; the main processor B is used for connecting the embedded USB flash disk B through a second special data communication line; monitoring result signals output by the watchdog 2-1 and the ID identification 2-1 are transmitted to the fault comprehensive monitoring 2-1; and the signal output end of the fault comprehensive monitoring module 2-1 is connected with the main processor module A.
In some embodiments, the system I/O processor module A includes a system I/O processor A, ID identifying 1-2, a watchdog 1-2, a system I/O output A, an output monitor A, a fault integration monitor 1-2, and output signal connection control switches KA1, KA 2; the system I/O processor A is connected with the A machine communication circuit 1, the ID identification 1-2, the watchdog 1-2, the system I/O output A, the output monitoring A and the fault comprehensive monitoring 1-2 through a system I/O processor A bus; the ID identification 1-2, the watchdog 1-2, the internal power supply A monitoring and the output indication signal connection fault comprehensive monitoring 1-2 of the external power supply A monitoring; the output signal of the fault comprehensive monitoring 1-2 is connected with control switches KA1 and KA 2; the signal output by the system I/O output A, the KA1 switch output signal and the KA2 switch output signal are connected with the output monitor A; the fault comprehensive monitoring 1-2 outputs an indication signal to be connected with the I/O processor module A of the system; and the computer B inputs the ID of the fault comprehensive monitoring 1-2.
In some embodiments, the system I/O processor module B includes a system I/O processor B, ID identification 2-2, a watchdog 2-2, a system I/O output B, an output monitor B, a fault integration monitor 2-2, and output signal connection control switches KB1, KB 2; the system I/O processor B is connected with the machine A communication circuit 2, the ID identification 2-2, the watchdog 2-2, the system I/O output B, the output monitoring B and the fault comprehensive monitoring 2-2 through a system I/O processor B bus; the ID identification 2-2, the watchdog 2-2, the internal power supply B monitoring and the output indication signal connection fault comprehensive monitoring 2-2 of the external power supply B monitoring; the output signal of the fault comprehensive monitoring 2-2 is connected with control switches KB1 and KB 2; the signal output by the system I/O output B, the KB1 switch output signal and the KB2 switch output signal are connected with the output monitor B; the fault comprehensive monitoring 2-2 outputs an indication signal to be connected with the I/O processor module A of the system; and the computer B inputs the ID of the fault comprehensive monitoring 2-2.
In some embodiments, the computer A is further provided with a safety indication circuit and an A/B pole communication circuit, and the safety indication circuit and the A/B pole communication circuit are used for being connected with the computer B; and the computer B is provided with a safety indication receiving circuit which is used for being connected with the computer A and feeding back the result to the safety indication circuit.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention. The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A computer platform with double-double parallel system structure is characterized in that the platform comprises a computer A and a computer B which are different in structure;
an incompletely symmetrical monitoring channel and a control channel of a reliable series structure are integrated in the computer A;
a fault-tolerant computer with a reliability gridding structure is integrated in the computer B;
the computer A controls the output priority to be higher than that of the computer B;
the B computer comprises a hot backup control computer.
2. The dual parallel architecture computer platform of claim 1,
the monitoring channel comprises a first processor, a first input signal circuit, a first channel cross link, a first synchronization circuit, a first monitoring circuit, a first watchdog, a first internal power supply, a first on/fault logic circuit, a control channel ID, a signal output circuit, a first signal transmission switch KA1, a second signal output switch KA2 and an on delay circuit;
the control channel comprises a second processor, a second input signal circuit, a second channel cross link, a second synchronization circuit, a second monitoring circuit, a second watchdog, a second internal power supply, a second on/fault logic circuit, a monitoring channel ID, an authorization release delay circuit, a safety indication circuit and an A/B machine communication circuit.
3. The dual parallel architecture computer platform of claim 2, wherein a bidirectional direct communication path is provided between the first input signal circuit and the second input signal circuit;
the first processor circuit and the second processor circuit realize bidirectional communication through a first channel cross link, a first synchronous circuit, a second channel cross link and a second synchronous circuit;
said first and second on/fault logic circuits being interconnected to effect a bi-directional status indication;
the control channel ID is input to a first on/off logic circuit as a priority identification signal;
the monitoring channel ID is used as a priority identification signal and is input into a second channel/fault logic circuit;
computer ID is input to both the first and second pass/fail logic circuits.
4. The dual parallel architecture computer platform of claim 2 or 3,
the first signal transmission switch KA1 and the second signal output switch KA2 are arranged in series;
the first signal output switch KA1 is controlled by a control signal output by the first on/fault logic circuit;
the second signal output switch KA2 is controlled by the control signal output by the second on/fault logic circuit;
the output ends of the first signal output switch KA1 and the second signal output switch KA2 carry out loop-back monitoring through a control channel and a monitoring channel.
5. The dual parallel architecture computer platform of claim 2,
the computer B comprises a main processor module A, a main processor module B, a system I/O processor module A and a system I/O processor module B,
the main processor module A is connected with the system I/O processor module A through a dual-port memory A-M and is connected with the system I/O processor module B through a dual-port memory B-M; the main processor module B is connected with the system I/O processor module A through a dual-port memory A-S and connected with the system I/O processor module B through a dual-port memory B-S;
the system I/O processor module A and the system I/O processor module B are connected with the computer A.
6. The dual parallel architecture computer platform of claim 5,
the main processor module A comprises a main processor A, a main processor A bus and a first special data communication line;
the main processor A is connected with the watchdog 1-1, the ID identification 1-1, the synchronization A, the data transmission A, the data reception A, the double-port memory A-M and the double-port memory B-M through a main processor A bus;
the main processor A is used for connecting the embedded USB flash disk A through a first special data communication line;
monitoring result signals output by the watchdog 1-1 and the ID identification 1-1 are transmitted to the fault comprehensive monitoring 1-1;
and the signal output end of the fault comprehensive monitoring 1-1 is connected with the main processor module B.
7. The dual parallel architecture computer platform of claim 5,
the main processor module B comprises a main processor B, a main processor B bus and a second special data communication line;
the main processor B is connected with the watchdog 2-1, the ID identification 2-1, the synchronization B, the data transmission B and the data reception B through a main processor B bus;
the main processor B is used for connecting the embedded USB flash disk B through a second special data communication line;
monitoring result signals output by the watchdog 2-1 and the ID identification 2-1 are transmitted to the fault comprehensive monitoring 2-1;
and the signal output end of the fault comprehensive monitoring module 2-1 is connected with the main processor module A.
8. The dual parallel architecture computer platform of claim 5,
the system I/O processor module A comprises a system I/O processor A, ID identification 1-2, a watchdog 1-2, a system I/O output A, an output monitoring A, a fault comprehensive monitoring 1-2 and output signal connection control switches KA1 and KA 2;
the system I/O processor A is connected with the A machine communication circuit 1, the ID identification 1-2, the watchdog 1-2, the system I/O output A, the output monitoring A and the fault comprehensive monitoring 1-2 through a system I/O processor A bus;
the ID identification 1-2, the watchdog 1-2, the internal power supply A monitoring and the output indication signal connection fault comprehensive monitoring 1-2 of the external power supply A monitoring;
the output signal of the fault comprehensive monitoring 1-2 is connected with control switches KA1 and KA 2;
the signal output by the system I/O output A, the KA1 switch output signal and the KA2 switch output signal are connected with the output monitor A;
the fault comprehensive monitoring 1-2 outputs an indication signal to be connected with the I/O processor module A of the system;
and the computer B inputs the ID of the fault comprehensive monitoring 1-2.
9. The dual parallel architecture computer platform of claim 5,
the system I/O processor module B comprises a system I/O processor B, ID identification 2-2, a watchdog 2-2, a system I/O output B, an output monitoring B, a fault comprehensive monitoring 2-2 and output signal connection control switches KB1 and KB 2;
the system I/O processor B is connected with the machine A communication circuit 2, the ID identification 2-2, the watchdog 2-2, the system I/O output B, the output monitoring B and the fault comprehensive monitoring 2-2 through a system I/O processor B bus;
the ID identification 2-2, the watchdog 2-2, the internal power supply B monitoring and the output indication signal connection fault comprehensive monitoring 2-2 of the external power supply B monitoring;
the output signal of the fault comprehensive monitoring 2-2 is connected with control switches KB1 and KB 2;
the signal output by the system I/O output B, the KB1 switch output signal and the KB2 switch output signal are connected with the output monitor B;
the fault comprehensive monitoring 2-2 outputs an indication signal to be connected with the I/O processor module A of the system;
and the computer B inputs the ID of the fault comprehensive monitoring 2-2.
10. The dual parallel architecture computer platform of claim 1,
the computer A is also provided with a safety indication circuit and an A/B pole communication circuit and is used for being connected with the computer B;
and the computer B is provided with a safety indication receiving circuit which is used for being connected with the computer A and feeding back the result to the safety indication circuit.
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