CN113868077B - Double-double parallel architecture computer platform - Google Patents
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- CN113868077B CN113868077B CN202111052058.7A CN202111052058A CN113868077B CN 113868077 B CN113868077 B CN 113868077B CN 202111052058 A CN202111052058 A CN 202111052058A CN 113868077 B CN113868077 B CN 113868077B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
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Abstract
The invention provides a double-double parallel architecture computer platform, which comprises an A computer and a B computer with different structures; the computer A integrates an incompletely symmetrical monitoring channel and a control channel of a reliability serial structure; integrating a fault-tolerant computer with a reliability grid structure in the computer B; the control output priority of the computer A is higher than that of the computer B; the B computer comprises a hot backup control computer. The double-double parallel architecture computer platform provided by the invention connects the double-computer serial safety structure and the double-computer networking structure in parallel to form a novel double-double parallel fault-tolerant reliability structure, the theoretical reliability MTBF value is more than 1.625 times of that of a single computer, and a synchronous indication circuit is not arranged between the A computer and the B computer, so that the running independence of the A computer and the B computer is improved, and the cable interconnection between the double computers is reduced.
Description
Technical Field
The invention belongs to the field of aviation onboard computers, and particularly relates to a double-double parallel architecture computer platform.
Background
On-board computer systems typically employ a multi-machine parallel redundant fault tolerant architecture to improve reliable performance characteristics, with Mean Time Between Failures (MTBF) being an important indicator of system reliability.
In the prior art, the MTBF value of the two-unit parallel system (as shown in fig. 3) is improved by 50% relative to the MTBF value of the single processor structure, the MTBF value of the three-unit parallel system is improved by 22.2% relative to the MTBF value of the two-unit parallel system, and the MTBF value of the six-unit parallel system is improved by 7.31% relative to the five-unit parallel system. Although the serial structure of two units is adopted to ensure the safety characteristic of the system relative to the single structure, the reliability MTBF value is only 1/2 of that of the single unit, in order to solve the problem of lower reliability, 2 computers with the two units serial structure can be connected in parallel again and then applied, the general serial-parallel structure of double pairs is shown as figure 5, namely, the A computer and the B computer form a main/standby parallel structure, the interiors of the A computer and the B computer are both composed of a monitoring channel and a control channel, the control channel is responsible for signal output, the monitoring channel plays an auxiliary monitoring function and forms a monitoring pair with the control channel, when two channels in the A computer with high priority find faults endangering the safety of the system or data are inconsistent, the two channels can jointly realize cutting off the signal output, and the B computer with low priority continuously realizes the signal output. However, the reliability MTBF of the dual parallel fault tolerant computer system is still only 0.75 times that of a single machine, and is lower than the theoretical reliability MTBF of the single machine although the reliability of the dual parallel fault tolerant computer system is improved relative to the reliability of a dual serial structure. The reliable MTBF values under the dual-machine gridded reliability architecture shown in fig. 6 are also difficult to meet.
Therefore, there is a need to provide a dual parallel fault tolerant computer platform for an on-board core control management computer system that combines both reliability and security features.
Disclosure of Invention
In order to solve the problems, the invention provides a double-double parallel architecture computer platform, which can ensure that the serial connection and the network structure are effectively connected in parallel, and the forward effective safety characteristic and the enhanced reliability characteristic are exerted.
The invention aims to provide a double-double parallel architecture computer platform, which comprises an A computer and a B computer with different structures; the computer A integrates an incompletely symmetrical monitoring channel and a control channel of a reliability serial structure; integrating a fault-tolerant computer with a reliability grid structure in the computer B; the control output priority of the computer A is higher than that of the computer B; the B computer comprises a hot backup control computer.
The dual-dual parallel architecture computer platform provided by the invention is further characterized in that the monitoring channel comprises a first processor, a first input signal circuit, a first channel cross link, a first synchronization circuit, a first monitoring circuit, a first watchdog, a first internal power supply, a first on/off logic circuit, a control channel ID, a signal output circuit, a first signal transmission switch KA1, a second signal output switch KA2 and an on delay circuit; the control channel comprises a second processor, a second input signal circuit, a second channel cross link, a second synchronous circuit, a second monitoring circuit, a second watchdog, a second internal power supply, a second on/off logic circuit, a monitoring channel ID, a weight release delay circuit, a safety indication circuit, an A computer and a B computer communication circuit.
The dual parallel architecture computer platform provided by the invention is also characterized in that a bidirectional direct communication path is arranged between the first input signal circuit and the second input signal circuit; the first processor circuit and the second processor circuit realize two-way communication through a first channel cross link, a first synchronous circuit, a second channel cross link and a second synchronous circuit; an interconnection between the first on/off logic circuit and the second on/off logic circuit to enable bi-directional status indication; the control channel ID is input into a first on/off logic circuit as a priority identification signal; the monitoring channel ID is used as a priority identification signal to be input into a second channel/fault logic circuit; the a computer ID is input into both the first on/off logic circuit and the second channel/off logic circuit.
The dual-dual parallel architecture computer platform provided by the invention is also characterized in that the first signal transmission switch KA1 and the second signal output switch KA2 are arranged in series; the first signal output switch KA1 is controlled by a control signal output by the first on/off logic circuit; the second signal output switch KA2 is controlled by a control signal output by the second on/off logic circuit; the output ends of the first signal output switch KA1 and the second signal output switch KA2 are subjected to wrapping monitoring through a control channel and a monitoring channel.
The dual-dual parallel architecture computer platform provided by the invention is also characterized in that the B computer comprises a main processor module A, a main processor module B, a system I/O processor module A and a system I/O processor module B, wherein the main processor module A is connected with the system I/O processor module A through a dual-port memory A-M and is connected with the system I/O processor module B through a dual-port memory B-M; the main processor module B is connected with the system I/O processor module A through a double-port memory A-S, and is connected with the system I/O processor module B through a double-port memory B-S, and the system I/O processor module A and the system I/O processor module B are connected with the computer A.
The dual parallel architecture computer platform provided by the present invention is further characterized in that the main processor module A includes a main processor A, a main processor A bus, and a first dedicated data communication line; the main processor A is connected with the watchdog 1-1, the ID recognition circuit 1-1, the synchronous A, the data transmission A, the data receiving A, the dual-port memory A-M and the dual-port memory B-M through a main processor A bus; the main processor A accesses the embedded USB flash disk A through a first special data communication line; the watchdog 1-1 and the monitoring result signal output by the ID recognition circuit 1-1 are transmitted to the fault comprehensive monitoring 1-1; and the signal output end of the fault comprehensive monitoring 1-1 is connected with the main processor module B.
The dual parallel architecture computer platform provided by the present invention further has such a feature that the main processor module B includes a main processor B, a main processor B bus, and a second dedicated data communication line; the main processor B is connected with the watchdog 2-1, the ID recognition circuit 2-1, the synchronous B, the data transmission B and the data receiving B through a main processor B bus; the main processor B accesses the embedded USB flash disk B through a second special data communication line; the watchdog 2-1 and the ID recognition circuit 2-1 output monitoring result signals to the fault comprehensive monitoring 2-1; and the signal output end of the fault comprehensive monitoring 2-1 is connected with the main processor module A.
The double-double parallel architecture computer platform provided by the invention is also characterized in that the system I/O processor module A comprises a system I/O processor A, ID identification circuit 1-2, a watchdog 1-2, a system I/O output A, an output monitor A, a fault comprehensive monitor 1-2 and output signal connection control switches KA1 and KA2; the system I/O processor A is connected with the A computer communication circuit 1, the ID recognition circuit 1-2, the watchdog 1-2, the system I/O output A, the output monitoring A and the fault comprehensive monitoring 1-2 through a system I/O processor A bus; the ID recognition circuit 1-2, the watchdog 1-2, the internal power supply A monitor and the external power supply A monitor are connected with the fault comprehensive monitor 1-2 through output indication signals; the output signals of the fault comprehensive monitoring devices 1-2 are connected with control switches KA1 and KA2; the system I/O output A outputs signals, KA1 switch output signals and KA2 switch output signals which are connected with the output monitoring A; the fault comprehensive monitoring 1-2 outputs an indication signal to be connected with the system I/O processor module A; and B, comprehensively monitoring the ID input faults of the computer by 1-2.
The double-double parallel architecture computer platform provided by the invention is also characterized in that the system I/O processor module B comprises a system I/O processor B, ID identification circuit 2-2, a watchdog 2-2, a system I/O output B, an output monitor B, a fault comprehensive monitor 2-2 and output signal connection control switches KB1 and KB2; the system I/O processor B is connected with the computer communication circuit 2, the ID recognition circuit 2-2, the watchdog 2-2, the system I/O output B, the output monitoring B and the fault comprehensive monitoring 2-2 through a system I/O processor B bus; the ID recognition circuit 2-2, the watchdog 2-2, the internal power supply B monitor and the external power supply B monitor are connected with the fault comprehensive monitor 2-2 through output indication signals; the output signal of the fault comprehensive monitoring 2-2 is connected with control switches KB1 and KB2; the system I/O output B outputs signals, KB1 switch output signals and KB2 switch output signals which are connected with the output monitoring B; the fault comprehensive monitoring 2-2 outputs an indication signal to be connected with the system I/O processor module A; and B, comprehensively monitoring the ID input faults of the computer by 2-2.
The double-double parallel architecture computer platform provided by the invention also has the characteristics that the A computer is also provided with a safety indication circuit, an A computer and a B computer communication circuit, and is used for being connected with the B computer; the computer B is provided with a safety indication receiving circuit which is used for being connected with the computer A and feeding back the result to the safety indication circuit.
Compared with the prior art, the beneficial effect of this application:
the double-double parallel architecture computer platform provided by the invention connects the double-computer serial safety structure and the double-computer networking structure in parallel to form a novel double-double parallel fault-tolerant reliability structure, the theoretical reliability MTBF value is more than 1.625 times of that of a single computer, and a synchronous indication circuit is not arranged between the A computer and the B computer, so that the running independence of the A computer and the B computer is improved, and the cable interconnection between the double computers is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the present invention, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a reliability block diagram of a dual parallel architecture computer platform provided by the present invention;
FIG. 2 is a block diagram of a dual parallel architecture computer platform provided by the present invention;
FIG. 3 is a reliability block diagram of a classical parallel system of the prior art;
FIG. 4 is a prior art series system reliability block diagram;
FIG. 5 is a reliability block diagram of a prior art serial-parallel architecture;
fig. 6 is a reliability block diagram of a prior art meshing structure.
Detailed Description
In order to make the technical means, the creation characteristics, the achievement of the purposes and the effects of the implementation of the present invention easy to understand, the following embodiments are specifically described with reference to the accompanying drawings for a dual parallel architecture computer platform provided by the present invention.
In the description of the embodiments of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the drawings, are merely for convenience in describing the present invention and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the invention.
Furthermore, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
The terms "mounted," "connected," "coupled," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the creation of the present invention can be understood by those of ordinary skill in the art in a specific case.
1-2, embodiments of the present invention provide a dual parallel architecture computer platform comprising an A computer and a B computer having different structures; the computer A integrates an incompletely symmetrical monitoring channel and a control channel of a reliability serial structure; integrating a fault-tolerant computer with a reliability grid structure in the computer B; the control output priority of the computer A is higher than that of the computer B; the B computer comprises a hot backup control computer. The safe structure with double machines connected in series and the double machine grid structure are connected in parallel to form a novel double-parallel fault-tolerant system structure, and the theoretical reliability MTBF value of the novel double-parallel fault-tolerant system structure is more than 1.625 times of that of a single machine.
In some embodiments, the supervisory channel includes a first processor, a first input signal circuit, a first channel cross-link, a first synchronization circuit, a first supervisory circuit, a first watchdog, a first internal power supply, a first on/off logic circuit, a control channel ID, a signal output circuit, a first signal delivery switch KA1, a second signal output switch KA2, and an on delay circuit; the control channel comprises a second processor, a second input signal circuit, a second channel cross link, a second synchronous circuit, a second monitoring circuit, a second watchdog, a second internal power supply, a second on/off logic circuit, a monitoring channel ID, a weight release delay circuit, a safety indication circuit, an A computer and a B computer communication circuit.
In some embodiments, a bi-directional direct communication path is provided between the first input signal circuit and the second input signal circuit; the first processor circuit and the second processor circuit realize two-way communication through a first channel cross link, a first synchronous circuit, a second channel cross link and a second synchronous circuit; an interconnection between the first on/off logic circuit and the second on/off logic circuit to enable bi-directional status indication; the control channel ID is input into a first on/off logic circuit as a priority identification signal; the monitoring channel ID is used as a priority identification signal to be input into a second channel/fault logic circuit; the a computer ID is input into both the first on/off logic circuit and the second channel/off logic circuit.
In some embodiments, the first signal transmission switch KA1 and the second signal output switch KA2 are disposed in series; the first signal output switch KA1 is controlled by a control signal output by the first on/off logic circuit; the second signal output switch KA2 is controlled by a control signal output by the second on/off logic circuit; the output ends of the first signal output switch KA1 and the second signal output switch KA2 are subjected to wrapping monitoring through a control channel and a monitoring channel.
In some embodiments, the B computer includes a main processor module a, a main processor module B, a system I/O processor module a, and a system I/O processor module B, where the main processor module a is connected to the system I/O processor module a through a dual-port memory a-M, and is connected to the system I/O processor module B through a dual-port memory B-M; the main processor module B is connected with the system I/O processor module A through a double-port memory A-S, and is connected with the system I/O processor module B through a double-port memory B-S, and the system I/O processor module A and the system I/O processor module B are connected with the computer A.
In some embodiments, the main processor module a includes a main processor a, a main processor a bus, and a first dedicated data communication line; the main processor A is connected with the watchdog 1-1, the ID recognition circuit 1-1, the synchronous A, the data transmission A, the data receiving A, the dual-port memory A-M and the dual-port memory B-M through a main processor A bus; the main processor A accesses the embedded USB flash disk A through a first special data communication line; the watchdog 1-1 and the monitoring result signal output by the ID recognition circuit 1-1 are transmitted to the fault comprehensive monitoring 1-1; and the signal output end of the fault comprehensive monitoring 1-1 is connected with the main processor module B.
In some embodiments, the main processor module B includes a main processor B, a main processor B bus, and a second dedicated data communication line; the main processor B is connected with the watchdog 2-1, the ID recognition circuit 2-1, the synchronous B, the data transmission B and the data receiving B through a main processor B bus; the main processor B accesses the embedded USB flash disk B through a second special data communication line; the watchdog 2-1 and the ID recognition circuit 2-1 output monitoring result signals to the fault comprehensive monitoring 2-1; and the signal output end of the fault comprehensive monitoring 2-1 is connected with the main processor module A.
In some embodiments, the system I/O processor module A includes a system I/O processor A, ID identification circuit 1-2, a watchdog 1-2, a system I/O output A, an output monitor A, a fault integrated monitor 1-2, and output signal connection control switches KA1, KA2; the system I/O processor A is connected with the A computer communication circuit 1, the ID recognition circuit 1-2, the watchdog 1-2, the system I/O output A, the output monitoring A and the fault comprehensive monitoring 1-2 through a system I/O processor A bus; the ID recognition circuit 1-2, the watchdog 1-2, the internal power supply A monitor and the external power supply A monitor are connected with the fault comprehensive monitor 1-2 through output indication signals; the output signals of the fault comprehensive monitoring devices 1-2 are connected with control switches KA1 and KA2; the system I/O output A outputs signals, KA1 switch output signals and KA2 switch output signals which are connected with the output monitoring A; the fault comprehensive monitoring 1-2 outputs an indication signal to be connected with the system I/O processor module A; and B, comprehensively monitoring the ID input faults of the computer by 1-2.
In some embodiments, the system I/O processor module B includes a system I/O processor B, ID identification circuit 2-2, a watchdog 2-2, a system I/O output B, an output monitor B, a fault integrated monitor 2-2, and output signal connection control switches KB1, KB2; the system I/O processor B is connected with the computer communication circuit 2, the ID recognition circuit 2-2, the watchdog 2-2, the system I/O output B, the output monitoring B and the fault comprehensive monitoring 2-2 through a system I/O processor B bus;
the ID recognition circuit 2-2, the watchdog 2-2, the internal power supply B monitor and the external power supply B monitor are connected with the fault comprehensive monitor 2-2 through output indication signals; the output signal of the fault comprehensive monitoring 2-2 is connected with control switches KB1 and KB2; the system I/O output B outputs signals, KB1 switch output signals and KB2 switch output signals which are connected with the output monitoring B; the fault comprehensive monitoring 2-2 outputs an indication signal to be connected with the system I/O processor module A; and B, comprehensively monitoring the ID input faults of the computer by 2-2.
In some embodiments, the computer a is further provided with a security indication circuit and communication circuits of the computer a and the computer B, and the communication circuits are used for being connected with the computer B; the computer B is provided with a safety indication receiving circuit which is used for being connected with the computer A and feeding back the result to the safety indication circuit.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention. The foregoing is merely a preferred embodiment of the present invention, and it should be noted that it will be apparent to those skilled in the art that modifications and variations can be made without departing from the technical principles of the present invention, and these modifications and variations should also be regarded as the scope of the invention.
Claims (8)
1. A dual double parallel architecture computer platform, the platform comprising a first computer and a second computer having different structures;
the first computer is internally integrated with an incompletely symmetrical monitoring channel and a control channel of a reliability serial structure;
integrating a fault-tolerant computer with a reliability grid structure in the second computer;
the first computer controls the output priority to be larger than that of the second computer;
the second computer comprises a hot-standby control computer,
the monitoring channel comprises a first processor, a first input signal circuit, a first channel cross link, a first synchronous circuit, a first monitoring circuit, a first watchdog, a first internal power supply, a first on/off logic circuit, a control channel ID, a signal output circuit, a first signal transmission switch KA1, a second signal output switch KA2 and an on delay circuit;
the control channel comprises a second processor, a second input signal circuit, a second channel cross link, a second synchronous circuit, a second monitoring circuit, a second watchdog, a second internal power supply, a second on/off logic circuit, a monitoring channel ID, a time-delay release circuit, a safety indication circuit, a first computer and a second computer communication circuit,
a bidirectional direct communication path is arranged between the first input signal circuit and the second input signal circuit;
the first processor circuit and the second processor circuit realize two-way communication through a first channel cross link, a first synchronous circuit, a second channel cross link and a second synchronous circuit;
an interconnection between the first on/off logic circuit and the second on/off logic circuit to enable bi-directional status indication;
the control channel ID is input into a first on/off logic circuit as a priority identification signal;
the monitoring channel ID is used as a priority identification signal to be input into a second channel/fault logic circuit;
the first computer ID is input with both the first on/off logic circuit and the second channel/off logic circuit.
2. The dual parallel architecture computer platform of claim 1, wherein,
the first signal transmission switch KA1 and the second signal output switch KA2 are arranged in series;
the first signal transmission switch KA1 is controlled by a control signal output by the first on/off logic circuit;
the second signal output switch KA2 is controlled by a control signal output by the second on/off logic circuit;
the output ends of the first signal transmission switch KA1 and the second signal output switch KA2 are subjected to wrapping monitoring through a control channel and a monitoring channel.
3. The dual parallel architecture computer platform of claim 1, wherein,
the second computer includes a first main processor module, a second main processor module, a first system I/O processor module, and a second system I/O processor module,
the first main processor module is connected with the first system I/O processor module through a first dual-port memory and is connected with the second system I/O processor module through a second dual-port memory;
the second main processor module is connected with the first system I/O processor module through a third dual-port memory and is connected with the second system I/O processor module through a fourth dual-port memory;
the first system I/O processor module and the second system I/O processor module are connected with the first computer.
4. The dual parallel architecture computer platform of claim 3,
the first main processor module comprises a first main processor, a first main processor bus and a first special data communication line;
the first main processor is connected with a third watchdog, a first ID identification circuit, a first synchronization circuit, a first data transmission circuit, a first data receiving circuit, the first dual-port memory and the second dual-port memory through a first main processor bus;
the first main processor accesses the embedded first U disk through a first special data communication line;
the monitoring result signals output by the third watchdog and the first ID recognition circuit are transmitted to the first fault comprehensive monitoring;
and the signal output end of the first fault comprehensive monitoring is connected with the second main processor module.
5. The dual parallel architecture computer platform of claim 3,
the second main processor module comprises a second main processor, a second main processor bus and a second special data communication line;
the second main processor is connected with the fourth watchdog, the second ID recognition circuit, the second synchronization, the second data transmission and the second data receiving through a second main processor bus;
the second main processor accesses the embedded second U disk through a second special data communication line;
the monitoring result signals output by the fourth watchdog and the second ID recognition circuit are transmitted to a second fault comprehensive monitor;
and the signal output end of the second fault comprehensive monitoring is connected with the first main processor module.
6. The dual parallel architecture computer platform of claim 3,
the first system I/O processor module comprises a first system I/O processor, a third ID recognition circuit, a fifth watchdog, a first system I/O output, a first output monitor, a third fault comprehensive monitor, a first signal transmission switch KA1 and a second signal output switch KA2;
the output signal of the third fault comprehensive monitoring is transmitted to a first signal transmission switch KA1 and a second signal output switch KA2;
the first system I/O processor is connected with a first communication circuit, a third ID identification circuit, a fifth watchdog, a first system I/O output, a first output monitor and a third fault comprehensive monitor of the first computer through a first system I/O processor bus;
the output indication signal of the third ID identification circuit, the fifth watchdog, the first internal power supply monitoring and the first external power supply monitoring is connected with the third fault comprehensive monitoring;
the I/O output signal of the first system, the output signal of the first signal transmission switch KA1 switch and the output signal of the second signal output switch KA2 switch are connected with a first output monitor;
the third fault comprehensive monitoring output indication signal is connected with the first system I/O processor module;
the second computer ID is input to the third fault integrated monitoring.
7. The dual parallel architecture computer platform of claim 3,
the second system I/O processor module comprises a second system I/O processor, a fourth ID recognition circuit, a sixth watchdog, a second system I/O output, a second output monitor, a fourth fault comprehensive monitor, a third signal transmission switch KB1 and a fourth signal output switch KB2;
the output signal of the fourth fault comprehensive monitoring is transmitted to a third signal transmission switch KB1 and a fourth signal output switch KB2;
the second system I/O processor is connected with the first computer through a second system I/O processor bus and is connected with the second communication circuit, the fourth ID recognition circuit, the sixth watchdog, the second system I/O output, the second output monitoring and the fourth fault comprehensive monitoring;
the output indication signal of the fourth ID identification circuit, the sixth watchdog, the second internal power supply monitor and the second external power supply monitor is connected with the fourth fault comprehensive monitor;
the I/O output signal of the second system, the switch output signal of the third signal transmission switch KB1 and the switch output signal of the fourth signal transmission switch KB2 are connected with a second output monitor;
the fourth fault comprehensive monitoring output indication signal is connected with the first system I/O processor module;
the second computer ID is input to the fourth fault integrated monitoring.
8. The dual parallel architecture computer platform of claim 1, wherein,
the first computer is also provided with a safety indication circuit, a first computer and a second computer communication circuit, and is used for being connected with the second computer;
the second computer is provided with a safety indication receiving circuit which is used for being connected with the first computer and feeding back the result to the safety indication circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111052058.7A CN113868077B (en) | 2021-09-08 | 2021-09-08 | Double-double parallel architecture computer platform |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111052058.7A CN113868077B (en) | 2021-09-08 | 2021-09-08 | Double-double parallel architecture computer platform |
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| EP0588414A1 (en) * | 1992-09-16 | 1994-03-23 | International Business Machines Corporation | Method and apparatus for redundant cooling of electronic devices |
| CN102053882A (en) * | 2011-01-11 | 2011-05-11 | 北京航空航天大学 | Heterogeneous satellite-borne fault-tolerant computer based on COTS (Commercial Off The Shelf) device |
| CN111352338A (en) * | 2018-12-20 | 2020-06-30 | 海鹰航空通用装备有限责任公司 | Dual-redundancy flight control computer and redundancy management method |
| CN112241352A (en) * | 2020-11-03 | 2021-01-19 | 中国航空工业集团公司西安航空计算技术研究所 | Monitoring system of gridding fault-tolerant computer platform |
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| EP0588414A1 (en) * | 1992-09-16 | 1994-03-23 | International Business Machines Corporation | Method and apparatus for redundant cooling of electronic devices |
| US5438226A (en) * | 1992-09-16 | 1995-08-01 | International Business Machines Corporation | Apparatus for redundant cooling of electronic devices |
| CN102053882A (en) * | 2011-01-11 | 2011-05-11 | 北京航空航天大学 | Heterogeneous satellite-borne fault-tolerant computer based on COTS (Commercial Off The Shelf) device |
| CN111352338A (en) * | 2018-12-20 | 2020-06-30 | 海鹰航空通用装备有限责任公司 | Dual-redundancy flight control computer and redundancy management method |
| CN112241352A (en) * | 2020-11-03 | 2021-01-19 | 中国航空工业集团公司西安航空计算技术研究所 | Monitoring system of gridding fault-tolerant computer platform |
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