CN113866613A - Test structure for Hall effect test and preparation method thereof - Google Patents

Test structure for Hall effect test and preparation method thereof Download PDF

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Publication number
CN113866613A
CN113866613A CN202111447251.0A CN202111447251A CN113866613A CN 113866613 A CN113866613 A CN 113866613A CN 202111447251 A CN202111447251 A CN 202111447251A CN 113866613 A CN113866613 A CN 113866613A
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layer
test
contact semiconductor
hall effect
substrate layer
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CN113866613B (en
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程洋
陈湘榴
王俊
周大勇
庞磊
李泉灵
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Suzhou Everbright Photonics Co Ltd
Gusu Laboratory of Materials
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Suzhou Everbright Photonics Co Ltd
Gusu Laboratory of Materials
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R3/00—Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00—Hall-effect devices
    • H10N52/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00—Hall-effect devices
    • H10N52/101—Semiconductor Hall-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00—Hall-effect devices
    • H10N52/80—Constructional details

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Hall/Mr Elements (AREA)

Abstract

The invention provides a test structure for Hall effect test and a preparation method thereof, wherein the test structure comprises the following components: a substrate layer; a test epitaxial layer on the substrate layer; the contact semiconductor layers are positioned on the surface of one side, back to the substrate layer, of the test epitaxial layer and are spaced, and doped ions are arranged in the contact semiconductor layers; and the test electrode is positioned on one side surface of part of the contact semiconductor layer, which faces away from the test epitaxial layer. The contact semiconductor layer forms ohmic contact more easily, is favorable to the injection current, transversely does not switch on between the adjacent contact semiconductor layer, can not cause the test epitaxial layer by the contact semiconductor layer short circuit, guarantees that the circuit path can satisfy hall effect test, and the condition of exhausting among the contact semiconductor layer can not cause the influence to the test epitaxial layer of below to test structure's test sensitivity has been improved.

Description

Test structure for Hall effect test and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a test structure for Hall effect testing and a preparation method thereof.
Background
The wavelength range of the quantum cascade laser can cover most of the wave bands of 3-30 mu m, and the quantum cascade laser is an ideal semiconductor laser light source for infrared and terahertz wave bands. The quantum cascade laser of the intermediate infrared adopts InGaAs/InAlAs superlattice as an active region, and the performance of the quantum cascade laser is influenced by the background carrier concentration and the carrier mobility of InGaAs and InAlAs materials. In order to test two parameters of background carrier concentration and carrier mobility of an active region, a wafer of a corresponding sample needs to be grown, and accurate Hall (Hall) effect test is carried out.
The conventional method has two problems that the quality of a wafer for Hall effect test is difficult to ensure, and defects are easy to appear on the surface, in particular to the test wafer of InAlAs; and secondly, the manufacturing and testing of the test wafer have problems, the contact between the surface of the test wafer and an electrode is difficult to manufacture, the epitaxial layer of the test wafer is easy to be exhausted, the electric leakage is easy to occur in the testing process, and the like.
In sum, the test sensitivity of the test wafer is reduced.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the problem of low test sensitivity of the test structure for hall effect test in the prior art, so as to provide a test structure for hall effect test and a preparation method thereof.
The invention provides a test structure for Hall effect test, comprising: a substrate layer; a test epitaxial layer on the substrate layer; the contact semiconductor layers are positioned on the surface of one side, back to the substrate layer, of the test epitaxial layer and are spaced, and doped ions are arranged in the contact semiconductor layers; and the test electrode is positioned on one side surface of part of the contact semiconductor layer, which faces away from the test epitaxial layer.
Optionally, the doping concentration of the doping ions in the contact semiconductor layer is 1e18atom/cm3～1e20atom/cm3。
Optionally, the doping ions include Si ions, C ions, Mg ions, Sn ions, or Zn ions.
Optionally, a projection shape of each of the contact semiconductor layers on the surface of the substrate layer includes a circle, an ellipse, or a polygon.
Optionally, the projection area of the plurality of spaced contact semiconductor layers on the surface of the substrate layer is 40% to 90% of the projection area of the test epitaxial layer on the surface of the substrate layer.
Optionally, the thickness of the contact semiconductor layer is 3nm to 20 nm.
Optionally, the plurality of spaced contact semiconductor layers are arranged in an array.
Optionally, the plurality of spaced contact semiconductor layers are uniformly distributed, the distance between adjacent contact semiconductor layers is 10 μm to 1000 μm, and the width of each contact semiconductor layer is 10 μm to 1000 μm.
Optionally, the material of the test epitaxial layer includes inaias; the material of the contact semiconductor layer is InGaAs with doped ions.
Optionally, the method further includes: a first buffer layer on a surface of the substrate layer; the second buffer layer is positioned on the surface of one side, opposite to the substrate layer, of the first buffer layer; the test epitaxial layer is positioned on the surface of one side, back to the substrate layer, of the second buffer layer.
Optionally, the first buffer layer comprises an InP buffer layer; the second buffer layer comprises an InGaAs buffer layer.
Optionally, the substrate layer comprises Fe-doped InP.
The invention also provides a preparation method of the test structure for the Hall effect test, which comprises the following steps: providing a substrate layer; forming a test epitaxial layer on the substrate layer; forming a plurality of contact semiconductor layers at intervals on the surface of one side, back to the substrate layer, of the test epitaxial layer, wherein the contact semiconductor layers are provided with doped ions; and forming a test electrode on one side surface of part of the contact semiconductor layer, which faces away from the test epitaxial layer.
Optionally, the step of forming the contact semiconductor layer includes: forming an initial contact semiconductor layer on the surface of one side, back to the substrate layer, of the test epitaxial layer; and etching and removing part of the initial contact semiconductor layer to form a contact semiconductor layer.
Optionally, a wet etching process is used to remove part of the initial contact semiconductor layer by etching, and the parameters of the wet etching process include: by the inclusion of H3PO3And H2O2The etching solution of (3).
Optionally, the method further includes: before the test epitaxial layer is formed, carrying out dry etching treatment on the surface of the substrate layer, wherein the gas adopted in the dry etching treatment comprises CBr4The temperature adopted by the dry etching treatment is 550-750 ℃.
Optionally, the method further includes: after the surface of the substrate layer is subjected to dry etching treatment and before the test epitaxial layer is formed, forming a first buffer layer on the surface of the substrate layer; and forming a second buffer layer on the surface of one side, opposite to the substrate layer, of the first buffer layer.
Optionally, the first buffer layer comprises an InP buffer layer; the second buffer layer comprises an InGaAs buffer layer.
Optionally, the projection area of the contact semiconductor layer on the surface of the substrate layer is 40% to 90% of the projection area of the test epitaxial layer on the surface of the substrate layer.
The technical scheme of the invention has the following beneficial effects:
1. according to the test structure for the Hall effect test, the contact semiconductor layer is arranged, and the doped ions are arranged in the contact semiconductor layer, so that the contact potential barrier between the test electrode and the surface of the test epitaxial layer can be reduced, ohmic contact can be formed more easily, and current injection is facilitated. The contact semiconductor layers are mutually spaced, and adjacent contact semiconductor layers are not transversely conducted, so that the test epitaxial layer is not short-circuited by the contact semiconductor layers, and the circuit path can meet the Hall effect test. The large part area of the surface of the test epitaxial layer is covered by the contact semiconductor layer, the contact area of the test epitaxial layer and air is small, and the condition that the energy band in the test epitaxial layer is bent to cause carrier depletion is reduced. Because the contact semiconductor layer is provided with the doped ions, the conductivity of the contact semiconductor layer is larger than that of the test epitaxial layer, and the depletion layer on the surface, which is in contact with air, of the contact semiconductor layer is thinner, so that most of the conditions of carrier depletion caused by the bending of an energy band inside the semiconductor layer due to the contact with the air are generated in the contact semiconductor layer, and the depletion condition in the contact semiconductor layer can not influence the test epitaxial layer below, thereby improving the test sensitivity of the test structure.
2. Further, the doping concentration of the dopant ion in the contact semiconductor layer is 1e18atom/cm3～1e20atom/cm3The contact semiconductor layer is heavily doped, so that the contact barrier between the test electrode and the surface of the test epitaxial layer can be further reduced, and ohmic contact can be more easily formed.
3. Further, the first buffer layer includes an InP buffer layer; the second buffer layer comprises an InGaAs buffer layer; the material composition of the first buffer layer is closer to the substrate layer, the material composition of the second buffer layer is closer to the test epitaxial layer, and the film quality of the test epitaxial layer can be improved through the transition of the first buffer layer and the second buffer layer.
4. According to the preparation method of the test structure for the Hall effect test, the contact semiconductor layer is arranged, and the doped ions are arranged in the contact semiconductor layer, so that the contact potential barrier between the test electrode and the surface of the test epitaxial layer can be reduced, ohmic contact can be formed more easily, and the injection of current is facilitated. The contact semiconductor layers are mutually spaced, adjacent contact semiconductor layers are not transversely conducted, the test epitaxial layer is not short-circuited by the contact semiconductor layers, and the circuit path can meet the Hall effect test. The large part area of the surface of the test epitaxial layer is covered by the contact semiconductor layer, the contact area of the test epitaxial layer and air is small, and the condition that the energy band in the test epitaxial layer is bent to cause carrier depletion is reduced. Because the contact semiconductor layer is provided with the doped ions, the conductivity of the contact semiconductor layer is larger than that of the test epitaxial layer, and the depletion layer on the surface, which is in contact with air, of the contact semiconductor layer is thinner, so that most of the conditions of carrier depletion caused by the bending of an energy band inside the semiconductor layer due to the contact with the air are generated in the contact semiconductor layer, and the depletion condition in the contact semiconductor layer can not influence the test epitaxial layer below, thereby improving the test sensitivity of the test structure.
5. Further, before the test epitaxial layer is formed, dry etching treatment is carried out on the surface of the substrate layer, partial materials on the surface of the substrate layer are removed, and a relatively pure substrate layer surface can be obtained.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic cross-sectional structural view of the test structure for Hall effect testing shown in FIG. 2, cut along the direction A-A;
FIG. 2 is a schematic top view of a test structure for Hall effect testing according to an embodiment of the present invention;
FIG. 3 is a flow chart of a method for fabricating a test structure for Hall effect testing according to an embodiment of the present invention;
fig. 4 to 8 are schematic structural diagrams illustrating a manufacturing process of a test structure for a hall effect test according to an embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
An embodiment of the present invention provides a test structure for hall effect test, referring to fig. 1 and 2, including:
a substrate layer 1;
a test epitaxial layer 2 positioned on the substrate layer 1;
the contact semiconductor layers 3 are positioned on the surface of one side, back to the substrate layer 1, of the test epitaxial layer 2 and are spaced, and doped ions are arranged in the contact semiconductor layers 3;
and the test electrode 4 is positioned on one side surface of part of the contact semiconductor layer 3, which faces away from the test epitaxial layer 2.
Because the contact semiconductor layer 3 is arranged and the doped ions are arranged in the contact semiconductor layer 3, the contact potential barrier between the test electrode 4 and the surface of the test epitaxial layer 2 can be reduced, so that ohmic contact is more easily formed, and the injection of current is facilitated. The contact semiconductor layers 3 are mutually spaced, and the adjacent contact semiconductor layers 3 are not transversely conducted, so that the test epitaxial layer 2 is not short-circuited by the contact semiconductor layers 3, and the circuit path can meet the Hall effect test. Most of the surface area of the test epitaxial layer 2 is covered by the contact semiconductor layer 3, the area of the test epitaxial layer 2 in contact with air is small, and the condition that the carrier is depleted due to the energy band bending inside the test epitaxial layer 2 is reduced. Because the contact semiconductor layer 3 is provided with the doped ions, the conductivity of the contact semiconductor layer 3 is larger than that of the test epitaxial layer 2, and the depletion layer on the surface of the contact semiconductor layer 3 contacted with air is thinner, so that most of the conditions of carrier depletion caused by the bending of an internal energy band of the semiconductor contacted with air are generated in the contact semiconductor layer 3, and the depletion condition in the contact semiconductor layer 3 can not influence the test epitaxial layer 2 below, thereby improving the test sensitivity of the test structure.
In one embodiment, the doping concentration of the dopant ions in the contact semiconductor layer 3 is 1e18atom/cm3～1e20atom/cm3E.g. 1e18atom/cm3、1e19atom/cm3Or 1e20atom/cm3. The contact semiconductor layer 3 is heavily doped to further reduce the contact barrier of the test electrode 4 with the surface of the test epitaxial layer 2, thereby making it easier to form ohmic contact.
The doping ions include Si ions, C ions, Mg ions, Sn ions or Zn ions.
The projection shape of each contact semiconductor layer 3 on the surface of the substrate layer 1 comprises a circle, an ellipse or a polygon. In this embodiment, the projection shape of the contact semiconductor layer 3 on the surface of the substrate layer 1 is a circle.
A plurality of spaced contact semiconductor layers 3 are arranged in an array.
The contact semiconductor layers 3 are uniformly distributed at intervals, in a specific embodiment, the distance between adjacent contact semiconductor layers 3 is 10 μm to 1000 μm, for example, 10 μm, 100 μm, 500 μm, 800 μm or 1000 μm, and the width of each contact semiconductor layer 3 is 10 μm to 1000 μm, for example, 10 μm, 100 μm, 500 μm, 800 μm or 1000 μm. The width of the contact semiconductor layer 3 in the width interval can meet the manufacturing and testing requirements, and if the width is too small, the precision requirement for photoetching and etching for manufacturing the contact semiconductor layer 3 is high, so that the yield is influenced; if the width is too large, the number of contact semiconductor layers 3 may be insufficient, and there may be no appropriate island-shaped contact semiconductor layer 3 under the test electrode 4.
In one embodiment, the contact semiconductor layer 3 has a thickness of 3nm to 20nm, for example, 3nm, 5nm, 10nm, 15nm, or 20 nm. The contact semiconductor layer 3 should not be too thick, otherwise extra ions may diffuse into the test epitaxial layer 2 below during the growth process, and the source material is wasted; the contact semiconductor layer 3 is also preferably not too thin, and its thickness must be larger than the width of the depletion layer to facilitate the formation of an effective ohmic contact.
In one embodiment, the projected area of the contact semiconductor layer 3 on the surface of the substrate layer 1 is 40% to 90%, for example, 40%, 60%, 70% or 90% of the projected area of the test epitaxial layer 2 on the surface of the substrate layer 1. If the projected area is large, the more difficult the photoetching and etching process for forming the contact semiconductor layer 3 is; if the projected area is small, the depletion layer contacting the surface of the semiconductor layer 3 cannot be effectively reduced.
The material of the test epitaxial layer 2 comprises InAlAs; the material of the contact semiconductor layer 3 is InGaAs with doped ions.
In one embodiment, the test epitaxial layer 2 has a thickness of 4 μm to 6 μm, for example 5 μm. In other embodiments, the thickness of the test epitaxial layer 2 may be selected from other thickness ranges without limitation.
The substrate layer 1 comprises InP doped with Fe. The substrate layer 1 is a semi-insulating substrate. At one endIn one embodiment, the substrate layer 1 has a resistivity of 105Ω˙cm～109Ω & cm, e.g. 105Ω˙cm、106Ω˙cm、107Ω˙cm、108Ω & cm or 109Ω˙cm。
In this embodiment, InP is doped with Fe, so that the substrate layer 1 is semi-insulating. So that no current will be conducted in the substrate layer during the test.
In this embodiment, the test structure further includes: a first buffer layer 5 on the surface of the substrate layer 1; a second buffer layer 6 positioned on the surface of one side, opposite to the substrate layer 1, of the first buffer layer 5; the test epitaxial layer 2 is positioned on one side of the second buffer layer 6, which faces away from the substrate layer 1.
The first buffer layer 5 includes an InP buffer layer; the second buffer layer 6 comprises an InGaAs buffer layer. The material composition of the first buffer layer 5 is closer to the substrate layer 1, the material composition of the second buffer layer 6 is closer to the test epitaxial layer 2, and the film quality of the test epitaxial layer 2 can be improved through the transition of the first buffer layer 5 and the second buffer layer 6.
In one embodiment, the first buffer layer 5 has a thickness of 5nm to 20nm, and the second buffer layer 6 has a thickness of 5nm to 20 nm.
In other embodiments, the test structure includes a single layer of the buffer layer.
In this embodiment, the test electrode 4 is made of indium particles with a hardness of 1.0, and the contact area of the test electrode 4 is 0.25mm2～4mm2. For example 0.25mm2、0.3mm2、0.35mm2Or 0.4mm2The test electrode 4 has a thickness of 0.02mm to 0.5mm, for example 0.02mm, 0.2mm, 0.4mm or 0.5 mm. The shape of the test electrode 4 comprises a cylinder.
Another embodiment of the present invention further provides a method for manufacturing a test structure for hall effect testing, referring to fig. 3, including:
s1, providing a substrate layer;
s2, forming a test epitaxial layer on the substrate layer;
s3, forming a plurality of contact semiconductor layers at intervals on the surface of one side, back to the substrate layer, of the test epitaxial layer, wherein the contact semiconductor layers are provided with doped ions;
and S4, forming a test electrode on one side surface of part of the contact semiconductor layer, which faces away from the test epitaxial layer.
The step of forming the contact semiconductor layer includes: forming an initial contact semiconductor layer on the surface of one side, back to the substrate layer, of the test epitaxial layer; and etching and removing part of the initial contact semiconductor layer to form a contact semiconductor layer.
In this embodiment, a wet etching process is used to etch and remove a part of the initial contact semiconductor layer, and the parameters of the wet etching process include: by the inclusion of H3PO3And H2O2The etching solution of (3).
The method of making a test structure further comprises: before the test epitaxial layer is formed, dry etching treatment is carried out on the surface of the substrate layer, partial materials on the surface of the substrate layer are removed, and a relatively pure substrate layer surface can be obtained. The gas adopted by the dry etching treatment comprises CBr4The temperature adopted by the dry etching treatment is 550-750 ℃.
The preparation method also comprises the following steps: after the surface of the substrate layer is subjected to dry etching treatment and before the test epitaxial layer is formed, forming a first buffer layer on the surface of the substrate layer; and forming a second buffer layer on the surface of one side, opposite to the substrate layer, of the first buffer layer.
The first buffer layer comprises an InP buffer layer; the second buffer layer comprises an InGaAs buffer layer.
The material composition of the first buffer layer is closer to the substrate layer, the material composition of the second buffer layer is closer to the test epitaxial layer, and the film quality of the test epitaxial layer can be improved through the transition of the first buffer layer and the second buffer layer.
Referring to fig. 4 to 8, the following will describe the preparation method of the test structure in detail with reference to the accompanying drawings:
referring to fig. 4, a substrate layer 1 is provided.
Substrate layer 1 may be a square Fe-doped InP semi-insulating substrate with a side length of 2 inches.
Referring to fig. 5, a first buffer layer 5 is formed on a side surface of the substrate layer 1; a second buffer layer 6 is formed on the surface of the first buffer layer 5 opposite to the substrate layer 1.
Specifically, the surface of the substrate layer 1 is subjected to dry etching treatment to remove part of the surface of the substrate layer 1 to obtain a pure surface, and the gas adopted in the dry etching treatment comprises CBr4The temperature used for the dry etching treatment is 550 ℃ to 750 ℃, for example, 550 ℃, 640 ℃ or 750 ℃, preferably 640 ℃.
The process of forming the first buffer layer 5 comprises a metal organic chemical vapor deposition process (MOCVD), and the parameters comprise: the gas used includes TMIn (trimethyl indium) and PH3The first buffer layer 5 includes an InP buffer layer having a thickness of 5nm to 20nm, for example, 5nm, 10nm, 15nm, or 20 nm.
The process for forming the second buffer layer 6 comprises an organometallic chemical vapor deposition process, and the parameters comprise: the gases used include TMIn (trimethyl indium), TMGa (trimethyl gallium) and AsH3. The second buffer layer 6 includes an InGaAs buffer layer having a thickness of 5nm to 20nm, for example, 5nm, 10nm, 15nm, or 20 nm.
Referring to fig. 6, a test epitaxial layer 2 is formed on a surface of the second buffer layer 6 opposite to the substrate layer 1.
The material of the test epitaxial layer 2 comprises InAlAs with a thickness of 4 μm to 6 μm, for example 4 μm, 5 μm or 6 μm, preferably 5 μm.
Referring to fig. 7, a plurality of spaced contact semiconductor layers 3 are formed on a surface of the test epitaxial layer 2 opposite to the substrate layer 1, and the contact semiconductor layers 3 have doped ions therein.
Specifically, an initial contact semiconductor layer is formed on the surface of one side, back to the substrate layer 1, of the test epitaxial layer 2, a wet etching process is adopted to etch and remove part of the initial contact semiconductor layer to form a plurality of contact semiconductor layers 3 at intervals, and the parameters of the wet etching process include: by the inclusion of H3PO3And H2O2Wherein the proportion of the corrosive liquid is H3PO4:H2O2:H2O =1:1:100 to 1:1:10, for example 1:1: 10.
The description of the contact semiconductor layer 3 refers to the foregoing and is not described in detail.
Referring to fig. 8, a test electrode 4 is formed on a surface of a portion of the contact semiconductor layer 3 opposite to the test epitaxial layer 2.
The indium metal particles are used as electrode material, and can be fixed on the surface by welding or pressure welding to form good contact with the surface with contact area of 0.25mm2～4mm2(e.g., 0.34 mm)2) A cylinder contact point having a thickness of 0.02mm to 0.5mm (e.g., 0.05 mm).
Finally, a hot plate is used for heating the test structure, the heating temperature is 400 ℃, the good ohmic contact between the test electrode 4 and the contact semiconductor layer 3 is favorably formed, and then the test structure is put into a solution with the ratio of HCl to H2O =1: 20 for a time of 0.5s to 1.5s, for example, 1s, to clean the In impurities remaining on the sidewalls of the test structure and keep the test structure free from interference from other factors, and finally, loading the test structure into a hall effect test apparatus and testing the background carrier concentration and mobility thereof using a van der bauer four-probe method.
Because the contact semiconductor layer 3 is arranged and the doped ions are arranged in the contact semiconductor layer 3, the contact potential barrier between the test electrode 4 and the surface of the test epitaxial layer 2 can be reduced, so that ohmic contact is more easily formed, and the injection of current is facilitated. The contact semiconductor layers 3 are mutually spaced, and the adjacent contact semiconductor layers 3 are not transversely conducted, so that the test epitaxial layer 2 is not short-circuited by the contact semiconductor layers 3, and the circuit path can meet the Hall effect test. Most of the surface area of the test epitaxial layer 2 is covered by the contact semiconductor layer 3, the area of the test epitaxial layer 2 in contact with air is small, and the condition that the carrier is depleted due to the energy band bending inside the test epitaxial layer 2 is reduced. Because the contact semiconductor layer 3 is provided with the doped ions, the conductivity of the contact semiconductor layer 3 is larger than that of the test epitaxial layer 2, and the depletion layer on the surface of the contact semiconductor layer 3 contacted with air is thinner, so that most of the conditions of carrier depletion caused by the bending of an internal energy band of the semiconductor contacted with air are generated in the contact semiconductor layer 3, and the depletion condition in the contact semiconductor layer 3 can not influence the test epitaxial layer 2 below, thereby improving the test sensitivity of the test structure.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.

Claims (19)

1. A test structure for hall effect testing, comprising:
a substrate layer;
a test epitaxial layer on the substrate layer;
the contact semiconductor layers are positioned on the surface of one side, back to the substrate layer, of the test epitaxial layer and are spaced, and doped ions are arranged in the contact semiconductor layers;
and the test electrode is positioned on one side surface of part of the contact semiconductor layer, which faces away from the test epitaxial layer.
2. Test structure for hall effect tests according to claim 1, characterized in that the doping concentration of said doping ions in said contact semiconductor layer is 1e18atom/cm3～1e20atom/cm3。
3. The test structure for hall effect testing of claim 1 or 2 wherein said dopant ions comprise Si ions, C ions, Mg ions, Sn ions or Zn ions.
4. The test structure for hall effect testing of claim 1 wherein the projected shape of each of said contacting semiconductor layers on the surface of said substrate layer comprises a circle, an ellipse or a polygon.
5. The test structure for hall effect testing of claim 1 wherein the projected area of said plurality of spaced apart contacting semiconductor layers on the surface of said substrate layer is 40% to 90% of the projected area of said test epitaxial layer on the surface of said substrate layer.
6. The test structure for hall effect testing of claim 1 wherein the thickness of the contacting semiconductor layer is between 3nm and 20 nm.
7. The test structure for hall effect testing of claim 1 wherein the plurality of spaced apart contacting semiconductor layers are arranged in an array.
8. The test structure for hall effect testing as claimed in claim 1 or 7 wherein a plurality of spaced contact semiconductor layers are uniformly distributed, the spacing between adjacent contact semiconductor layers is 10 μm to 1000 μm, and the width of each of said contact semiconductor layers is 10 μm to 1000 μm.
9. The test structure for hall effect testing of claim 1 wherein the material of said test epitaxial layer comprises inaias; the material of the contact semiconductor layer is InGaAs with doped ions.
10. The test structure for hall effect testing of claim 1 further comprising: a first buffer layer on a surface of the substrate layer; the second buffer layer is positioned on the surface of one side, opposite to the substrate layer, of the first buffer layer;
the test epitaxial layer is positioned on the surface of one side, back to the substrate layer, of the second buffer layer.
11. The test structure for hall effect testing of claim 10 wherein said first buffer layer comprises an InP buffer layer; the second buffer layer comprises an InGaAs buffer layer.
12. The test structure for hall effect testing of claim 1 wherein said substrate layer comprises Fe-doped InP.
13. A method for preparing a test structure for Hall effect testing, comprising:
providing a substrate layer;
forming a test epitaxial layer on the substrate layer;
forming a plurality of contact semiconductor layers at intervals on the surface of one side, back to the substrate layer, of the test epitaxial layer, wherein the contact semiconductor layers are provided with doped ions;
and forming a test electrode on one side surface of part of the contact semiconductor layer, which faces away from the test epitaxial layer.
14. The method of claim 13, wherein the step of forming the contact semiconductor layer comprises: forming an initial contact semiconductor layer on the surface of one side, back to the substrate layer, of the test epitaxial layer; and etching and removing part of the initial contact semiconductor layer to form a contact semiconductor layer.
15. The method of claim 14, wherein the step of removing the portion of the initial contact semiconductor layer is performed by a wet etching process, and the parameters of the wet etching process include: by the inclusion of H3PO3And H2O2The etching solution of (3).
16. Use according to claim 13 for hall effect measurementsA method of preparing a test structure, comprising: before the test epitaxial layer is formed, carrying out dry etching treatment on the surface of the substrate layer, wherein the gas adopted in the dry etching treatment comprises CBr4The temperature adopted by the dry etching treatment is 550-750 ℃.
17. The method of making a test structure for hall effect testing as recited in claim 16, further comprising: after the surface of the substrate layer is subjected to dry etching treatment and before the test epitaxial layer is formed, forming a first buffer layer on the surface of the substrate layer; and forming a second buffer layer on the surface of one side, opposite to the substrate layer, of the first buffer layer.
18. The method of fabricating a test structure for hall effect testing of claim 17 wherein said first buffer layer comprises an InP buffer layer; the second buffer layer comprises an InGaAs buffer layer.
19. The method of claim 13, wherein the projected area of the contact semiconductor layer on the surface of the substrate layer is 40-90% of the projected area of the test epitaxial layer on the surface of the substrate layer.
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