CN113866484A - Power tube circuit integrated with sampling resistor - Google Patents
Power tube circuit integrated with sampling resistor Download PDFInfo
- Publication number
- CN113866484A CN113866484A CN202111220865.5A CN202111220865A CN113866484A CN 113866484 A CN113866484 A CN 113866484A CN 202111220865 A CN202111220865 A CN 202111220865A CN 113866484 A CN113866484 A CN 113866484A
- Authority
- CN
- China
- Prior art keywords
- sampling
- power tube
- resistor
- circuit
- tube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
Abstract
The invention relates to the technical field of power tube circuits, and discloses a power tube circuit integrated with a sampling resistor, which comprises an IC chip, wherein a main power tube and a secondary power tube are integrated on the IC chip, the main power tube is connected with the secondary power tube in parallel, the main power tube is connected with a source electrode drain electrode in a top aluminum metal through-laid mode, the secondary power tube is connected with the source electrode in a top aluminum metal through-laid mode, the drain electrode is connected in a top aluminum metal through-laid mode, the aluminum metal routing parasitic resistor is the sampling resistor, and two ends of the metal routing resistor are resistor sampling ends. The sampling resistor is arranged in the chip, and the parasitic resistor on the wiring of the lower tube of the power tube is used as the sampling current resistor by utilizing the characteristics of the power tube of the switching power supply, so that the current can be accurately sampled, the condition of reverse current can be responded, the accurate sampling with high efficiency and wide range and basically no reduction of loss is realized on the basis of not increasing additional elements and circuits, the cost is saved, and the efficiency is improved.
Description
Technical Field
The invention relates to the technical field of power tube circuits, in particular to a power tube circuit integrated with a sampling resistor.
Background
In the existing switching power supply circuit, various modes are adopted for current sampling, and the current sampling mainly comprises IC peripheral accurate resistance sampling, built-in resistance sampling and voltage mirror image sampling through a power tube.
By adopting a peripheral accurate resistance sampling method, current information obtained by using a precise sampling resistor outside an IC is required to be sent to an internal loop, so that not only are external pins increased, but also the number of peripheral elements is increased, the requirement on resistance is higher, and the realization cost is high;
by adopting a method of sampling with a built-in resistor, a built-in lightly doped poly resistor needs to be set as a sampling resistor, so that current can be accurately sampled, an external resistor is not needed, the efficiency is improved while the interference is reduced, but the working efficiency cannot be improved better due to the loss caused by the resistor and the interference generated by the resistor;
the method is widely applied, has no resistance loss and improves the working efficiency, but for a switch circuit, the method cannot accurately sample reverse current, when the voltage of a switch end SW is too lower than PGND, the sampling circuit cannot normally work, and meanwhile, the sampling proportion is influenced by the power tube rds (on) and cannot cope with the condition that VDD is adjustable.
The inventor thinks that if the sampling resistor can be arranged in the chip, and the characteristic of the power tube of the switching power supply is utilized, the parasitic resistor on the wiring of the lower tube of the power tube is used as the sampling current resistor, so that the current can be accurately sampled, the reverse current can be sampled, and the high-efficiency and wide-range sampling can be realized on the basis of not increasing additional elements and circuits.
Disclosure of Invention
Aiming at the defects and shortcomings in the prior art, the invention provides the power tube circuit integrated with the sampling resistor, and the routing parasitic resistor of the power tube is set as the sampling resistor, so that the sampling resistor in an IC is not needed, the precision of sampling current can be improved, the cost is saved, and the efficiency is improved.
In order to achieve the purpose, the invention provides the following technical scheme: the utility model provides a power tube circuit of sampling resistance has integrateed, includes the IC chip, the last integration of IC chip has main power tube and secondary power tube, main power tube is parallelly connected with the secondary power tube, main power tube adopts top aluminium metal to lead to paving the form and connects the source electrode drain electrode, the secondary power tube adopts an aluminium metal to connect the source electrode, adopts top aluminium metal to lead to paving the form and connect the drain electrode, the parasitic resistance of an aluminium is sampling resistance, the both ends of an aluminium metal are resistance sampling end.
In a preferred embodiment of the present invention, the channel length and width of the primary power transistor and the secondary power transistor are the same.
In a preferred embodiment of the present invention, the finger number of the primary power transistor is greater than the finger number of the secondary power transistor.
In a preferred embodiment of the present invention, the current flowing through the primary power tube is larger than the current flowing through the secondary power tube.
As a preferred embodiment of the present invention, the main power transistor and the sub power transistor are connected in parallel and are disposed at the same position of the layout.
As a preferred embodiment of the present invention, the positive and negative ends of the metal trace resistor are connected to a sampling amplifier circuit, the sampling amplifier circuit includes a resistor R1, one end of which is connected to the positive terminal of the sampling resistor, the other end of which is connected to the source of the NMOS transistor M3, one end of the resistor R2 is connected to the positive terminal of the sampling resistor, the other end of which is connected to the source of the NMOS transistor M4, one end of the resistor R3 is connected to the negative terminal of the sampling resistor, the other end of which is connected to the sources of the NMOS transistors M5 and M6, and resistors Rf1, Rf2 and Rf3 are respectively connected in series to R1, R2 and R3 to realize adjustment of the sampling coefficient, the NMOS transistors M3, M4 and M5 form a first current mirror, the NMOS transistors M11, M12, M21 and M22 form a second current mirror, the PMOS transistors M6 and M7 form a third current mirror, and the output of the sampling amplifier circuit is the output current output of the PMOS transistor M7, thereby increasing the working range and the linearity of the sampling amplifier circuit.
As a preferred embodiment of the present invention, the positive end of the resistor sampling end is a far-ground end VIS of the metal routing resistor, the negative end of the resistor sampling end is a near-ground end PGND of the metal routing resistor, the far-ground end VIS is a positive input end of the sampling amplifying circuit, and the near-ground end PGND is a negative input end of the sampling amplifying circuit.
In a preferred embodiment of the present invention, a branch current of the sampling amplifying circuit connected to the positive terminal of the sampling terminal is smaller than a current flowing through the secondary power tube.
Compared with the prior art, the invention provides a power tube circuit integrated with a sampling resistor, which has the following beneficial effects:
the sampling resistor is arranged in the chip, and the parasitic resistor on the wiring of the lower tube of the power tube is used as the sampling current resistor by utilizing the characteristics of the power tube of the switching power supply, so that the current can be accurately sampled, the reverse current can be sampled, the accurate sampling with high efficiency and wide range and basically no reduction of loss is realized on the basis of not increasing additional elements and circuits, the cost is saved, and the efficiency is improved.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a schematic diagram of a simple model circuit of parasitic resistances of a primary power tube and a secondary power tube of a power tube circuit integrated with a sampling resistor according to the present invention;
FIG. 2 is a model of the parasitic resistance of the secondary power transistor of the power transistor circuit integrated with the sampling resistor according to the present invention;
FIG. 3 is a schematic diagram of the layout of the primary power transistor and the secondary power transistor of the power transistor circuit integrated with the sampling resistor according to the present invention;
FIG. 4 is a block diagram of a power transistor circuit integrated with a sampling resistor according to the present invention;
FIG. 5 is a schematic diagram of a sampling amplifier circuit of a power transistor circuit integrated with a sampling resistor according to the present invention;
fig. 6 is a sampling signal relationship diagram of a power tube circuit integrated with a sampling resistor according to the present invention.
In the figure: 101. a main power tube; 102. and a secondary power tube.
Detailed Description
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further described with the specific embodiments.
As shown in fig. 4, the present invention provides a technical solution: a power tube circuit integrated with a sampling resistor comprises a power tube lower tube consisting of a main power tube 101 and a secondary power tube 102 and a parasitic resistor of aluminum metal, and provides sampling current for a main loop of a boost switch circuit, wherein the main loop comprises an inductor, a power tube upper tube 103, a power tube lower tube consisting of the main power tube 101 and the secondary power tube 102, a parasitic resistor model, a sampling amplification circuit, a slope compensation RAMP, an error amplifier EA, divider resistors Rd1 and Rd2, an output capacitor Cout, PWM, a clock CLK and a control logic unit, and when the loop works, the control logic outputs GP and GN signals to control the upper tube of the power tube to cut off and conduct the lower tube, the inductive current flows through the parasitic resistor to generate voltage drop VIS, and is sampled and amplified by the sampling amplifying circuit, after being overlapped and compensated with the RAMP signal RAMP, the signal is sent to PWM and output of an error amplifier for comparison, and then sent to control logic to generate control signals GP and GN to control the conduction and the cut-off of the upper and the lower tubes of the power tube.
As shown in FIG. 1, in the lower tube of the power tube in the parasitic resistance model, the finger number of the main power tube 101 is f1, the finger number of the secondary power tube 102 is f2, and in an ideal case of neglecting the parasitic resistance, the ratio of the current flowing through the main power tube and the secondary power tube should be f1: f 2.
As shown in fig. 2, the sub-power transistor 102 is split into a plurality of units according to the number of via holes on an aluminum metal trace at the drain end, each NMOS has a hole between the source and the metal trace corresponding to the NMOS, a hole between the drain and the metal trace, and a metal line resistor between via holes corresponding to the NMOS between the drain and the metal trace, the resistor connecting the source and the PGND is an aluminum metal trace resistor, the resistor connecting the drain and the SW is a hole between the top aluminum and the aluminum metal trace, and a parasitic resistor similar to the aluminum metal parasitic resistor and the top metal, when the switching power supply normally works, the lower tube of the power transistor is turned on, the current proportionally flows through the main power transistor 101 and the sub-power transistor 102, the current flowing through the sub-power transistor 102 generates a voltage difference on the parasitic resistor to be sampled from both ends of the source aluminum metal, the current flowing through the metal line resistor between via holes near the PGND end is large, and the current flowing through the metal line resistor between via holes near the visn end is small, the current has a trace current flowing through the VIS end and the parasitic sampling resistor in the parasitic resistor sampling amplifying circuit, and the current flowing through the secondary power tube 102 is far larger than the current of the sampling amplifying circuit, so that the error can be ignored, and the relationship between the current and the voltage difference of the PGND end of the VIS end can be found through modeling
VIS < (1/2) (parasitic r I102);
when the parasitic resistance of the drain electrode is larger than the parasitic resistance of the source electrode, the true value of the equation is smaller, and the sampling signal is estimated on the basis of the smaller true value.
As shown in fig. 3, the source and the drain of the main power transistor 101 are all wired in a manner of being fully covered by aluminum, the drain of the sub power transistor 102 is wired in a manner of being fully covered by aluminum, the source is wired in a manner of being connected by an aluminum wire, the finger number f1 of the main power transistor 101 is much larger than the finger number f2 of the sub power transistor 102, the rds (on) of the whole power transistor is not affected by the sub power transistor 102, the conversion efficiency is not affected while no additional sampling device is added, the on-resistance of the whole main power transistor 101 is smaller than that of the whole sub power transistor 102, and the current actually flowing through the sub power transistor 102 is
I102<(f2/(f1+f2))*IL。
As shown in fig. 5 and fig. 6, the sampling amplifying circuit includes a resistor R having one end connected to the positive terminal of the sampling resistor and the other end connected to the source of the NMOS transistor M, one end connected to the positive terminal of the sampling resistor R and the other end connected to the source of the NMOS transistor M, one end of the resistor R connected to the negative terminal of the sampling resistor R, the other end connected to the sources of the NMOS transistors M, Rf, which are connected in series with R, R to adjust the sampling coefficient, the NMOS transistors M, which form a current mirror one, the PMOS transistors M, which form a current mirror two, the PMOS transistors M, which form a current mirror three, the output of the sampling amplifying circuit is the output current of the PMOS transistor M, the current mirror one formed by the PMOS transistors M, R, the current mirror one formed by the PMOS transistors M, which form a current mirror to ensure that the currents of the first branch and the second branch are equal, and the voltages of the point B of the first branch and the second branch are ensured by the NMOS transistors C, the sampling amplification circuit comprises resistors R1, R2 and R3 with the resistance ratio of 1:2:1, resistors Rf1, Rf2 and Rf3 with the resistance ratio of 1:2:1, and resistors Rf1, Rf2 and Rf3 with the resistance ratios of less than R1, R2 and R3, so that fine adjustment of sampling coefficients is provided for R1, R2 and R3. The PMOS transistor M6 of the third branch amplifies the sampling current Ic, and the PMOS transistor M7 of the fourth branch mirrors the current of the third branch M6 and outputs the current. The voltage formula of the point B on the first branch is
VB＝Iin*(R2+Rf2)+VIS,
The voltage formula of point B on the second branch is
VC＝I2*(R3+Rf3)，
Since the mirror images of the PMOS tubes M1 and M2 make I1 equal to I2, and the mirror images of the NMOS tubes M3 and M4 make the voltages at the point A and the point B equal, the output formula of the sampling amplifying circuit is as follows
ISENSE＝(VIS/(R3+Rf3))+Iin，
Considering the size of the sampling resistance value and the poor fine adjustment of the voltage drop on the metal wire, resistors Rf1 and Rf2 are introduced into the sampling amplifying circuit, and resistors R1 and R2 are subjected to fine adjustment through Rf1 and Rf2 according to the description in the formula so as to obtain proper delta (dIL/dISENSE), delta (dIL/dISENSE) ≈ and ((1/2) × R parasitical × f2/(f1+ f2))/R3+ RF 3.
While there have been shown and described what are at present considered the fundamental principles and essential features of the invention and its advantages, it will be apparent to those skilled in the art that the invention is not limited to the details of the foregoing exemplary embodiments, but is capable of other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (7)
1. The utility model provides a power tube circuit of integrated sampling resistor which includes the IC chip which characterized in that: the IC chip is integrated with a main power tube and a secondary power tube, the main power tube is connected with the secondary power tube in parallel, the main power tube adopts a top aluminum metal to be connected with a source electrode drain electrode in a through-paving mode, the secondary power tube adopts an aluminum metal to be connected with a source electrode in a through-paving mode, the drain electrode is connected in a through-paving mode by adopting the top aluminum metal, parasitic resistance of the aluminum metal is sampling resistance, and two ends of the aluminum metal are resistance sampling ends.
2. The power tube circuit integrated with the sampling resistor as claimed in claim 1, wherein: the channel length and width of the main power tube and the secondary power tube are the same.
3. The power tube circuit integrated with the sampling resistor as claimed in claim 1, wherein: the finger number of the main power tube is larger than that of the secondary power tube.
4. The power tube circuit integrated with the sampling resistor as claimed in claim 1, wherein: the current flowing through the main power tube is larger than the current flowing through the secondary power tube.
5. The power tube circuit integrated with the sampling resistor as claimed in claim 1, wherein: the positive end and the negative end of the metal wiring resistor are connected with a sampling amplifying circuit, the sampling amplifying circuit comprises a resistor R1, one end of the resistor R1 is connected with the positive end of a sampling resistor, the other end of the resistor R2 is connected with the source electrode of an NMOS tube M3, the other end of the resistor R2 is connected with the source electrode of the NMOS tube M4, one end of a resistor R3 is connected with the negative end of the sampling resistor, the other end of the resistor R3 is connected with the source electrodes of the NMOS tubes M5 and M6, resistors Rf1, Rf2 and Rf3 are respectively connected in series with R1, R2 and R3 to realize adjustment of sampling coefficients, the NMOS tubes M3, M4 and M5 form a current mirror I, the PMOS tubes M11, M12, M21 and M22 form a current mirror II, the PMOS tubes M6 and M7 form a current mirror III, the output of the sampling amplifying circuit is the PMOS tube M7, and the working range and the linearity of the sampling amplifying circuit are increased.
6. The power tube circuit integrated with the sampling resistor as claimed in claim 5, wherein: the positive end of the resistance sampling end is a far-ground end VIS of the metal wiring resistor, the negative end of the resistance sampling end is a near-ground end PGND of the metal wiring resistor, the far-ground end VIS is a positive input end of the sampling amplifying circuit, and the near-ground end PGND is a negative input end of the sampling amplifying circuit.
7. The power tube circuit integrated with the sampling resistor as claimed in claim 5, wherein: and the current of a branch circuit connected with the positive end of the sampling end in the sampling amplification circuit is less than the current flowing through the secondary power tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111220865.5A CN113866484A (en) | 2021-10-20 | 2021-10-20 | Power tube circuit integrated with sampling resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111220865.5A CN113866484A (en) | 2021-10-20 | 2021-10-20 | Power tube circuit integrated with sampling resistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113866484A true CN113866484A (en) | 2021-12-31 |
Family
ID=78996710
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111220865.5A Pending CN113866484A (en) | 2021-10-20 | 2021-10-20 | Power tube circuit integrated with sampling resistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113866484A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102175908A (en) * | 2011-01-27 | 2011-09-07 | 无锡硅动力微电子股份有限公司 | Method for detecting current by wiring parasitic resistors by using power tube |
| CN104333221A (en) * | 2014-10-23 | 2015-02-04 | 中山大学 | Adaptive line loss compensation circuit for DC-DC (direct current) converter |
| CN110350767A (en) * | 2019-07-03 | 2019-10-18 | 苏州源特半导体科技有限公司 | A kind of current sample comparator circuit |
| CN210053349U (en) * | 2019-07-12 | 2020-02-11 | 苏州源特半导体科技有限公司 | Current modulator for switching power supply |
| CN111290463A (en) * | 2020-04-03 | 2020-06-16 | 南京芯力微电子有限公司 | Line loss compensation circuit of low dropout linear voltage stabilizing circuit and control method |
| US20200389088A1 (en) * | 2019-06-05 | 2020-12-10 | University Of Electronic Science And Technology Of China | Transient response enhancement circuit for buck-type voltage converters |
-
2021
- 2021-10-20 CN CN202111220865.5A patent/CN113866484A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102175908A (en) * | 2011-01-27 | 2011-09-07 | 无锡硅动力微电子股份有限公司 | Method for detecting current by wiring parasitic resistors by using power tube |
| CN104333221A (en) * | 2014-10-23 | 2015-02-04 | 中山大学 | Adaptive line loss compensation circuit for DC-DC (direct current) converter |
| US20200389088A1 (en) * | 2019-06-05 | 2020-12-10 | University Of Electronic Science And Technology Of China | Transient response enhancement circuit for buck-type voltage converters |
| CN110350767A (en) * | 2019-07-03 | 2019-10-18 | 苏州源特半导体科技有限公司 | A kind of current sample comparator circuit |
| CN210053349U (en) * | 2019-07-12 | 2020-02-11 | 苏州源特半导体科技有限公司 | Current modulator for switching power supply |
| CN111290463A (en) * | 2020-04-03 | 2020-06-16 | 南京芯力微电子有限公司 | Line loss compensation circuit of low dropout linear voltage stabilizing circuit and control method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI362818B (en) | Multi-phase dc-dc controller and controlling method thereof | |
| JP5169498B2 (en) | Current detection circuit and switching regulator including the current detection circuit | |
| WO2014072383A1 (en) | Absolute value current-sensing circuit for step-down dc-to-dc converters with integrated power stage | |
| CN102811023B (en) | Power amplifier | |
| CN216851374U (en) | Pre-charging circuit and chip | |
| CN213634248U (en) | Enhancement type buffer suitable for LDO circuit and LDO circuit thereof | |
| EP1885061B1 (en) | Amplifier arrangement and method for amplification | |
| CN113866484A (en) | Power tube circuit integrated with sampling resistor | |
| CN103401431B (en) | A kind of high stability inverse-excitation type DC-DC converter | |
| CN116388763B (en) | DAC compatible with voltage/current output | |
| CN115833560B (en) | SenseFET type full-wave inductance current sensor | |
| CN110048601B (en) | Active capacitance circuit | |
| CN113851077A (en) | Constant current source driving module of LED display screen and constant current source gain control method | |
| CN111900974A (en) | High-side current sampling circuit | |
| CN116338281A (en) | High-voltage MOSFET bidirectional current sampling circuit, power management chip and mobile electronic device | |
| Chen et al. | On-chip current sensing technique for hysteresis current controlled DC-DC converter | |
| CN114967830A (en) | Current limiting circuit, chip and electronic equipment | |
| CN110661409A (en) | Feedforward control method and circuit of converter | |
| US8704504B2 (en) | Power supply circuit comprising detection circuit including reference voltage circuits as reference voltage generation circuits | |
| CN114221541A (en) | Voltage reduction circuit and amplifier | |
| US20120242306A1 (en) | Driving circuit | |
| EP2178209A1 (en) | Chopper-type comparator and a/d converter | |
| CN108362929B (en) | Double-circuit positive-end current sampling module, sampling circuit, switching circuit and sampling method | |
| CN112816773A (en) | Current sampling circuit | |
| CN115955221B (en) | High-side voltage comparison circuit and control method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |