CN113851582A - Vertical Hall sensor and preparation method thereof - Google Patents
Vertical Hall sensor and preparation method thereof Download PDFInfo
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- CN113851582A CN113851582A CN202110949851.0A CN202110949851A CN113851582A CN 113851582 A CN113851582 A CN 113851582A CN 202110949851 A CN202110949851 A CN 202110949851A CN 113851582 A CN113851582 A CN 113851582A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- 229920005591 polysilicon Polymers 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 16
- 238000005468 ion implantation Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 9
- 239000011810 insulating material Substances 0.000 claims abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- 230000035945 sensitivity Effects 0.000 abstract description 10
- 238000002513 implantation Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 9
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000012876 topography Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N52/00—Hall-effect devices
- H10N52/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N52/00—Hall-effect devices
- H10N52/101—Semiconductor Hall-effect devices
Abstract
The invention relates to a vertical Hall sensor and a preparation method thereof. A vertical-type hall sensor, comprising: a silicon substrate with a deep groove formed on the surface; the deep groove is filled with a doped polysilicon layer; a plurality of contact regions are formed on the surface of the doped polycrystalline silicon layer, and the doping type of the contact regions is the same as that of the polycrystalline silicon layer; contact holes are formed above the contact areas, metal interconnection structures are formed among the contact holes, and the contact holes are isolated through insulating materials. The invention realizes the purpose of increasing the depth of the sensor by etching the groove first and then filling the doped polysilicon, and does not need the means of increasing the ion implantation depth, thereby improving the shape factor G, improving the sensitivity of the sensor and avoiding the problem of limited implantation depth of the ion implantation process.
Description
Technical Field
The invention relates to the field of semiconductor device manufacturing processes, in particular to a vertical Hall sensor and a manufacturing method thereof.
Background
The vertical hall sensor is used for detecting a magnetic field parallel to a plane of a chip, and is generally fabricated by a Deep N-well (DNW) in a CMOS integrated circuit, that is, by directly implanting ions into a semiconductor substrate. Limited to the existing technical conditions, the sensitivity is often low. In order to improve the sensitivity of the device, common methods include reducing the DNW width, using a narrow contact hole, and increasing the DNW depth. However, reducing the DNW width or using narrow contact holes tends to increase the resistance of the device, resulting in higher device power consumption. The DNW depth is limited by the ion implantation depth and the high-temperature diffusion technical conditions, the increase amplitude is limited, and the sensitivity of the vertical Hall sensor is greatly limited.
Disclosure of Invention
The invention mainly aims to provide a vertical Hall sensor and a preparation method thereof, the method realizes the purpose of increasing the depth of the sensor by using a mode of firstly etching a groove and then filling doped polysilicon, and does not need a means of increasing the ion implantation depth, thereby improving the shape factor G, improving the sensitivity of the sensor and avoiding the problem of limited implantation depth of an ion implantation process.
In order to achieve the above object, the present invention provides the following technical solutions.
A first aspect of the present invention provides a method for manufacturing a vertical hall sensor, including:
providing a silicon substrate;
forming a buffer oxide layer on the silicon substrate;
forming a silicon nitride layer over the buffer oxide layer;
etching a deep groove in the silicon substrate through the buffer oxide layer and the silicon nitride layer;
forming a first insulating layer on the surface of the deep groove;
filling doped polysilicon in the deep trench to cover the first insulating layer;
flattening and thinning the doped polysilicon;
removing the silicon nitride layer;
performing ion implantation on the surface of the doped polycrystalline silicon to form a plurality of contact regions; the ion implantation type is the same as the doping type of the doped polysilicon;
and depositing a second insulating layer, forming a contact hole and forming metal interconnection above the contact region in sequence.
A second aspect of the present invention provides a vertical-type hall sensor, which includes:
a silicon substrate with a deep groove formed on the surface,
the deep groove is filled with a doped polysilicon layer;
a plurality of contact regions are formed on the surface of the doped polycrystalline silicon layer, and the doping type of the contact regions is the same as that of the polycrystalline silicon layer;
contact holes are formed above the contact areas, metal interconnection structures are formed among the contact holes, and the contact holes are isolated through insulating materials.
Compared with the prior art, the invention achieves the following technical effects:
(1) the aim of larger depth of the sensor is fulfilled by combining deep groove etching and doped polysilicon filling the groove, so that higher sensitivity is obtained;
(2) the contact resistance of the device is not increased, and other adverse effects are avoided;
(3) the process provided by the invention is compatible with a CMOS process or other integrated circuit processes, and is easier to popularize.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
FIG. 1 is a top plan view of a vertical Hall sensor according to the present invention;
FIG. 2 is a schematic cross-sectional view of a vertical Hall sensor according to the present invention;
FIG. 3 is a diagram of the operation of the sensor shown in FIG. 2;
FIG. 4 is a flow chart of a method for manufacturing a vertical Hall sensor according to the present invention;
fig. 5 to 13 are schematic structural diagrams obtained in different processes when the vertical hall sensor is manufactured according to the present invention.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
According to the working principle of the Hall sensor, the Hall voltage is as follows:
wherein G is a form factor, depending on the geometry of the Hall sensor; r isHIs a Hall scattering factor and is determined by materials; q is the electron electric quantity, n is the carrier concentration, and t isThe width of the vertical hall sensor; i is the input current (bias current) and B is the magnetic field strength.
Sensitivity of the Hall sensor is SIIt is related to the following factors:
then
VH＝SIIB formula (3)
As can be seen from equation (2), in order to increase the sensitivity of the hall sensor, the shape factor G can be increased, or the carrier concentration n can be decreased to decrease the width t. However, decreasing n and t increases the resistance of the device, thereby increasing the device power consumption, and therefore starts primarily with increasing the form factor G.
The shape factor is usually between 0 and 1, which is determined by the geometry of the Hall sensor. Typically the form factor is affected by short circuit effects, the more pronounced the short circuit effect the smaller G. For vertical hall sensors, there are generally two ways to reduce the short circuit effect:
first, the depth of the sensor is increased. As the depth increases, current flows in the depth direction, which correspondingly reduces the leakage current to the output, thereby increasing the form factor G.
Second, the use of narrow contact holes equates to increased distance between the electrodes, thereby reducing shorting effects. However, the narrow contact hole increases the contact resistance, thereby increasing the power consumption of the device.
Therefore, to increase the form factor G, one would typically choose to increase the depth of the sensor. The vertical hall sensor is usually fabricated by using Deep N-well (DNW) in CMOS process. To increase the depth of DNW, only the depth of ion implantation or the thermal budget of high temperature diffusion can be increased, however, under the existing technical conditions, the increase of the depth of DNW is very limited, and in order to take the performance of CMOS devices into consideration, the thermal budget of high temperature diffusion must be strictly controlled, thus greatly limiting the sensitivity of the vertical hall sensor.
In order to obtain a vertical hall sensor with higher sensitivity, the invention provides a vertical hall sensor manufactured in a manner that a deep trench is filled with doped polysilicon, namely the vertical hall sensor shown in fig. 1 and 2.
Specifically, the vertical hall sensor provided by the present invention comprises:
the surface of the silicon substrate 1 is formed with a Deep Trench (DTI), the deep trench defines the position of the sensor, and the size (including depth, width, etc.) of the deep trench can be adjusted according to the required performance or application scene of the sensor. The silicon substrate 1 may be a wafer, a silicon on insulator, or the like.
An insulating layer 6 is formed on the surface of the silicon substrate 1. The insulating layer may isolate and protect the active region, wherein surfaces within the deep trench are covered with the insulating layer, such as shown in fig. 2. The material of the insulating layer is usually silicon oxide SiO2The growth mode can be any, for example, dry or wet oxygen oxidation, chemical vapor deposition or atomic layer deposition.
And the deep groove is filled with a doped polysilicon layer 2 which covers the insulating layer 6 in the deep groove. Because the polysilicon is self-doped, ion implantation is not needed, the depth of the groove can be increased without limit to increase the form factor, the problem of limited depth of the ion implantation process is not needed to be considered, and the problem of increased contact resistance is not needed to be considered. The doping type is N-type or P-type, and the specific element type is not limited in the present invention.
A plurality of contact regions 7 are formed on the surface of the doped polysilicon layer 2, and the doping type of the contact regions 7 is the same as that of the doped polysilicon layer 2. The contact region 7 requires a higher doping concentration and can be realized by means of ion implantation after filling.
Contact holes 5 are formed above the contact regions 7, metal interconnection structures are formed among the contact holes 5, and the contact holes are isolated through insulating materials. The metal layers may be provided in one or more layers, for example, two layers as shown in fig. 2, including metal layers 3 and 4, adjacent metal layers being connected by via holes 12, and the via holes 12 and the contact holes 5 being isolated from each other by an insulating material. For between contact holesOf the type of insulating material, usually silicon oxide SiO2The growth mode can be any, for example, dry or wet oxygen oxidation, chemical vapor deposition or atomic layer deposition.
In addition, the number and layout of contact holes are arbitrary and can be designed as is typical in the art, for example, the sensor of fig. 2 uses 5 electrodes, and its working state is as shown in fig. 3, including C1, C2, C3, C4, and C5 electrodes, where C1 and C5 are shorted together by a metal layer, that is, C1 and C5 are always equipotential. During operation, bias current IbiasInflow from the C1 and C5 ends, outflow from the C3 end, or vice versa; c2 and C4 are output electrodes that output voltage values (i.e., hall voltages). Fig. 3 illustrates the operation principle of the vertical hall sensor by taking the current in one direction as an example. When no magnetic field exists outside, the ends of C2 and C4 are equipotential due to the complete symmetry of the sensor structure, that is, the output voltage is 0; when a magnetic field parallel to the sensor surface is applied, the current deflects under the action of the lorentz force, negative charges are accumulated on the lower surface of the sensor at the side of C2, correspondingly positive charges are left on the upper surface, and the situation is opposite at the side of C4, so that a potential difference is formed between C2 and C4, namely the Hall voltage VH. For a sensor of this construction, the shape factor G is affected by the short circuit effect, which is more pronounced the smaller G. The short-circuit effect means that in a non-ideal condition, a part of current at the input end flows away from the output end, namely, the current flows into the terminal C1/C5, and in the process of flowing out from the terminal C3, because the resistance of the device is limited, a part of leakage current flows away from the terminal C2/C4. Therefore, to increase the form factor, the occurrence of the short-circuit effect must be suppressed. According to the invention, the deep groove is etched, and the doped polysilicon is filled in the deep groove to increase the depth of the sensor, and along with the increase of the depth, the current flows to the depth direction, so that the leakage current flowing to the output end is correspondingly reduced, and the shape factor G is increased.
For the above-described vertical type hall sensor structure provided by the present invention, any preparation method may be employed, and one of them is listed below.
In the process shown in fig. 4, a silicon substrate 1 is provided first, and a buffer oxide layer 9 is formed on the silicon substrate 1, so as to obtain the topography shown in fig. 5. The buffer oxide layer 9 may be formed by any method, including but not limited to evaporation, thermal oxidation (dry or wet), chemical vapor deposition (LPCVD, RTCVD, PECVD), atomic layer deposition, and the like, and a high temperature oxidation method is preferably used in the present invention.
Next, forming a silicon nitride layer 10 over the buffer oxide layer 9, resulting in the topography shown in fig. 6; the silicon nitride layer 10 serves as a sacrificial layer, mainly serves as a mask layer, and can protect an underlying substrate from being damaged to generate defects. The silicon nitride layer 10 may be formed by any process including, but not limited to, LPCVD, RTCVD, PECVD, atomic layer deposition, etc., with LPCVD being preferred in the present invention.
And then, etching a deep trench 11 in the silicon substrate 1 through the buffer oxide layer 9 and the silicon nitride layer 10 to obtain the morphology shown in fig. 7. The etching at this step usually employs a typical process, i.e., including photoresist coating, exposure, development, etching, and subsequent photoresist removal processes. Different etchants may be used to etch in steps for different materials.
And then covering an insulating layer 6 on the surface of the deep trench 11 to obtain the morphology shown in fig. 8. The material of the insulating layer 6 is typically silicon oxide SiO2The growth mode can be any, for example, dry or wet oxygen oxidation, chemical vapor deposition or atomic layer deposition. The invention preferably adopts a high-temperature oxidation method to form silicon oxide on the surface of the deep trench to be used as an insulating layer.
And then filling doped polysilicon in the deep trench 11 to form a doped polysilicon layer 2, and covering the insulating layer 6 to obtain the shape shown in fig. 9. The doped polysilicon layer 2 may be formed by a chemical vapor deposition (LPCVD, PECVD, etc.) or atomic layer deposition process. The invention preferentially adopts the LPCVD mode to form the polysilicon. This step is accomplished by autodoping, i.e., adding a gas containing the desired doping element, including but not limited to B, to the LPCVD precursor gas2H6、PH3、AsH3And the like. Concentration of dopingThe degree is preferably controlled to 1015～1016cm-3And (3) a range.
In the last step, in order to ensure that the deep trench is completely filled with polysilicon, excessive filling is usually performed, so that the polysilicon covers the silicon nitride layer 10, and at this time, the doped polysilicon layer 2 needs to be planarized and thinned, so that the silicon nitride is exposed. The means of thinning is arbitrary, such as Chemical Mechanical Planarization (CMP), wet etching, or a combination of both. For example, in the manner shown in the flow chart of fig. 4, CMP is first stopped on the surface of the silicon nitride layer to obtain the topography shown in fig. 10; and then wet etching is carried out to ensure that the polysilicon is basically flush with the surface of the substrate, so as to obtain the appearance shown in the figure 11.
The silicon nitride layer 10 is then removed to obtain the topography shown in fig. 12, by any means, such as a typical phosphoric acid solution etching method.
The surface of the doped polysilicon layer 2 is ion implanted to form a plurality of contact regions 7, resulting in the topography shown in fig. 13, including 5 contact regions. The doping concentration of the contact region 7 reaches 1020cm-3The above levels. This step of ion implantation is of the same type as the doping of the doped polysilicon.
And sequentially depositing an insulating layer, forming a contact hole and forming a metal interconnection above the contact region 7. The structure of the metal interconnection is various, for example, two metal layers, metal layer 3 and metal layer 4, as shown in fig. 2, adjacent metal layers are connected through a via hole 12, and contact holes 5 are isolated by an insulating material. Procedures used in this step include, but are not limited to, typical deposition, sputtering, patterning, and the like.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (10)
1. A preparation method of a vertical Hall sensor is characterized by comprising the following steps:
providing a silicon substrate;
forming a buffer oxide layer on the silicon substrate;
forming a silicon nitride layer over the buffer oxide layer;
etching a deep groove in the silicon substrate through the buffer oxide layer and the silicon nitride layer;
forming a first insulating layer on the surface of the deep groove;
filling doped polysilicon in the deep trench to cover the first insulating layer;
flattening and thinning the doped polysilicon;
removing the silicon nitride layer;
performing ion implantation on the surface of the doped polycrystalline silicon to form a plurality of contact regions; the ion implantation type is the same as the doping type of the doped polysilicon;
and depositing a second insulating layer, forming a contact hole and forming metal interconnection above the contact region in sequence.
2. The method according to claim 1, wherein the buffer oxide layer, the first insulating layer, and the second insulating layer are each independently selected from thermal silicon oxide or CVD-deposited silicon oxide.
3. The method of claim 1, wherein the doped polysilicon has a doping concentration of up to 1015～1016cm-3。
4. A method according to claim 3, wherein the doping concentration of the contact region is up to 1020cm-3The above levels.
5. The production method according to claim 1, wherein the silicon nitride layer is removed using a phosphoric acid solution.
6. The production method according to claim 1, wherein the buffer oxide layer is formed by a high-temperature oxidation method;
and/or the presence of a gas in the gas,
the silicon nitride layer is formed using LPCVD.
7. The method of manufacturing according to claim 1, wherein the thinning is performed by: combining CMP and wet etching.
8. A vertical hall sensor, comprising:
a silicon substrate with a deep groove formed on the surface,
the deep groove is filled with a doped polysilicon layer, and the polysilicon layer is isolated from silicon below the polysilicon layer through an insulating layer;
a plurality of contact regions are formed on the surface of the doped polycrystalline silicon layer, and the doping type of the contact regions is the same as that of the polycrystalline silicon layer;
contact holes are formed above the contact areas, metal interconnection structures are formed among the contact holes, and the contact holes are isolated through insulating materials.
9. The vertical hall sensor of claim 8 wherein the doped polysilicon layer has a doping concentration of up to 1015～1016cm-3。
10. The vertical hall sensor of claim 9 wherein the contact region has a doping concentration of up to 1020cm-3The above levels.
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