CN113851484A - 3D NAND memory and manufacturing method thereof - Google Patents

3D NAND memory and manufacturing method thereof Download PDF

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Publication number
CN113851484A
CN113851484A CN202111085087.3A CN202111085087A CN113851484A CN 113851484 A CN113851484 A CN 113851484A CN 202111085087 A CN202111085087 A CN 202111085087A CN 113851484 A CN113851484 A CN 113851484A
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layer
charge storage
sacrificial
storage layer
insulating
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高庭庭
刘小欣
夏志良
孙昌志
耿万波
杜小龙
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

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Abstract

The application provides a manufacturing method of a 3D NAND memory, which comprises the following steps: forming at least one first insulating layer and at least one first sacrificial layer on a substrate; forming a second sacrificial layer with a thickness greater than the first sacrificial layer; etching to remove the preset size part of the second sacrificial layer and the preset size part of at least one layer of the first sacrificial layer; forming at least one first charge storage layer and a second charge storage layer, wherein the width of the first charge storage layer is larger than that of the second charge storage layer; and etching to remove the second charge storage layer and part of at least one first charge storage layer. According to the manufacturing method of the 3D NAND memory, the formed top selection gate layer does not comprise the charge storage layer, and in the process of opening or closing the top selection gate, electrons in the polycrystalline silicon channel layer can be prevented from transferring to the charge storage layer to generate a weak electron injection effect, so that the threshold voltage of the top selection gate is unstable.

Description

3D NAND memory and manufacturing method thereof
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a 3D NAND memory and a manufacturing method thereof.
Background
NAND flash memory is a better storage device than hard disk drives, and is widely used in electronic products as people seek nonvolatile storage products with low power consumption, light weight and good performance. The NAND flash memory with a planar structure is approaching the limit of practical expansion, and in order to further increase the storage capacity and reduce the storage cost per bit, a NAND memory with a 3D structure is proposed.
Currently, a TSG (top select gate) of a CTF (charge trapping) type 3D NAND memory is of an ONOP (barrier layer-charge storage layer-tunneling layer-polysilicon channel layer) type, and when the TSG is turned on or turned off, the TSG affects the distribution of charges in the polysilicon channel layer, so that part of electrons in the polysilicon channel layer are transferred to the charge storage layer, and a weak electron injection effect is generated, so that the threshold voltage of the TSG is unstable, and the data read-write capability of the 3D NAND memory is unstable, thereby affecting the control capability of the TSG.
Disclosure of Invention
In order to solve the above technical problems, the present application provides a 3D NAND memory and a method for manufacturing the same, in which a charge storage layer does not exist in a top select gate of the 3D NAND memory, and electrons in a polysilicon channel layer can be prevented from migrating into the charge storage layer in a process of turning on or off the top select gate, so that the top select gate has a stable threshold voltage.
One aspect of the present application provides a method of manufacturing a 3D NAND memory, the method of manufacturing the 3D NAND memory including: providing a substrate; forming a stack layer on the substrate, wherein the stack layer comprises at least one first insulating layer and at least one first sacrificial layer, the first insulating layer and the first sacrificial layer are formed by alternately stacking, and the number of the first insulating layers is one more than that of the first sacrificial layers; forming a second sacrificial layer on one side of the stacked layers far away from the substrate, wherein the thickness of the second sacrificial layer is larger than that of the first sacrificial layer; forming a second insulating layer on one side of the second sacrificial layer far away from the stacking layer; etching the second insulating layer, the second sacrificial layer and the stacked layer along a stacking direction to form at least one channel hole penetrating through the second insulating layer, the second sacrificial layer and the stacked layer, so that the second insulating layer, the second sacrificial layer, the at least one first insulating layer and the at least one first sacrificial layer have side walls exposed out of the at least one channel hole; etching and removing a preset size part of the second sacrificial layer and a preset size part of the at least one first sacrificial layer from the at least one channel hole, so that the side walls of the second sacrificial layer and each first sacrificial layer are recessed inwards to have the same size; depositing and forming a charge storage layer from the at least one channel hole, wherein the charge storage layer comprises at least one first charge storage layer covering the side wall of the first sacrificial layer and a second charge storage layer covering the side wall of the second sacrificial layer, and the width of the first charge storage layer is larger than that of the second charge storage layer, so that the side wall of the first charge storage layer protrudes out of the side wall of the second charge storage layer; and etching the charge storage layer from the at least one channel hole, and simultaneously removing the second charge storage layer and part of the at least one first charge storage layer to form at least one target charge storage layer, wherein the target charge storage layer covers the side wall of the first sacrificial layer.
Another aspect of the present application also provides a 3D NAND memory, the 3D NAND memory including: the semiconductor device comprises a substrate, a top selection gate layer, at least one control gate layer, at least one first insulating layer, at least one channel hole and a second insulating layer. Each control gate layer comprises a first conductive layer and a target charge storage layer, the first insulating layers and the first conductive layers are alternately stacked on the substrate, the number of layers of the at least one first insulating layer is one more than that of the first conductive layers of the at least one control gate layer, and the first insulating layers protrude out of the first conductive layers in a direction perpendicular to the stacking direction. The top selection gate layer comprises a second conductive layer which is arranged on one side, far away from the control gate layer, of the first insulating layer in a stacking mode, wherein the thickness of the second conductive layer is larger than that of the first conductive layer, and the first insulating layer adjacent to the second conductive layer protrudes out of the second conductive layer in a direction perpendicular to the stacking direction. The second insulating layer covers one side, far away from the first insulating layer, of the second conducting layer, and protrudes out of the second conducting layer in the direction perpendicular to the stacking direction. The channel hole penetrates through the second insulating layer, the second conducting layer, the first insulating layer and the first conducting layer along the stacking direction, and the charge storage layer covers the side wall, exposed out of the at least one channel hole, of the first conducting layer.
According to the 3D NAND memory and the manufacturing method thereof, the second charge storage layer covering the side wall of the second sacrificial layer is removed through etching, and the top selection gate layer which does not include the charge storage layer is formed, so that when the top selection gate is turned on or turned off, electrons in the second polysilicon channel layer of the top selection gate layer cannot migrate to the charge storage layer, and the threshold voltage of the top selection gate is stable, and therefore the top selection gate has stable control capability, and the first charge storage layer covering the side wall of the first sacrificial layer is reserved, so that the data storage function of the control gate layer including the first charge storage layer is not affected.
Drawings
In order to more clearly illustrate the technical solution of the present application, the drawings needed to be used in the embodiments will be briefly described below, and obviously, the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing a 3D NAND memory according to an embodiment of the present disclosure.
Fig. 2 to 8 are schematic cross-sectional structures of the 3D NAND memory corresponding to the steps in fig. 1.
FIG. 9 is a cross-sectional structure of the 3D NAND memory after forming a barrier layer.
Fig. 10 is a schematic cross-sectional structure of the 3D NAND memory after the third charge storage layer is removed.
FIG. 11 is a flowchart of a method for manufacturing a 3D NAND memory according to another embodiment of the present application.
Fig. 12 to 17 are schematic cross-sectional structures of the 3D NAND memory corresponding to the steps in fig. 11.
FIG. 18 is a schematic cross-sectional view of a 3D NAND memory according to an embodiment of the present application.
Reference numerals:
a substrate 10; a stack of layers 20; a first insulating layer 201; a first sacrificial layer 202; a second sacrificial layer 30; a second insulating layer 40; a channel hole 50; a barrier layer 60; a first barrier layer 601; a second barrier layer 602; a third barrier layer 603; a charge storage layer 70; a first charge storage layer 701; a second charge storage layer 702; a target charge storage layer 703; a third charge storage layer 705; a tunneling layer 80; a first tunneling layer 801; a second tunneling layer 802; a third tunneling layer 803; a polysilicon channel layer 85; a first polysilicon channel layer 851; a second polysilicon channel layer 852; a third polysilicon channel layer 853; an oxide layer 90; a polysilicon plug 95; a first groove 2021; a second groove 301; a third groove 303; a fourth groove 2013; a first conductive layer 2022; a second conductive layer 302; a control gate layer 11; a top select gate layer 12; the 3D NAND memory 100.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without inventive step, are within the scope of the present disclosure.
In the description of the present application, the terms "first", "second", "third", etc. are used for distinguishing different objects, not for describing a particular order, and further, the terms "upper", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, only for convenience of description and simplicity of description, but do not indicate or imply that the referred device or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present application.
It should be noted that the drawings provided in the embodiments of the present invention are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in the actual implementation, the type, quantity and proportion of the components in the actual implementation can be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1 to 8 together, fig. 1 is a flowchart illustrating a method for manufacturing a 3D NAND memory according to an embodiment of the present disclosure, and fig. 2 to 8 are schematic cross-sectional structures of the 3D NAND memory corresponding to the steps in fig. 1. As shown in fig. 1, the method of manufacturing the 3D NAND memory includes the steps of:
s101: a substrate 10 is provided.
S102: as shown in fig. 2, a stack layer 20 is formed on the substrate 10, the stack layer 20 includes at least one first insulating layer 201 and at least one first sacrificial layer 202, and the first insulating layer 201 and the first sacrificial layer 202 are alternately stacked, wherein the number of layers of the at least one first insulating layer 201 is one more than that of the at least one first sacrificial layer 202.
S103: as shown in fig. 3, a second sacrificial layer 30 is formed on a side of the stacked layer 20 away from the substrate 10, and a thickness of the second sacrificial layer 30 is greater than a thickness of the first sacrificial layer 202.
S104: as shown in fig. 4, a second insulating layer 40 is formed on a side of the second sacrificial layer 30 away from the stacked layer 20.
S105: as shown in fig. 5, the second insulating layer 40, the second sacrificial layer 30 and the stacked layer 20 are etched along the stacking direction of the layers of the stacked layer 20 to form at least one channel hole 50 penetrating through the second insulating layer 40, the second sacrificial layer 30 and the stacked layer 20, so that the second insulating layer 40, the second sacrificial layer 30, the at least one first insulating layer 201 and the at least one first sacrificial layer 202 have sidewalls exposed from the at least one channel hole 50.
S106: as shown in fig. 6, a predetermined dimension portion of the second sacrificial layer 30 and a predetermined dimension portion of the at least one first sacrificial layer 202 are etched and removed from the at least one channel hole 50, so that the sidewalls of the second sacrificial layer 30 and each first sacrificial layer 202 are recessed inward by the same dimension. The predetermined size portion refers to a portion having a predetermined size, so that after the predetermined size portion of the second sacrificial layer 30 and the predetermined size portion of the at least one first sacrificial layer 202 are removed by etching, the sidewalls of the second sacrificial layer 30 and each first sacrificial layer 202 are recessed inward by the same predetermined size. Wherein the preset dimension refers to a dimension in a direction perpendicular to the wall of the channel hole 50.
S107: as shown in fig. 7, a charge storage layer 70 is deposited from the at least one channel hole 50, the charge storage layer 70 includes at least one first charge storage layer 701 covering a sidewall of the first sacrificial layer 202 and a second charge storage layer 702 covering a sidewall of the second sacrificial layer 30, wherein a width of the first charge storage layer 701 is larger than that of the second charge storage layer 702, so that a sidewall of the first charge storage layer 701 protrudes from a sidewall of the second charge storage layer 702.
S108: as shown in fig. 8, the charge storage layer 70 is etched from the at least one channel hole 50, and the second charge storage layer 702 and a portion of the at least one first charge storage layer 701 are removed to form at least one target charge storage layer 703, where the target charge storage layer 703 covers a sidewall of the first sacrificial layer 202.
The substrate 10 may be a semiconductor material, such as silicon, germanium, or the like.
The first insulating layer 201 and the second insulating layer 40 may be silicon dioxide layers. The first sacrificial layer 202, the second sacrificial layer 30, and the charge storage layer 70 may be silicon nitride layers.
The thicknesses of the second sacrificial layer 30 and the first sacrificial layer 202 are the dimensions of the second sacrificial layer 30 and the first sacrificial layer 202 in the stacking direction.
The widths of the first charge storage layer 701 and the second charge storage layer 702 are the sizes of the first charge storage layer 701 and the second charge storage layer 702 in the direction perpendicular to the stacking direction.
The method for manufacturing the 3D NAND memory is further specifically described below with reference to fig. 2 to 8.
Referring to fig. 2 again, fig. 2 is a schematic cross-sectional structure diagram of the 3D NAND memory obtained after step S102 in fig. 1 is completed. As shown in fig. 2, forming the stack layer 20 on the substrate 10 includes: forming the first insulating layer 201 on the substrate 10; forming the first sacrificial layer 202 on the side of the first insulating layer 201 far away from the substrate 10; the first insulating layers 201 and the first sacrificial layers 202 are repeatedly and alternately stacked to form at least one first insulating layer 201 and at least one first sacrificial layer 202, wherein the number of layers of the at least one first insulating layer 201 is one more than that of the at least one first sacrificial layer 202.
Specifically, the first insulating layer 201 may be formed by a chemical vapor deposition process, for example, the substrate 10 is placed in a reaction chamber of a vertical furnace tube, and TEOS (tetraethylorthosilicate) and a carrier gas N are introduced into the reaction chamber2TEOS decomposes to produce silicon dioxide, which is uniformly deposited on the substrate 10 to form the first insulating layer 201; for another example, the substrate 10 is placed in a reaction chamber of a vertical furnace tube, and DCS (dichlorosilane) and N are introduced into the reaction chamber2O, DCS and N2Reaction of O to form SiO2、N2And HCl, SiO produced2Is uniformly deposited on the substrate 10 to form the first insulating layer 201.
In some other embodiments, the first insulating layer 201 can be formed by an atomic layer deposition process, for example, by placing the substrate 10 in a vertical furnace tubeIn the reaction chamber, Si [ N (CH) is introduced into the reaction chamber3)3]3H and O3，Si[N(CH3)3]3H and O3The reaction produces silicon dioxide, which is uniformly deposited on the substrate 10 to form the first insulating layer 201.
In some embodiments, the first sacrificial layer 202 may be formed by a chemical vapor deposition process, for example, DCS (dichlorosilane) and ammonia gas are introduced into a reaction chamber, and react with the ammonia gas to form silicon nitride, and the silicon nitride is uniformly deposited on the first insulating layer 201 to form the first sacrificial layer 202; as another example, SiH is introduced into the reaction chamber4With ammonia, SiH4Reacts with ammonia gas to form silicon nitride, and the formed silicon nitride is uniformly deposited on the first insulating layer 201 to form the first sacrificial layer 202.
Referring to fig. 3 again, fig. 3 is a schematic cross-sectional structure diagram of the 3D NAND memory obtained after step S103 in fig. 1 is completed. As shown in fig. 3, a second sacrificial layer 30 is formed on a side of the stacked layer 20 away from the substrate 10, and a thickness of the second sacrificial layer 30 is greater than a thickness of the first sacrificial layer 202.
The second sacrificial layer 30 may be formed by a chemical vapor deposition process, and the specific process may refer to the process of forming the first sacrificial layer 202, which is not described herein again.
Referring to fig. 4 again, fig. 4 is a schematic cross-sectional structure diagram of the 3D NAND memory obtained after step S104 in fig. 1 is completed. As shown in fig. 4, a second insulating layer 40 is formed on a side of the second sacrificial layer 30 away from the stacked layer 20. The second insulating layer 40 may be formed by a chemical vapor deposition process or an atomic layer deposition process, and the specific process may refer to the process for forming the first insulating layer 201, which is not described herein again.
Referring to fig. 5 again, fig. 5 is a schematic cross-sectional view of the 3D NAND memory obtained after step S105 in fig. 1 is completed. As shown in fig. 5, the second insulating layer 40, the second sacrificial layer 30 and the stacked layer 20 are etched along the stacking direction to form at least one channel hole 50 penetrating through the second insulating layer 40, the second sacrificial layer 30 and the stacked layer 20, so that the second insulating layer 40, the second sacrificial layer 30, the at least one first insulating layer 201 and the at least one first sacrificial layer 202 have sidewalls exposed to the at least one channel hole 50.
The at least one channel hole 50 may be formed by a photolithography process and an etching process, specifically, a photoresist layer covering the top of the second insulating layer 40 is formed by spin-coating a photoresist on the second insulating layer 40, a portion of the photoresist layer is removed by an exposure and development process to form at least one opening in the photoresist layer, the opening exposes a portion of the second insulating layer 40, and the second insulating layer 40, the second sacrificial layer 30, the at least one first insulating layer 201, and the at least one first sacrificial layer 202 are sequentially etched from the at least one opening by a dry or wet etching process to form the at least one channel hole 50.
Referring to fig. 6 again, fig. 6 is a schematic cross-sectional structure diagram of the 3D NAND memory after step S106 is completed. As shown in fig. 6, in some embodiments, a wet etching process is used to etch and remove a predetermined dimension portion of the second sacrificial layer 30 and a predetermined dimension portion of the at least one first sacrificial layer 202, so that the sidewalls of the second sacrificial layer 30 and each first sacrificial layer 202 are recessed inward by the same dimension.
Specifically, a wet etching machine is used for etching, the wet etching machine includes an etching groove, a hot phosphoric acid solution is contained in the etching groove, the 3D NAND memory is completely immersed in the hot phosphoric acid solution and is immersed for a preset time t1, the hot phosphoric acid solution enters the 3D NAND memory from the at least one channel hole 50 and selectively etches the second sacrificial layer 30 and the first sacrificial layer 202, and the preset time t1 can be obtained according to an etching rate v1 of a wet etching process and a preset size L of the second sacrificial layer 30 and the first sacrificial layer 202, which are preset to be removed, that is, t1 is L/v 1.
Wherein the volume fraction range of the hot phosphoric acid solution is 85-88%, and the temperature range of the hot phosphoric acid solution is 155-165 ℃.
After the etching process, the side wall of the second sacrificial layer 30 is recessed inwards to enable the second sacrificial layer 30 and two adjacent first insulating layers 201 to form a third groove 303, the side wall of each first sacrificial layer 202 is recessed inwards to enable the first sacrificial layer 202 and two adjacent first insulating layers 201 to form a fourth groove 2013, and the inner diameter of the third groove 303 is larger than that of the fourth groove 2013.
In some other embodiments, the 3D NAND memory may be completely immersed in a hydrofluoric acid solution, and the predetermined-sized portion of the second sacrificial layer 30 and the predetermined-sized portion of the first sacrificial layer 202 may be removed by hydrofluoric acid etching.
In other embodiments, the predetermined-sized portion of the second sacrificial layer 30 and the predetermined-sized portion of the at least one first sacrificial layer 202 may be removed by etching through a dry etching process, specifically, the 3D NAND memory is disposed in a reaction chamber of an ICP (inductively coupled plasma) apparatus, and a fluorine-containing gas, for example, CHF, is introduced into the reaction chamber3The plasma generated by the apparatus and the fluorine-containing gas act together to etch away the predetermined-sized portion of the second sacrificial layer 30 and the predetermined-sized portion of the at least one first sacrificial layer 202.
Referring to fig. 7 again, fig. 7 is a schematic cross-sectional structure diagram of the 3D NAND memory after step S107 is completed. As shown in fig. 7, a charge storage layer 70 is deposited from the at least one channel hole 50, the charge storage layer 70 includes at least one first charge storage layer 701 covering a sidewall of the first sacrificial layer 202 and a second charge storage layer 702 covering a sidewall of the second sacrificial layer 30, wherein a width of the first charge storage layer 701 is larger than that of the second charge storage layer 702, so that a sidewall of the first charge storage layer 701 protrudes from a sidewall of the second charge storage layer 702.
Specifically, the charge storage layer 70 may be formed by a chemical vapor deposition process or an atomic layer deposition process, for example, the 3D NAND memory is placed in a reaction chamber of a vertical furnace tube, DCS (dichlorosilane) and ammonia gas are introduced into the reaction chamber for a preset time t2, the DCS and ammonia gas react to generate silicon nitride, the generated silicon nitride is uniformly deposited in the third groove 303 and covers the sidewall of the second sacrificial layer 30 to form the second charge storage layer 702, and meanwhile, the silicon nitride is uniformly deposited in the fourth groove and covers the sidewall of the first sacrificial layer 202 to form the first charge storage layer 701.
The predetermined time T2 can be calculated according to the deposition rate v2 of the silicon nitride and the deposition thickness T1 of the silicon nitride, that is, T2 is T1/v2, wherein the deposition thickness T1 of the silicon nitride is greater than half of the thickness of the first sacrificial layer 202 and less than half of the thickness of the second sacrificial layer 30, such that the silicon nitride can fill the fourth groove 2013 when deposited in the fourth groove 2013, and the silicon nitride covers the inner wall of the third groove 303 and does not fill the third groove 303 when deposited in the third groove 303, such that the width of the first charge storage layer 701 covering the side wall of the first sacrificial layer 202 is greater than the width of the second charge storage layer 702 covering the side wall of the second sacrificial layer 30, and the widths of the first charge storage layer 701 and the second charge storage layer 702 are the first charge storage layer 701, the second charge storage layer 702, and the first charge storage layer 701 and the second charge storage layer 702 are the first charge storage layer 701, the second charge storage layer 701, and the second charge storage layer 702 are the first charge storage layer 701, and the second charge storage layer 702 respectively, The size of the second charge storage layer 702 in the direction perpendicular to the stacking direction is such that, subsequently, while the second charge storage layer 702 covering the sidewall of the second sacrificial layer 30 is completely removed by an etching process, the portion of the first charge storage layer 701 covering the sidewall of the first sacrificial layer 202 is removed, and the remaining portion of the first charge storage layer 701 still covers the sidewall of the first sacrificial layer 202 to form the target charge storage layer 703.
Referring to fig. 8 again, fig. 8 is a schematic cross-sectional view of the 3D NAND memory after step S108 is completed. As shown in fig. 8, in some embodiments, the charge storage layer 70 is etched from within the at least one channel hole 50 using a wet etching process while removing the second charge storage layer 702 and a portion of the at least one first charge storage layer 701.
Specifically, a wet etching machine is used for etching, the wet etching machine comprises an etching groove, a hot phosphoric acid solution is filled in the etching groove, the 3D NAND memory is completely soaked in the hot phosphoric acid solution and soaked for a preset time t3, the preset time t3 can be obtained according to the etching rate v3 of the wet etching process and the width W of the second charge storage layer 702, that is, t3 is W/v 3. The hot phosphoric acid solution enters the 3D NAND memory from the at least one channel hole 50 and selectively etches the charge storage layer 70, and since the width of the first charge storage layer 701 is greater than that of the second charge storage layer 702, under the same etching time, the second charge storage layer 702 is completely removed, a portion of the first charge storage layer 701 is removed, and the remaining portion of the first charge storage layer 701 still covers the sidewall of the first blocking layer 601 to form the target charge storage layer 703.
Wherein the volume fraction range of the hot phosphoric acid solution is 85-88%, and the temperature range of the hot phosphoric acid solution is 155-165 ℃.
In some other embodiments, the 3D NAND memory may be completely immersed in a hydrofluoric acid solution, and the predetermined-sized portion of the second sacrificial layer 30 and the predetermined-sized portion of the first sacrificial layer 202 may be removed by hydrofluoric acid etching.
In other embodiments, the charge storage layer 70 may be etched by a dry etching process, and specifically, the 3D NAND memory is placed in a reaction chamber of an ICP (inductively coupled plasma) apparatus, and a fluorine-containing gas, for example, CHF3The plasma generated by the apparatus and the fluorine-containing gas act together to etch away the second charge storage layer 702 and a portion of the at least one first charge storage layer 701.
Referring to fig. 9, fig. 9 is a schematic cross-sectional view of a 3D NAND memory after forming a barrier layer. As shown in fig. 9, in some embodiments, before the forming of the charge storage layer 70, the method for manufacturing the 3D NAND memory further includes: a barrier layer 60 is deposited from the at least one channel hole 50, and the barrier layer 60 includes at least one first barrier layer 601 covering the sidewall of the first sacrificial layer 202 and at least one second barrier layer 602 covering the sidewall of the second sacrificial layer 30. The depositing of the charge storage layer 70 from the at least one channel hole 50 includes at least one first charge storage layer 701 covering the sidewall of the first sacrificial layer 202 and at least one second charge storage layer 702 covering the sidewall of the second sacrificial layer 30, including: the charge storage layer 70 is deposited from the at least one channel hole 50, and the charge storage layer 70 includes at least one first charge storage layer 701 covering the sidewall of the first blocking layer 601 and at least one second charge storage layer 702 covering the sidewall of the second blocking layer 602.
The barrier layer 60 may be formed by a chemical vapor deposition process or an atomic layer deposition process, and specifically, the 3D NAND memory is placed in a reaction chamber of a vertical furnace tube, and TEOS (tetraethylorthosilicate) and a carrier gas N are introduced into the reaction chamber2At a preset time t4, TEOS decomposes to generate silicon dioxide, which is uniformly deposited in the at least one channel hole 50 and covers the sidewalls of the first sacrificial layer 202 and the second sacrificial layer 30 to form a first barrier layer 601 and a second barrier layer 602, respectively, and the thicknesses of the first barrier layer 601 and the second barrier layer 602 are the same.
The predetermined time T4 can be calculated according to the deposition rate v4 of the silicon dioxide and the deposition thickness T2 of the silicon dioxide, that is, T4 is T2/v4, wherein the deposition thickness T2 of the silicon dioxide is less than half of the thickness of the second sacrificial layer 30, so that when the silicon dioxide is deposited in the fourth groove 2013, the silicon dioxide covers the inner wall of the fourth groove 2013 and does not fill the fourth groove 2013, and therefore, when the charge storage layer 70 is formed, the silicon nitride can be deposited in the fourth groove 2013 to fill the fourth groove 2013.
Referring to fig. 9 again, in some embodiments, the blocking layer 60 further includes at least one third blocking layer 603, the third blocking layer 603 covers a sidewall of the first insulating layer 201, a process of forming the third blocking layer 603 may be performed simultaneously with the above-described process of forming the first blocking layer 601 and the second blocking layer 602, the charge storage layer 70 further includes at least one third charge storage layer 705 covering the third blocking layer 603, and the process of forming the third charge storage layer 705 may be performed simultaneously with the above-described process of forming the first charge storage layer 701 and the second charge storage layer 702.
Referring to fig. 10, fig. 10 is a schematic cross-sectional structure diagram of the 3D NAND memory after the third charge storage layer 705 is removed. As shown in fig. 10, when the charge storage layer 70 further includes at least one third charge storage layer 705, the method for manufacturing the 3D NAND memory further includes etching to remove the at least one third charge storage layer 705, wherein the process of etching to remove the third charge storage layer 705 and the process of etching to remove the second charge storage layer 702 may be performed simultaneously.
Referring to fig. 11 to 17 together, fig. 11 is a flowchart illustrating a method for manufacturing a 3D NAND memory according to another embodiment of the present application, and fig. 12 to 17 are schematic cross-sectional structures of the 3D NAND memory corresponding to the steps in fig. 11. As shown in fig. 11, in some embodiments, the method of manufacturing a 3D NAND memory further includes:
s110: as shown in fig. 12, a tunneling layer 80 is deposited from the at least one channel hole 50, and the tunneling layer 80 includes at least one first tunneling layer 801 covering the sidewall of the target charge storage layer 703 and a second tunneling layer 802 covering the sidewall of the second blocking layer 602.
S111: as shown in fig. 13, a polysilicon channel layer 85 is deposited from the at least one channel hole 50, and the polysilicon channel layer 85 includes at least a first polysilicon channel layer 851 covering the sidewall of the first tunneling layer 801 and a second polysilicon channel layer 852 covering the sidewall of the second tunneling layer 802.
S112: as shown in fig. 14, an oxide layer 90 is deposited from within the at least one channel hole 50 to cover the sidewalls of the polysilicon channel layer 85.
S113: as shown in fig. 15, a polysilicon plug 95 is formed overlying the top of the oxide layer 90.
S114: as shown in fig. 16, the at least one first sacrificial layer 202 and the second sacrificial layer 30 are etched away to form at least one first groove 2021 and a second groove 301, respectively.
S115: as shown in fig. 17, at least one first conductive layer 2022 and at least one second conductive layer 302 are formed by filling conductive materials in the at least one first recess 2021 and the second recess 301, respectively, to form at least one control gate layer 11 and at least one top selection gate layer 12, respectively, where the control gate layer 11 includes the first conductive layer 2022, a first blocking layer 601, a target charge storage layer 703, a first tunneling layer 801, and a first polysilicon channel layer 851, and the top selection gate layer 12 includes the second conductive layer 302, a second blocking layer 602, a second tunneling layer 802, and a second polysilicon channel layer 852.
The tunneling layer 80 may be a silicon dioxide layer, the oxide layer 90 may be a silicon dioxide layer, and the conductive material may be tungsten.
The tunneling layer 80, the polysilicon channel layer 85, the oxide layer 90, and the polysilicon plug 95 may be formed by a chemical vapor deposition process or an atomic layer deposition process.
In some embodiments, the tunneling layer 80 further includes at least one third tunneling layer covering the sidewall of the third blocking layer 603, and the polysilicon channel layer 85 includes at least one third polysilicon channel layer covering the sidewall of the third tunneling layer. The process of forming the third tunneling layer may be performed simultaneously with the process of forming the first tunneling layer 801 and the second tunneling layer 802, and the process of forming the third polysilicon channel layer may be performed simultaneously with the process of forming the first polysilicon channel layer 851 and the second polysilicon channel layer 852.
According to the manufacturing method of the 3D NAND memory provided by the embodiment of the application, the second charge storage layer 702 covering the sidewall of the second sacrificial layer 30 is removed by etching, and the top select gate layer 12 without a charge storage layer is formed, so that when the top select gate is turned on or turned off, electrons in the second polysilicon channel layer 852 of the top select gate layer 12 do not migrate to the charge storage layer, and the threshold voltage of the top select gate is stabilized, so that the top select gate has stable control capability, and the data read-write capability of the 3D NAND memory is stabilized, and the first charge storage layer 701 covering the sidewall of the first sacrificial layer 202 is retained, so that the data storage function of the control gate layer 11 including the first charge storage layer 701 is not affected.
Referring to fig. 18, fig. 18 is a schematic cross-sectional structure diagram of a 3D NAND memory 100 according to an embodiment of the present application. As shown in fig. 18, the 3D NAND memory 100 includes: a substrate 10, at least one control gate layer 11, a top select gate layer 12, at least one first insulating layer 201, a second insulating layer 40, and at least one channel hole 50, each control gate layer 11 comprising a first conductive layer 2022, a target charge storage layer 703, the top select gate layer 12 comprising a second conductive layer 302.
The first insulating layers 201 and the first conductive layers 2022 are alternately stacked on the substrate 10, the number of the at least one first insulating layer 201 is one more than that of the first conductive layers 2022 of the at least one control gate layer 11, and the first insulating layers 201 protrude from the first conductive layers 2022 in a direction perpendicular to the stacking direction.
The second conductive layer 302 is stacked on the first insulating layer 201 on a side away from the control gate layer 11, wherein a thickness of the second conductive layer 302 is greater than a thickness of the first conductive layer 2022, the thicknesses of the second conductive layer 302 and the first conductive layer 2022 are dimensions of the second conductive layer 302 and the first conductive layer 2022 in a stacking direction, and the first insulating layer 201 adjacent to the second conductive layer 302 protrudes from the second conductive layer 302 in a direction perpendicular to the stacking direction.
The second insulating layer 40 covers one side of the second conductive layer 302, which is far away from the first insulating layer 201, and the second insulating layer 40 protrudes from the second conductive layer 302 along a direction perpendicular to the stacking direction.
The at least one channel hole 50 penetrates the second insulating layer 40, the second conductive layer 302, the first insulating layer 201, and the first conductive layer 2022 in the stacking direction of the first insulating layer 201 and the first conductive layer 2022, and extends to the substrate 10.
The target charge storage layer 703 covers a sidewall of the first conductive layer 2022 exposed to the at least one channel hole 50.
Referring to fig. 18 again, in some embodiments, each control gate layer 11 further includes a first blocking layer 601, a first tunneling layer 801 and a first polysilicon channel layer 851, wherein the first blocking layer 601 covers sidewalls of the first conductive layer 2022 exposed to the at least one channel hole 50 and between the sidewalls of the first conductive layer 2022 and the target charge storage layer 703, and the first tunneling layer 801 and the first polysilicon channel layer 851 sequentially cover sidewalls of the target charge storage layer 703.
The top select gate layer 12 further includes a second blocking layer 602, a second tunneling layer 802, and a second polysilicon channel layer 852, wherein the second blocking layer 602, the second tunneling layer 802, and the second polysilicon channel layer 852 sequentially cover sidewalls of the second conductive layer 302 exposed to the at least one channel hole 50.
The oxide layer 90 covers sidewalls of the first polysilicon channel layer 851 and the second polysilicon channel layer 852 exposed to the at least one channel hole 50.
The 3D NAND memory 100 further includes an oxide layer 90 and a polysilicon plug 95, wherein the oxide layer 90 covers sidewalls of the first polysilicon channel layer 851 and the second polysilicon channel layer 852 exposed to the at least one channel hole 50, and the polysilicon plug 95 is stacked on top of the oxide layer 90.
Wherein the first insulating layer 201, the second insulating layer 40, and the oxide layer 90 may be silicon dioxide layers.
The first blocking layer 601, the second blocking layer 602, the first tunneling layer 801, and the second tunneling layer 802 may be silicon dioxide layers.
The target charge storage layer 703 may be a silicon nitride layer.
Both the first conductive layer 2022 and the second conductive layer 302 can be tungsten layers.
In some embodiments, the 3D NAND memory 100 further includes at least one third blocking layer 603, at least one third tunneling layer 803, and at least one third polysilicon channel layer 853, wherein the third blocking layer 603 covers sidewalls of the first insulating layer 201 exposed to the at least one channel hole 50, the third tunneling layer 803 covers sidewalls of the third blocking layer 603, and the third polysilicon channel layer 853 covers sidewalls of the third tunneling layer 803.
The top select gate layer 12 of the 3D NAND memory 100 provided by the present application does not include a charge storage layer, so that when the top select gate is turned on or off, electrons in the second polysilicon channel layer 852 of the top select gate layer 12 do not migrate to the charge storage layer, and the threshold voltage of the top select gate is stable, so that the top select gate has stable control capability, and the data read-write capability of the 3D NAND memory 100 is stable.
The 3D NAND memory 100 provided in the above embodiments corresponds to the above-described method for manufacturing the 3D NAND memory, and the relevant points can be referred to each other.
It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The foregoing is an implementation of the embodiments of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the embodiments of the present application, and these modifications and decorations are also regarded as the protection scope of the present application.

Claims (10)

1. A method of manufacturing a 3D NAND memory, the method comprising:
providing a substrate;
forming a stack layer on the substrate, wherein the stack layer comprises at least one first insulating layer and at least one first sacrificial layer, the first insulating layer and the first sacrificial layer are formed by alternately stacking, and the number of the first insulating layers is one more than that of the first sacrificial layers;
forming a second sacrificial layer on one side of the stacked layers far away from the substrate, wherein the thickness of the second sacrificial layer is larger than that of the first sacrificial layer;
forming a second insulating layer on one side of the second sacrificial layer far away from the stacking layer;
etching the second insulating layer, the second sacrificial layer and the stacked layer along a stacking direction to form at least one channel hole penetrating through the second insulating layer, the second sacrificial layer and the stacked layer, so that the second insulating layer, the second sacrificial layer, the at least one first insulating layer and the at least one first sacrificial layer have side walls exposed out of the at least one channel hole;
etching and removing a preset size part of the second sacrificial layer and a preset size part of the at least one first sacrificial layer from the at least one channel hole, so that the side walls of the second sacrificial layer and each first sacrificial layer are recessed inwards to have the same size;
depositing and forming a charge storage layer from the at least one channel hole, wherein the charge storage layer comprises at least one first charge storage layer covering the side wall of the first sacrificial layer and a second charge storage layer covering the side wall of the second sacrificial layer, and the width of the first charge storage layer is larger than that of the second charge storage layer, so that the side wall of the first charge storage layer protrudes out of the side wall of the second charge storage layer; and
and etching the charge storage layer from the at least one channel hole, and simultaneously removing the second charge storage layer and part of the at least one first charge storage layer to form at least one target charge storage layer, wherein the target charge storage layer covers the side wall of the first sacrificial layer.
2. The method of claim 1, wherein the etching away the pre-sized portion of the second sacrificial layer and the pre-sized portion of the at least one first sacrificial layer from within the at least one trench hole comprises:
and etching and removing the preset size part of the second sacrificial layer and the preset size part of the at least one first sacrificial layer by using a wet etching process.
3. The method of claim 2, wherein the etching away the predetermined-sized portion of the second sacrificial layer and the predetermined-sized portion of the at least one first sacrificial layer using a wet etching process comprises:
and soaking the 3D NAND memory in a hot phosphoric acid solution for a preset time, and etching the second sacrificial layer and the at least one first sacrificial layer through the hot phosphoric acid.
4. The method of claim 1, wherein said etching the charge storage layer from within the at least one trench hole, removing the second charge storage layer and a portion of the at least one first charge storage layer comprises:
and etching the charge storage layer by using a wet etching process, and removing the second charge storage layer and part of the at least one first charge storage layer.
5. The method of claim 4, wherein the etching the charge storage layer using a wet etching process to remove the second charge storage layer and a portion of the at least one first charge storage layer comprises:
and soaking the 3D NAND memory in a hot phosphoric acid solution for a preset time, and etching the second charge storage layer and the at least one first charge storage layer through the hot phosphoric acid.
6. The method of claim 1, wherein prior to said forming a charge storage layer, said method further comprises:
depositing and forming a barrier layer from the at least one channel hole, wherein the barrier layer comprises at least one first barrier layer covering the side wall of the first sacrificial layer and at least one second barrier layer covering the side wall of the second sacrificial layer;
the depositing from the at least one channel hole forms a charge storage layer, the charge storage layer comprises at least one first charge storage layer covering the side wall of the first sacrificial layer and a second charge storage layer covering the side wall of the second sacrificial layer, and the depositing comprises:
and depositing and forming a charge storage layer from the at least one channel hole, wherein the charge storage layer comprises at least one first charge storage layer covering the side wall of the first blocking layer and at least one second charge storage layer covering the side wall of the second blocking layer.
7. The method of claim 6, wherein the blocking layer further comprises at least one third blocking layer overlying a sidewall of the first insulating layer, wherein the charge storage layer further comprises at least one third charge storage layer overlying a sidewall of the third blocking layer, and wherein the method further comprises:
and etching to remove the at least one third charge storage layer.
8. The method of claim 6, further comprising:
depositing a tunneling layer from the at least one trench hole, wherein the tunneling layer comprises at least one first tunneling layer covering the side wall of the target charge storage layer and at least one second tunneling layer covering the side wall of the second blocking layer;
depositing and forming a polysilicon channel layer from the at least one channel hole, wherein the polysilicon channel layer comprises at least one first polysilicon channel layer covering the side wall of the first tunneling layer and at least one second polysilicon channel layer covering the side wall of the second tunneling layer;
depositing an oxide layer covering the side wall of the polysilicon channel layer from the at least one channel hole;
forming a polysilicon plug covering the top of the oxide layer;
etching and removing the at least one first sacrificial layer and the second sacrificial layer to form at least one first groove and at least one second groove respectively; and
filling a conductive material in the at least one first groove and the second groove to form at least one first conductive layer and at least one second conductive layer respectively so as to form at least one control gate layer and at least one top selection gate layer respectively, wherein the control gate layer comprises the first conductive layer, a first blocking layer, a target charge storage layer, a first tunneling layer and a first polysilicon channel layer, and the top selection gate layer comprises the second conductive layer, a second blocking layer, a second tunneling layer and a second polysilicon channel layer.
9. A3D NAND memory, wherein the 3D NAND memory comprises:
the semiconductor device comprises a substrate, a top selection gate layer, at least one control gate layer, at least one first insulating layer, at least one channel hole and a second insulating layer;
each control gate layer comprises a first conductive layer and a target charge storage layer;
the first insulating layers and the first conducting layers are alternately stacked on the substrate, the number of layers of the at least one first insulating layer is one more than that of the first conducting layers of the at least one control gate layer, and the first insulating layers protrude out of the first conducting layers in a direction perpendicular to the stacking direction;
the top select gate layer comprises a second conductive layer;
the second conductive layer is arranged on one side, far away from the control gate layer, of the first insulating layer in a stacked mode, wherein the thickness of the second conductive layer is larger than that of the first conductive layer, and the first insulating layer adjacent to the second conductive layer protrudes out of the second conductive layer in a direction perpendicular to the stacking direction;
the second insulating layer covers one side, far away from the first insulating layer, of the second conducting layer, and protrudes out of the second conducting layer along the direction perpendicular to the stacking direction;
the channel hole penetrates through the second insulating layer, the second conducting layer, the first insulating layer and the first conducting layer along the stacking direction;
the charge storage layer covers a side wall of the first conductive layer exposed out of the at least one channel hole.
10. The 3D NAND memory of claim 9 wherein each control gate layer further comprises a first blocking layer, a first tunneling layer and a first polysilicon channel layer, wherein the first blocking layer covers a sidewall of the first conductive layer exposed to the at least one channel hole and between the sidewall of the first conductive layer and the charge storage layer, and the first tunneling layer and the first polysilicon channel layer in turn cover a sidewall of the target charge storage layer;
the top selection gate layer further comprises a second blocking layer, a second tunneling layer and a second polysilicon channel layer, wherein the second blocking layer, the second tunneling layer and the second polysilicon channel layer sequentially cover the side wall of the second conducting layer exposed out of the at least one channel hole;
the 3D NAND memory further comprises an oxide layer and a polysilicon plug, wherein the oxide layer covers the first polysilicon channel layer and the second polysilicon channel layer and is exposed out of the side wall of the at least one channel hole, and the polysilicon plug is arranged on the top of the oxide layer in a laminated mode.
CN202111085087.3A 2021-09-15 2021-09-15 3D NAND memory and manufacturing method thereof Pending CN113851484A (en)

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