CN113851482A - Three-dimensional memory and preparation method thereof - Google Patents
Three-dimensional memory and preparation method thereof Download PDFInfo
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- CN113851482A CN113851482A CN202111107935.6A CN202111107935A CN113851482A CN 113851482 A CN113851482 A CN 113851482A CN 202111107935 A CN202111107935 A CN 202111107935A CN 113851482 A CN113851482 A CN 113851482A
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
The application provides a three-dimensional memory and a preparation method thereof. The three-dimensional memory comprises a substrate, a first stacking structure and a second stacking structure which are sequentially stacked on the substrate; the first stacking structure is arranged on the stacking surface of the substrate, the first stacking structure is provided with a first sub-channel hole which penetrates through the first stacking structure and is in contact with the substrate, and the thickness of the first stacking structure is a first thickness; the second stacking structure is arranged on the surface, deviating from the substrate, of the first stacking structure, the second stacking structure is provided with a second sub-channel hole which penetrates through the second stacking structure and is communicated with the first sub-channel hole, the thickness of the second stacking structure is a second thickness, and the second thickness is smaller than the first thickness. The three-dimensional memory solves the problems that in the prior art, due to the increase of the number of stacked layers, the inclination degree of an upper-layer channel hole is more and more serious, the upper-layer channel hole cannot be aligned with a lower-layer channel hole, and then, when the bottom of the channel hole is etched, the side wall is damaged, and the electrical performance of the three-dimensional memory is affected.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory and a preparation method thereof.
Background
At present, in the process of manufacturing a three-dimensional memory, an etching process of a Channel Hole (CH) is one of the key processes in the processes related to the three-dimensional memory, and as the number of stacked layers increases, the aspect ratio of the Channel hole etching is further increased, so as to facilitate etching the Channel hole, the Channel hole is etched by two stacking processes. In the existing two-time forming process, the inclination of the upper-layer channel hole can influence the alignment with the lower-layer channel hole, and along with the increase of the number of stacked layers, the inclination degree of the upper-layer channel hole is more and more serious, so that the upper-layer channel hole cannot be aligned with the lower-layer channel hole, and further, when the bottom of the channel hole is etched in the subsequent process, the side wall damage can be caused, and the electrical performance of the three-dimensional memory is influenced.
Disclosure of Invention
In view of this, the application provides a three-dimensional memory and a manufacturing method thereof, so as to solve the problem that in the prior art, due to the increase of the number of stacked layers, the inclination degree of an upper-layer channel hole is more and more severe, so that the upper-layer channel hole cannot be aligned with a lower-layer channel hole, and further, when the bottom of the channel hole is subsequently etched, side wall damage is caused, and the electrical performance of the three-dimensional memory is affected.
In a first aspect, the present application provides a three-dimensional memory, including a substrate, a first stacked structure and a second stacked structure sequentially stacked on the substrate;
the first stacking structure is arranged on the stacking surface of the substrate and provided with a first sub-channel hole which penetrates through the first stacking structure and is in contact with the substrate, and the thickness of the first stacking structure is a first thickness;
the second stacking structure is arranged on the surface, deviating from the substrate, of the first stacking structure, the second stacking structure is provided with a second sub-channel hole which penetrates through the second stacking structure and is communicated with the first sub-channel hole, the thickness of the second stacking structure is a second thickness, and the second thickness is smaller than the first thickness.
In one embodiment, the ratio of the first thickness to the second thickness is between 1.1 and 1.3.
In one embodiment, the number of stacked layers of the first stacked structure is the same as the number of stacked layers of the second stacked structure.
In one embodiment, the first stacked structure includes first insulating layers and first sacrificial layers alternately stacked.
In one embodiment, the second stacked structure includes second insulating layers and second sacrificial layers alternately stacked.
In an embodiment, the thickness of the first insulating layer is a third thickness, the thickness of the second insulating layer is a fourth thickness, and the third thickness is equal to the fourth thickness.
In an embodiment, the thickness of the first sacrificial layer is a fifth thickness, the thickness of the second sacrificial layer is a sixth thickness, and the sixth thickness is smaller than the fifth thickness.
In one embodiment, the thickness range of the fifth thickness is
The thickness range of the sixth thickness is
In a second aspect, the present application further provides a method for manufacturing a three-dimensional memory, where the method for manufacturing a three-dimensional memory includes:
providing a substrate, wherein the substrate has a stacking face;
forming a first stacked structure on the stacked surface of the substrate, wherein the thickness of the first stacked structure is a first thickness;
etching the first stacked structure to form a first sub-channel hole penetrating through the first stacked structure;
forming a second stacked structure on a surface of the first stacked structure facing away from the substrate, wherein a thickness of the second stacked structure is a second thickness, and the second thickness is smaller than the first thickness;
and etching the second stacking structure at the position of the second stacking structure, which is aligned with the first sub-channel hole, so as to form the second sub-channel hole penetrating through the second stacking structure, wherein the bottom of the second sub-channel hole is communicated with the top of the first sub-channel hole.
In one embodiment, after the "etching the first stacked structure to form the first sub-channel hole penetrating through the first stacked structure" and before the "forming the second stacked structure on the surface of the first stacked structure facing away from the substrate", the method for manufacturing the three-dimensional memory includes:
and forming a polycrystalline silicon sacrificial layer in the first sub-channel hole.
In one embodiment, after the "etching the second stacked structure at a position of the second stacked structure aligned with the first sub-channel hole to form the second sub-channel hole penetrating through the second stacked structure", the method for manufacturing the three-dimensional memory includes:
removing the polysilicon sacrificial layer to enable the second sub-channel hole to be communicated with the first sub-channel hole to form a channel hole;
and depositing a blocking layer, a storage layer, a tunneling layer and a channel layer on the bottom and the side wall of the channel hole in sequence.
The three-dimensional memory of this application sets up the sub-channel hole of second through setting up first sub-channel hole in first stacked structure in the second stacked structure, can make the sub-channel hole of second and first sub-channel hole intercommunication and form the channel hole that link up. Compared with the channel holes formed by single etching with high stacking thickness, the stacking thickness of the first stacking structure and the second stacking structure formed by stacking respectively is low, on one hand, the etching depth required for etching the first sub-channel hole and the second sub-channel hole can be correspondingly reduced, and further the etching depth-to-width ratio of the first sub-channel hole and the second sub-channel hole is reduced, so that the contour distortion of the first sub-channel hole and the second sub-channel hole is improved, and the contour form of the channel holes is ensured to be normal after the first sub-channel hole and the second sub-channel hole are communicated to form the channel holes. On the other hand, the thickness of the second stacking structure is smaller than that of the first stacking structure, which is equivalent to the reduction of the etching depth of the second sub-channel hole, so that the inclination risk of the second sub-channel hole is greatly reduced, the inclination of the subsequently formed channel hole is improved, the damage to the side wall caused by the subsequent etching of the bottom of the channel hole is avoided, and the electrical performance of the three-dimensional memory and the yield of the three-dimensional memory are improved.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic cross-sectional view of a three-dimensional memory according to an embodiment of the present disclosure;
FIG. 2 is a cross-sectional view of a three-dimensional memory of a conventional structure;
fig. 3 is a schematic flowchart of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure;
fig. 4 is a schematic cross-sectional view illustrating a first stacked structure of a three-dimensional memory according to an embodiment of the present disclosure;
FIG. 5 is a schematic cross-sectional view of a first sub-channel hole of a three-dimensional memory according to an embodiment of the present disclosure;
fig. 6 is a schematic cross-sectional view of the first sub-channel hole shown in fig. 5, wherein an epitaxial layer is disposed at the bottom of the first sub-channel hole;
FIG. 7 is a schematic cross-sectional view of the first sub-channel hole shown in FIG. 5, wherein an oxide layer is formed on the surface of the epitaxial layer;
FIG. 8 is a cross-sectional view of the first sub-channel hole of FIG. 5 filled with a sacrificial layer of polysilicon;
fig. 9 is a schematic cross-sectional view illustrating a second stacked structure of a three-dimensional memory according to an embodiment of the present application;
FIG. 10 is a cross-sectional view of a second sub-channel hole of the second stacked structure shown in FIG. 8;
FIG. 11 is a cross-sectional view of a channel hole of a three-dimensional memory according to an embodiment of the present disclosure;
FIG. 12 is a schematic cross-sectional view of a blocking layer, a memory layer, a tunneling layer and a channel layer sequentially deposited on the wall of the trench hole shown in FIG. 11.
Detailed Description
Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it is to be understood that the invention may be practiced otherwise than as specifically described and that the invention is therefore not limited to the following embodiments.
The Three-dimensional (3D) stacking technology can form a Three-dimensional integrated and signal-connected 3D solid memory chip in a vertical direction by stacking chips or structures with different functions through micro-machining technologies such as stacking or hole interconnection. Three-dimensional (3D) memory is a technology that is used to arrange memory cells three-dimensionally over a substrate to increase the storage density of the memory.
The three-dimensional (3D) memory includes a 3D NOR (NOR) memory and a 3D NAND (3D NAND) memory. Compared with a 3D NOR memory, the 3D NAND memory has the advantages of high writing speed, simple erasing operation, small volume, large capacity and high storage density per unit area, thereby realizing smaller memory cells to achieve higher storage density. Therefore, the three-dimensional memory adopting the NAND structure is widely used.
In a three-dimensional memory employing a NAND structure, a memory array includes a core (core) region having a channel structure. The Channel structure is formed in a Channel Hole (CH) vertically penetrating through stacked layers (stacks) of the three-dimensional memory. The trench hole of the stacked layers is generally formed by a single etching, but the number of layers (tier) of the three-dimensional memory is increasing to improve memory density and capacity, for example, the number of layers of the stacked layers is increasing from 64 layers to 96 layers, 128 layers or more, resulting in further increase of Aspect Ratio (AR) of trench hole etching, and with this trend, difficulty of single etching to form the trench hole is increasing, and control of Critical Dimension (CD) and defects is very difficult, resulting in low production efficiency and increase of cost.
Therefore, in the fabrication process of the three-dimensional memory, the stack layer is often divided into a plurality of stacks (decks) stacked on top of each other. For example, in a Dual stack process, a lower channel hole is etched after a lower stack is formed, an upper stack is stacked and an upper channel hole is etched, and then a channel structure filling the upper and lower channel holes is formed. The upper and lower stacks stacked together require alignment (Overlay) to align the centerlines of the upper and lower channel holes.
However, the most important factor affecting the alignment of the upper and lower channel holes is the inclination of the upper channel hole, and the inclination degree of the upper channel hole is related to the depth of the upper channel hole, and the correlation is exponential, that is, as the number of layers of the stacked layers increases, the inclination degree of the upper channel hole becomes more serious, so that the upper channel hole is difficult to align with the lower channel hole, and further, when the bottom of the channel hole is subsequently etched, the side wall of the channel hole is damaged, and the electrical performance of the three-dimensional memory is affected.
In view of the above, referring to fig. 1, the present application provides a three-dimensional memory 100, wherein the three-dimensional memory 100 includes a substrate 10, a first stacked structure 20 and a second stacked structure 30 sequentially stacked on the substrate 10.
The first stacked structure 20 is disposed on the stacking surface 101 of the substrate 10, the first stacked structure 20 is disposed with a first sub-channel hole 21 penetrating the first stacked structure 20 and contacting the substrate 10, and a thickness of the first stacked structure 20 is a first thickness D1.
The second stacked structure 30 is disposed on a surface of the first stacked structure 20 away from the substrate 10, the second stacked structure 30 has a second sub-channel hole 31 penetrating through the second stacked structure 30 and communicating with the first sub-channel hole 21, a thickness of the second stacked structure 30 is a second thickness D2, and the second thickness D2 is smaller than the first thickness D1.
It is understood that the number of stacking layers of the first stacking structure 20 and the second stacking structure 30 is determined by the number of memory cells required to be formed in the vertical direction, and may be designed according to actual memory requirements. The number of stacked layers of the first stacked structure 20 and the second stacked structure 30 refers to the number of layers of the first stacked structure 20 and the second stacked structure 30 during final molding. In the embodiment of the present application, the number of stacked layers of the first stacked structure 20 is the same as that of the second stacked structure 30. Of course, in other embodiments, the number of stacking layers of the first stacking structure 20 may be different from the number of stacking layers of the second stacking structure 30, and those skilled in the art can design the stacking structures according to practical situations, which is not specifically limited in this application.
In the embodiment of the present application, the second stacked structure 30 is disposed on the first stacked structure 20, that is, the second sub-channel hole 31 is a hole structure located at an upper position relative to the first sub-channel hole 21, and the first sub-channel hole 21 and the second sub-channel hole 31 are both part of a channel hole (not shown) for forming a memory cell string. In other words, the second sub-channel hole 31 needs to be aligned with the first sub-channel hole 21, that is, the center line of the first sub-channel hole 21 is aligned with the center line of the first sub-channel hole 21 to form a through channel hole. However, in the actual alignment process, the second sub-channel hole 31 may be inclined due to the increase of the number of stacked layers. The inclination degree of the second sub-channel hole 31 is related to the depth of the second sub-channel hole 31 in an exponential relationship, that is, as the number of stacked layers of the second stacked structure 30 increases, the inclination degree of the second sub-channel hole 31 becomes more severe, which may cause difficulty in aligning the second sub-channel hole 31 with the first sub-channel hole 21.
It is understood that the second sub-channel hole 31 is disposed in the second stack structure 30 and penetrates the second stack structure 30, and the second stack structure 30 is formed by continuously stacking a plurality of layers, that is, the depth of the second sub-channel hole 31 is determined by the sum of the thicknesses of the plurality of layers of the second stack structure 30, and the sum of the thicknesses of the plurality of layers is the thickness of the second stack structure 30, that is, the depth of the second sub-channel hole 31 is determined by the thickness of the second stack structure 30. Since the increase of the number of stacked layers is substantially the increase of the stacked thickness, that is, the inclination degree of the second sub-channel hole 31 is related to the thickness of the second stacked structure 30, the inclination degree becomes more and more serious as the thickness of the second stacked structure 30 increases.
Thus, by providing the first sub-channel hole 21 in the first stacked structure 20 and providing the second sub-channel hole 31 in the second stacked structure 30, the second sub-channel hole 31 can be made to communicate with the first sub-channel hole 21 to form a through channel hole. Compared with the channel holes formed by single etching with high stacking thickness, the stacking thickness of the first stacking structure 20 and the second stacking structure 30 formed by stacking respectively is low, so that the etching depth required for etching the first sub-channel hole 21 and the second sub-channel hole 31 can be correspondingly reduced, the etching depth-to-width ratio of the first sub-channel hole 21 and the second sub-channel hole 31 can be further reduced, the contour distortion of the first sub-channel hole 21 and the second sub-channel hole 31 can be improved, and the normal contour form of the channel holes can be ensured after the first sub-channel hole 21 and the second sub-channel hole 31 are communicated to form the channel holes.
In addition, compared with the second stacked structure 30 having the same thickness as the first stacked structure 20, the second stacked structure 30 has a thickness smaller than that of the first stacked structure 20 on the basis of the same number of stacked layers as the first stacked structure 20, which is equivalent to reducing the etching depth of the second sub-channel hole 31, thereby greatly reducing the risk of inclination of the second sub-channel hole 31, improving the inclination of the subsequently formed channel hole, avoiding the damage of the sidewall caused by the subsequent etching of the bottom of the channel hole, and improving the electrical performance of the three-dimensional memory 100 and the yield of the three-dimensional memory 100.
It should be noted that, as shown in fig. 2, in the conventional two-stack structure, the thickness of the upper-layer stack structure is a2, the thickness of the lower-layer stack structure is a1, and a2 is a1, after the optimization of the embodiment of the present application, as shown in fig. 1, the thickness of the first stack structure 20 located at the lower layer is a first thickness D1, the thickness of the second stack structure 30 located at the upper layer is a second thickness D2, and the first thickness D1 is equal to a1, the second thickness D2 is smaller than a2, and the second thickness D2 is smaller than the first thickness D1. In other words, in the embodiment of the present application, compared to the conventional two-stack structure design, the thickness of the second stack structure 30 is directly reduced without changing the number of stacked layers, and as the thickness of the second stack structure 30 is reduced, the risk of the second sub-channel hole 31 being inclined is also reduced, thereby facilitating the alignment of the second sub-channel hole 31 and the first sub-channel hole 21.
Further, the ratio of the first thickness D1 to the second thickness D2 is between 1.1 and 1.3, so that the ratio of the thicknesses of the first stacked structure 20 and the second stacked structure 30 satisfying this relationship can effectively reduce the risk of inclination of the second sub-channel hole 31 when the second sub-channel hole 31 is aligned with the first sub-channel hole 21, and the second sub-channel hole 31 can be aligned with the first sub-channel hole 21 along a predetermined track, thereby improving the problems of poor appearance and poor electrical performance of the subsequently formed channel hole.
It is understood that, since the depth of the first sub-channel hole 21 depends on the thickness of the first stacked structure 20, the depth of the second sub-channel hole 31 depends on the thickness of the second stacked structure 30. A ratio of the first thickness D1 of the first stacked structure 20 to the second thickness D2 of the second stacked structure 30 satisfies 1.1-1.3, where the ratio includes endpoints. The ratio of the depth of the first sub-channel hole 21 to the depth of the second sub-channel hole 31 also satisfies 1.1 to 1.3, where the ratio includes endpoints.
The principle of the thickness reduction of the second stack structure 30 will be described in detail below.
In the embodiment of the present application, the substrate 10 is a semiconductor substrate 10. For example, the substrate 10 may be a single crystal Silicon (Si) substrate 10, a single crystal Germanium (Ge) substrate 10, a Silicon On Insulator (SOI) substrate 10, or a Germanium On Insulator (GOI) substrate 10, or the like. The substrate 10 may also be a P-type doped substrate 10 or an N-type doped substrate 10. Suitable materials can be selected as the substrate 10 according to actual requirements, and the present application is not limited to this. Of course, in other embodiments, the material of the substrate 10 may also be a semiconductor or a compound including other elements. For example, the substrate 10 may be a gallium arsenide (GaAs) substrate 10, an Indium phosphide (InP) substrate 10, a silicon carbide (SiC) substrate 10, or the like.
Further, the substrate 10 has a stacking surface 101, and the stacking surface 101 is used for forming a stacking structure, in the embodiment of the present application, the first stacking structure 20 is disposed on the stacking surface 101 of the substrate 10. The first stacked structure 20 includes first insulating layers 22 and first sacrificial layers 23 alternately stacked. It is understood that, in the embodiment of the present application, the alternating stacking arrangement is actually an alternating stacking arrangement, i.e. a stacking relationship of "first insulating layer 22-first sacrificial layer 23-first insulating layer 22-. -" first insulating layer 22 "is formed, and the first stacking structure 20 having a plurality of layer structures is formed by the continuous alternating stacking arrangement of the first insulating layer 22 and the first sacrificial layer 23. Since the first insulating layer 22 and the first sacrificial layer 23 have different etching selectivity, the first sacrificial layer 23 as a gate sacrificial layer is removed in a subsequent process, and a space of the first sacrificial layer 23 is filled with a highly conductive material to form a gate (word line).
The material of the first insulating layer 22 may be an insulating dielectric material such as silicon oxide, aluminum oxide, hafnium oxide, or tantalum oxide, the material of the first sacrificial layer 23 may be silicon nitride, and the highly conductive material may be metal tungsten, cobalt, copper, nickel, etc., and may also be polysilicon, doped silicon, or any combination thereof. In the embodiment of the present application, the material of the first insulating layer 22 is silicon oxide, and the material of the first sacrificial layer 23 is silicon nitride.
The second stacked structure 30 is disposed on a surface of the first stacked structure 20 facing away from the substrate 10. The second stack structure 30 includes second insulating layers 32 and second sacrificial layers 33 alternately stacked. It is understood that, in the embodiment of the present application, the alternating stacking arrangement is actually an alternating stacking arrangement, i.e. a stacking relationship of "second insulating layer 32-second sacrificial layer 33-second insulating layer 32-. second insulating layer 32" is formed, and the second stacking structure 30 having a plurality of layer structures is formed by a continuous alternating stacking arrangement of the second insulating layer 32 and the second sacrificial layer 33. Since the second insulating layer 32 and the second sacrificial layer 33 have different etching selectivity, the second sacrificial layer 33 as a gate sacrificial layer is removed in a subsequent process, and a space of the second sacrificial layer 33 is filled with a highly conductive material to form a gate (word line).
The material of the second insulating layer 32 may be an insulating dielectric material such as silicon oxide, aluminum oxide, hafnium oxide, or tantalum oxide, the material of the second sacrificial layer 33 may be silicon nitride, and the highly conductive material may be metal tungsten, cobalt, copper, nickel, etc., and may also be polysilicon, doped silicon, or any combination thereof. In the embodiments of the present application, the material of the second insulating layer 32 is silicon oxide, and the material of the second sacrificial layer 33 is silicon nitride.
It is understood that in the first stacked structure 20, the number of stacked layers is substantially the sum of the number of layers of the first insulating layer 22 and the first sacrificial layer 23. Correspondingly, in the second stacked structure 30, the number of stacked layers is substantially the sum of the number of layers of the second insulating layer 32 and the second sacrificial layer 33. During the final forming of the first stacking structure 20 and the second stacking structure 30, the number of stacking layers of the first stacking structure 20 is the same as that of the second stacking structure 30, but during the forming of the first stacking structure 20 and the second stacking structure 30, the number of actually formed layers in each stacking structure is more than that during the final forming, and the extra layers are removed during the forming, which is not specifically described herein.
Further, as shown in fig. 1, the thickness of the first insulating layer 22 is a third thickness D3, the thickness of the second insulating layer 32 is a fourth thickness D4, and the third thickness D3 is equal to the fourth thickness D4.
It is understood that the first insulating layer 22 having the third thickness D3 in the first stacked structure 20 means that the thickness of most of the first insulating layers 22 is the third thickness D3, but there are still several layers of the first insulating layers 22 in the first stacked structure 20, which are different from the third thickness D3. For example, the thickness of the first insulating layer 22 closely attached to the stacking surface 101 of the substrate 10 is smaller than the third thickness D3, and the thickness of the first insulating layer 22 disposed on the first sacrificial layer 23 closest to the substrate 10 is larger than the third thickness D3, which are set in relation to the formation process of the three-dimensional memory 100, in other words, the set of the layer thicknesses is not used to limit the specific thickness and the thickness distribution of the first insulating layer 22 of the first stacked structure 20.
Correspondingly, in the second stacked structure 30, the fact that the thickness of the second insulating layer 32 is the fourth thickness D4 means that the thickness of most of the second insulating layers 32 is the fourth thickness D4, but there are still several layers of the second insulating layers 32 in the second stacked structure 30, which are not equal to the fourth thickness D4. For example, the thickness of the second insulating layer 32 in the second stacked structure 30 closely attached to the first stacked structure 20 is greater than the fourth thickness D4, the thickness of the second insulating layer 32 on the top of the second stacked structure 30 is greater than the fourth thickness D4, and the thickness of these layers is set in relation to the formation process of the three-dimensional memory 100, in other words, the thickness of these layers is not set to limit the specific thickness and thickness distribution of the second insulating layer 32 of the second stacked structure 30.
It should be understood that in the first stacked structure 20 and the second stacked structure 30, the first insulating layer 22 and the second insulating layer 32 have the same layer thickness, and the thickness thereof is not changed, and therefore, the thickness of the second stacked structure 30 is not reduced. Therefore, in order to reduce the thickness of the second stacked structure 30, the thickness of the second sacrificial layer 33 needs to be reduced.
Specifically, the thickness of the first sacrificial layer 23 is a fifth thickness D5, the thickness of the second sacrificial layer 33 is a sixth thickness D6, and the sixth thickness D6 is less than the fifth thickness D5. In the embodiment of the present application, the thickness range of the fifth thickness D5 is
The thickness range of the sixth thickness D6 is
The specific reduced thickness range value of the second sacrificial layer 33 may be defined according to actual conditions, and it is only required that the thickness of each second sacrificial layer 33 is reduced compared with the thickness of the first sacrificial layer 23, and in addition, the reduction degrees of the thicknesses of the plurality of second sacrificial layers 33 may be the same or different, and this is not specifically limited in the embodiment of the present application.
By reducing the thickness of the second sacrificial layer 33 of the second stacked structure 30, the thickness of the whole second stacked structure 30 is reduced, so that the etching depth of the second sub-channel hole 31 is reduced, the inclination degree of the second sub-channel hole 31 is effectively reduced, the second sub-channel hole 31 can be aligned with the first sub-channel hole 21, the yield of the three-dimensional memory 100 is improved, and the electrical performance of the three-dimensional memory 100 is more reliable.
Referring to fig. 3, the method for manufacturing the three-dimensional memory 100 at least includes S100, S200, S300, S400, and S500, which are described in detail below.
S100: providing a substrate, wherein the substrate has a stacking surface;
s200: forming a first stacked structure on the stacked surface of the substrate, wherein the thickness of the first stacked structure is a first thickness;
s300: etching the first stacked structure to form a first sub-channel hole penetrating through the first stacked structure;
s400: forming a second stacked structure on the surface of the first stacked structure, which is far away from the substrate, wherein the thickness of the second stacked structure is a second thickness, and the second thickness is smaller than the first thickness;
s500: and etching the second stacking structure at the position of the second stacking structure, which is aligned with the first sub-channel hole, so as to form a second sub-channel hole penetrating through the second stacking structure, wherein the bottom of the second sub-channel hole is communicated with the top of the first sub-channel hole.
Each step will be further described below.
S100: a substrate 10 is provided, wherein the substrate 10 has a stacking face 101.
Referring to fig. 4, in the embodiment of the present application, the substrate 10 is a semiconductor substrate 10. By way of example, the substrate 10 may be a single crystal silicon, single crystal germanium, silicon-on-insulator or germanium-on-insulator substrate 10, or the like. The substrate 10 may also be a P-doped or N-doped substrate 10. Suitable materials can be selected as the substrate 10 according to actual requirements, and the present application is not limited to this. Of course, in other embodiments, the material of the substrate 10 may also be a semiconductor or a compound including other elements. The substrate 10 may be, for example, a gallium arsenide, indium phosphide, or silicon carbide substrate 10, or the like.
S200: a first stacked structure 20 is formed on the stacking surface 101 of the substrate 10, wherein the thickness of the first stacked structure 20 is a first thickness D1.
As shown in fig. 4, in the embodiment of the present application, the first stacked structure 20 includes the first insulating layers 22 and the first sacrificial layers 23 alternately stacked, and the first stacked structure 20 having a multi-layer structure is formed by successive alternate deposition of the first insulating layers 22 and the first sacrificial layers 23. The first insulating layer 22 and the first sacrificial layer 23 may be deposited by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Plasma-enhanced CVD (PECVD), Sputtering (Sputtering), Metal-organic Chemical vapor deposition (MOCVD), and Atomic Layer Deposition (ALD), and the first stacked structure 20 may be formed by selecting a deposition method according to actual requirements.
It should be noted that, in the first stacked structure 20, a layer closest to the substrate 10 is a first insulating layer 22, which covers the stacked surface 101 of the substrate 10, so that the substrate 10 does not have an exposed area, which effectively prevents charged particles from entering the first sub-channel hole 21 through the substrate 10, and prevents the charged particles from generating an electronic force influence on the etching particles of the subsequent process to cause the etching particles to shift, thereby ensuring that the etching can be performed in an expected direction, and improving the yield and the working stability of the three-dimensional memory 100.
It is understood that the thickness of the first stacked structure 20 is the sum of the layer thicknesses of the multilayer structures of the first stacked structure 20, in other words, the first thickness D1 is the sum of the layer thicknesses of the first insulating layer 22 and the first sacrificial layer 23 in the first stacked structure 20.
S300: the first stacked structure 20 is etched to form a first sub-channel hole 21 penetrating the first stacked structure 20.
Referring to fig. 5, in the embodiment of the present application, the etching method for etching the first sub-channel hole 21 may be dry etching or wet etching, and the first stacked structure 20 is etched until the first sub-channel hole 21 formed by etching exposes the substrate 10. The first sub-channel hole 21 extends from a surface of the first stacked structure 20 facing away from the substrate 10 to the stacked surface 101 of the substrate 10 to expose the substrate 10, and a portion of the first sub-channel hole 21 is located in the substrate 10 but does not penetrate through the substrate 10. In other words, the first sub-channel hole 21 is a through hole penetrating the first stacked structure 20, and is a part of a channel hole (not shown) finally used for forming the memory cell string.
In step S300, a plurality of first sub-channel holes 21 may be formed simultaneously. The number, size and arrangement of the first sub-channel holes 21 are not particularly limited in the embodiments of the present application. That is, the first sub-channel holes 21 shown in fig. 5 are only examples and are not intended to limit the positions and the number of the first sub-channel holes 21.
Specifically, the first sub-channel hole 21 has an inverted trapezoid-shaped channel sidewall structure with a larger top pore diameter and a smaller bottom pore diameter than the bottom pore diameter. Of course, in other embodiments, the inclination of the sidewall of the first sub-channel hole 21 may be adjusted by adjusting the etching process parameters or by using a high aspect ratio etching process. This is not specifically limited by the present application.
The first sub-channel hole 21 is formed in the first stacked structure 20 and penetrates through the first stacked structure 20, and the first stacked structure 20 is formed by continuously stacking the first insulating layer 22 and the first sacrificial layer 23, i.e., the depth of the first sub-channel hole 21 is determined by the sum of the layer thicknesses of the first insulating layer 22 and the first sacrificial layer 23 of the second stacked structure 30, and the sum of the layer thicknesses of the first insulating layer 22 and the first sacrificial layer 23 is the thickness of the first stacked structure 20, i.e., the depth of the first sub-channel hole 21 is determined by the thickness of the second stacked structure 30.
Referring to fig. 6, in the embodiment of the present application, after the first stacked structure 20 is etched to form the first sub-channel hole 21 penetrating the first stacked structure 20, an epitaxial layer 40 is formed at the bottom of the first sub-channel hole 21. Specifically, the epitaxial layer 40 is formed at the bottom of the first sub-channel hole 21 and covers the substrate 10, which may be a silicon layer deposited at the bottom of the first sub-channel hole 21 by Selective Epitaxial Growth (SEG).
Referring to fig. 7, after the epitaxial layer 40 is formed at the bottom of the first sub-channel hole 21, an oxide layer 50 is formed on the surface of the epitaxial layer 40 away from the substrate 10. For example, the oxide layer 50 may serve as an insulating layer, which is made of oxide (oxide).
Referring to fig. 8, after forming an oxide layer 50 on the surface of the epitaxial layer 40 facing away from the substrate 10, a sacrificial layer 60 of polysilicon is formed in the first sub-channel hole 21. The sacrificial polysilicon layer 60 fills the first sub-channel hole 21 to support the subsequent formation of other stacked structures.
S400: and forming a second stacked structure 30 on a surface of the first stacked structure 20 facing away from the substrate 10, wherein the thickness of the second stacked structure 30 is a second thickness D2, and the second thickness D2 is smaller than the first thickness D1.
Referring to fig. 9, in the embodiment of the present application, the second stack structure 30 includes second insulating layers 32 and second sacrificial layers 33 alternately stacked, and the second stack structure 30 having a multi-layer structure is formed by sequentially and alternately depositing the second insulating layers 32 and the second sacrificial layers 33. The second insulating layer 32 and the second sacrificial layer 33 can be deposited by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Plasma-enhanced CVD (PECVD), Sputtering (Sputtering), Metal-organic Chemical vapor deposition (MOCVD), and Atomic Layer Deposition (ALD), and the second stacked structure 30 can be formed by selecting a deposition method according to actual requirements. Note that, in the second stacked structure 30, a layer on top of the second stacked structure 30 is the second insulating layer 32.
Further, the second stack structure 30 has the same number of stacked layers as the first stack structure 20.
It is understood that the thickness of the second stack structure 30 is the sum of the layer thicknesses of the multilayer layer structures of the second stack structure 30, in other words, the second thickness D2 is the sum of the layer thicknesses of the second insulating layer 32 and the second sacrificial layer 33 in the second stack structure 30. In the embodiment of the present application, the second thickness D2 of the second stacked structure is smaller than the first thickness D1 of the first stacked structure 20, which is beneficial for the subsequent processes to be performed smoothly, and will be described in further detail below.
S500: the second stack structure 30 is etched at a position of the second stack structure 30 aligned with the first sub-channel hole 21 to form a second sub-channel hole 31 penetrating the second stack structure 30, wherein a bottom of the second sub-channel hole 31 communicates with a top of the first sub-channel hole 21.
Referring to fig. 10, in the embodiment of the present disclosure, the etching method for etching the second sub-channel hole 31 may be dry etching or wet etching, and the second stack structure 30 is etched until the second sub-channel hole 31 formed by etching exposes the first sub-channel hole 21. The second sub-channel hole 31 extends from a surface of the second stacked structure 30 facing away from the first stacked structure 20 into the first sub-channel hole 21, and a portion of the second sub-channel hole 31 is located in the first sub-channel hole 21. In other words, the second sub-channel hole 31 is a through hole penetrating the first stacked structure 20, and is another portion of a channel hole finally used to form the memory cell string.
In step S500, a plurality of second sub-channel holes 31 may be formed simultaneously. The number, size and arrangement of the second sub-channel holes 31 are not particularly limited in the embodiments of the present application. That is, the second sub-channel holes 31 shown in fig. 11 are only examples and are not intended to limit the positions and the number of the second sub-channel holes 31.
Specifically, the second sub-channel hole 31 has an inverted trapezoid-shaped channel sidewall structure with a larger top pore diameter and a smaller bottom pore diameter than the bottom pore diameter. Of course, in other embodiments, the inclination of the sidewall of the second sub-channel hole 31 may be adjusted by adjusting the etching process parameters or by using a high aspect ratio etching process. This is not specifically limited by the present application.
The second sub-channel hole 31 is formed in the second stacked structure 30 and penetrates through the second stacked structure 30, and the second stacked structure 30 is formed by continuously stacking the second insulating layer 32 and the second sacrificial layer 33, i.e., the depth of the second sub-channel hole 31 is determined by the sum of the layer thicknesses of the second insulating layer 32 and the second sacrificial layer 33 of the second stacked structure 30, and the sum of the layer thicknesses of the second insulating layer 32 and the second sacrificial layer 33 is the thickness of the second stacked structure 30, i.e., the depth of the second sub-channel hole 31 is determined by the thickness of the second stacked structure 30. Also, since the inclination degree of the second sub-channel hole 31 is related to the thickness of the second stack structure 30, the inclination degree becomes more and more severe as the thickness of the second stack structure 30 increases.
Therefore, the second thickness D2 of the second stacked structure 30 is smaller than the first thickness D1 of the first stacked structure 20, which is equivalent to reducing the etching depth of the second sub-channel hole 31, so as to greatly reduce the inclination risk of the second sub-channel hole 31, facilitate the alignment of the second sub-channel hole 31 and the first sub-channel hole 21, and improve the inclination and appearance of the subsequently formed channel hole.
Referring to fig. 11, after the second stack structure 30 is etched at a position of the second stack structure 30 aligned with the first sub-channel hole 21 to form a second sub-channel hole 31 penetrating the second stack structure 30, the polysilicon sacrificial layer 60 is removed to make the second sub-channel hole 31 penetrate the first sub-channel hole 21 to form a channel hole 70. To ensure complete removal of the polysilicon sacrificial layer 60 from the first sub-channel hole 21, the bottom critical dimension of the second sub-channel hole 22 is set larger than the bottom critical dimension of the second sub-channel hole 31, and the top critical dimension of the second sub-channel hole 31 is set larger than the bottom critical dimension of the second sub-channel hole 31, such that the top critical dimension T2 of the second sub-channel hole 31 is larger than the top critical dimension T1 of the first sub-channel hole 21, and the bottom critical dimension B2 of the second sub-channel hole 31 is larger than the bottom critical dimension B1 of the second sub-channel hole 31. This situation may cause that when the sacrificial material (the first sacrificial layer 23 and the second sacrificial layer 33) is subsequently removed to fill the high conductive material such as metal tungsten to form the gate, the space of the first sub-channel hole 21 filled with metal tungsten is narrower than the space of the second sub-channel hole 31, which further increases the probability of causing the filling gap or the filling path to be blocked, and thus, a larger leakage current is easily generated, which affects the electrical performance of the three-dimensional memory 100, and even affects the smooth performance of the subsequent process.
Therefore, the second thickness D2 of the second stacked structure 30 is smaller than the first thickness D1 of the first stacked structure 20, which is equivalent to reducing the etching depth of the second sub-channel hole 31, avoiding the sidewall damage caused by the subsequent etching of the bottom of the channel hole 70, and improving the electrical performance of the three-dimensional memory 100 and the yield of the three-dimensional memory 100.
Referring to FIG. 12, after removing the polysilicon sacrificial layer 60 to form the channel hole 70 by making the second sub-channel hole 31 and the first sub-channel hole 21 communicate with each other, a blocking layer 81, a storage layer 82, a tunneling layer 83 and a channel layer 84 are sequentially deposited on the bottom and sidewalls of the channel hole 70.
Specifically, the blocking layer 81, the memory layer 82, the tunneling layer 83, and the channel layer 84 may be sequentially formed on the sidewall of the channel hole 70 by ALD, CVD, PVD, or any other suitable process to form an Oxide-Nitride-Oxide-polysilicon (ONOP) structure.
As shown in fig. 12, a blocking layer 81 is formed between the memory layer 82 and the sidewall of the channel hole 70 for blocking the outflow of the electron charges. The storage layer 82 is formed between the tunneling layer 83 and the blocking layer 81, and may allow electrons or holes from the channel layer 84 to tunnel through the tunneling layer 83 to the storage layer 82 to store electron charges (electrons or holes) for a storage operation. The storage or removal of charge in the storage layer 82 may affect the on/off state and/or conductance of the semiconductor channel. A tunneling layer 83 is formed between the channel layer 84 and the storage layer 82 for tunneling electron charges (electrons or holes). The channel layer 84 is formed on a sidewall of the tunneling layer 83, and the channel layer 84 is a polysilicon layer.
The three-dimensional memory 100 of the present application can form a through channel hole by providing the first sub-channel hole 21 in the first stacked structure 20 and providing the second sub-channel hole 31 in the second stacked structure 30 such that the second sub-channel hole 31 communicates with the first sub-channel hole 21. Compared with the channel holes formed by single etching with high stacking thickness, the stacking thickness of the first stacking structure 20 and the second stacking structure 30 formed by stacking respectively is low, on one hand, the etching depth required for etching the first sub-channel hole 21 and the second sub-channel hole 31 can be correspondingly reduced, and further the etching depth-to-width ratio of the first sub-channel hole 21 and the second sub-channel hole 31 is reduced, so that the contour distortion of the first sub-channel hole 21 and the second sub-channel hole 31 is improved, and the contour form of the channel holes is ensured to be normal after the first sub-channel hole 21 and the second sub-channel hole 31 are communicated to form the channel holes. On the other hand, the thickness of the second stacked structure 30 is smaller than that of the first stacked structure 20, which is equivalent to reducing the etching depth of the second sub-channel hole 31, so that the risk of inclination of the second sub-channel hole 31 is greatly reduced, the inclination of the subsequently formed channel hole is improved, sidewall damage caused by subsequent etching on the bottom of the channel hole is avoided, and the electrical performance of the three-dimensional memory 100 and the yield of the three-dimensional memory 100 are improved.
The foregoing is illustrative of the present invention and it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and are intended to be within the scope of the invention.
Claims (11)
1. The three-dimensional memory is characterized by comprising a substrate, a first stacked structure and a second stacked structure, wherein the first stacked structure and the second stacked structure are sequentially stacked on the substrate;
the first stacking structure is arranged on the stacking surface of the substrate and is provided with a first sub-channel hole which penetrates through the first stacking structure and is in contact with the substrate;
the second stacking structure is arranged on the surface, away from the substrate, of the first stacking structure, and is provided with a second sub-channel hole which penetrates through the second stacking structure and is communicated with the first sub-channel hole;
the top critical dimension of the second sub-channel hole is larger than the top critical dimension of the first sub-channel hole, and the bottom critical dimension of the second sub-channel hole is larger than the bottom critical dimension of the first sub-channel hole.
2. The three-dimensional memory according to claim 1, wherein the thickness of the first stacked structure is a first thickness, the thickness of the second stacked structure is a second thickness, and a ratio of the first thickness to the second thickness is between 1.1 and 1.3.
3. The three-dimensional memory according to claim 2, wherein the first stack structure has the same number of stacked layers as the second stack structure.
4. The three-dimensional memory according to claim 2, wherein the first stacked structure comprises first insulating layers and first gate layers alternately stacked.
5. The three-dimensional memory according to claim 4, wherein the second stacked structure comprises second insulating layers and second gate layers alternately stacked.
6. The three-dimensional memory according to claim 5, wherein the thickness of the first insulating layer is a third thickness, the thickness of the second insulating layer is a fourth thickness, and the third thickness is equal to the fourth thickness.
7. The three-dimensional memory of claim 6, wherein a thickness of the first gate layer is a fifth thickness and a thickness of the second gate layer is a sixth thickness, the sixth thickness being less than the fifth thickness.
8. The three-dimensional memory according to claim 7, wherein the thickness range of the fifth thickness is
The thickness range of the sixth thickness is
9. A preparation method of a three-dimensional memory is characterized by comprising the following steps:
providing a substrate, wherein the substrate has a stacking face;
forming a first stacked structure on the stacked surface of the substrate;
etching the first stacked structure to form a first sub-channel hole penetrating through the first stacked structure;
forming a second stacked structure on a surface of the first stacked structure facing away from the substrate;
the second stack structure is aligned with the first sub-channel hole, the second stack structure is etched at the position of the first sub-channel hole to form a second sub-channel hole penetrating through the second stack structure, wherein the bottom of the second sub-channel hole is communicated with the top of the first sub-channel hole, the top critical dimension of the second sub-channel hole is larger than that of the first sub-channel hole, and the bottom critical dimension of the second sub-channel hole is larger than that of the second sub-channel hole.
10. The method of manufacturing a three-dimensional memory according to claim 9, wherein after the "etching the first stacked structure to form the first sub-channel hole penetrating the first stacked structure" and before the "forming the second stacked structure at a surface of the first stacked structure facing away from the substrate", the method of manufacturing a three-dimensional memory includes:
and forming a polycrystalline silicon sacrificial layer in the first sub-channel hole.
11. The method of claim 10, wherein after the etching the second stack structure at a position of the second stack structure aligned with the first sub-channel hole to form the second sub-channel hole penetrating the second stack structure, the method comprises:
removing the polysilicon sacrificial layer to enable the second sub-channel hole to be communicated with the first sub-channel hole to form a channel hole;
and depositing a blocking layer, a storage layer, a tunneling layer and a channel layer on the bottom and the side wall of the channel hole in sequence.
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